Line Coverage for Module :
spid_jedec
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 47 | 47 | 100.00 |
| CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
| ALWAYS | 73 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| ALWAYS | 83 | 4 | 4 | 100.00 |
| ALWAYS | 91 | 5 | 5 | 100.00 |
| ALWAYS | 101 | 8 | 8 | 100.00 |
| ALWAYS | 121 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 125 | 1 | 1 | 100.00 |
| ALWAYS | 132 | 3 | 3 | 100.00 |
| ALWAYS | 138 | 16 | 16 | 100.00 |
64 logic unused_cmd_info;
65 1/1 assign unused_cmd_info = ^{cmd_info_i , cmd_info_idx_i};
Tests: T1 T2 T3
66
67 //////////////
68 // Datapath //
69 //////////////
70
71 // Jedec latch
72 always_ff @(posedge clk_i or negedge rst_ni) begin
73 2/2 if (!rst_ni) jedec <= '{default: '0};
Tests: T1 T2 T3 | T1 T2 T3
74 2/2 else if (cmd_sync_pulse_i) jedec <= sys_jedec_i;
Tests: T6 T13 T14 | T6 T13 T14
MISSING_ELSE
75 end
76
77 // If num_cc is non-zero, the logic shall return CC first
78 logic cc_needed;
79 1/1 assign cc_needed = |jedec.num_cc;
Tests: T1 T2 T3
80
81 logic [7:0] cc_count;
82 always_ff @(posedge clk_i or negedge rst_ni) begin
83 2/2 if (!rst_ni) cc_count <= '0;
Tests: T1 T2 T3 | T1 T2 T3
84 1/1 else if (st_q == StCC && outclk_p2s_sent_i) begin
Tests: T6 T13 T14
85 1/1 cc_count <= cc_count + 1'b 1;
Tests: T18 T42 T69
86 end
MISSING_ELSE
87 end
88
89 // Output to Parallel-to-Serial
90 always_ff @(posedge clk_out_i or negedge rst_out_ni) begin
91 1/1 if (!rst_out_ni) begin
Tests: T1 T2 T3
92 1/1 outclk_p2s_valid_o <= 1'b 0;
Tests: T1 T2 T3
93 1/1 outclk_p2s_byte_o <= 8'h 0;
Tests: T1 T2 T3
94 end else begin
95 1/1 outclk_p2s_valid_o <= p2s_valid;
Tests: T6 T13 T14
96 1/1 outclk_p2s_byte_o <= p2s_byte;
Tests: T6 T13 T14
97 end
98 end
99
100 always_comb begin : p2s_byte_logic
101 1/1 p2s_byte = 8'h 0;
Tests: T1 T2 T3
102
103 1/1 if (st_q == StIdle) begin
Tests: T1 T2 T3
104 // Manufacturer ID always
105 1/1 p2s_byte = (cc_needed) ? jedec.cc : jedec.jedec_id;
Tests: T1 T2 T3
106 1/1 end else if (st_q == StCC) begin
Tests: T18 T82 T42
107 1/1 p2s_byte = jedec.cc;
Tests: T18 T42 T69
108 1/1 end else if (st_q == StJedecId) begin
Tests: T18 T82 T42
109 1/1 p2s_byte = jedec.jedec_id;
Tests: T18 T82 T42
110 end else begin
111 // based on byte_sel_q
112 // End of the transfer but host keep toggles SCK. Sending out 0 always
113 1/1 p2s_byte = (byte_sel_q >= 2'b 10) ? 8'h 0 :
Tests: T18 T82 T42
114 (byte_sel_q == 2'b 01) ? jedec.device_id[15:8] :
115 jedec.device_id[7:0] ;
116 end
117 end : p2s_byte_logic
118
119 // Byte selection
120 always_ff @(posedge clk_i or negedge rst_ni) begin : byte_sel_latch
121 2/2 if (!rst_ni) byte_sel_q <= 2'h 0; // select manufacturer id
Tests: T1 T2 T3 | T1 T2 T3
122 2/2 else if (next_byte) byte_sel_q <= byte_sel_d;
Tests: T6 T13 T14 | T18 T82 T42
MISSING_ELSE
123 end : byte_sel_latch
124
125 1/1 assign byte_sel_d = (byte_sel_q == 2'b 10) ? 2'b 10 : byte_sel_q + 1'b 1;
Tests: T1 T2 T3
126
127 ///////////
128 // State //
129 ///////////
130
131 always_ff @(posedge clk_i or negedge rst_ni) begin : state_latch
132 2/2 if (!rst_ni) st_q <= StIdle;
Tests: T1 T2 T3 | T1 T2 T3
133 1/1 else st_q <= st_d;
Tests: T6 T13 T14
134 end : state_latch
135
136 `ASSERT_KNOWN(JedecStKnown_A, st_q)
137 always_comb begin : next_state_logic
138 1/1 st_d = st_q;
Tests: T1 T2 T3
139
140 1/1 p2s_valid = 1'b 0;
Tests: T1 T2 T3
141 1/1 next_byte = 1'b 0;
Tests: T1 T2 T3
142
143 1/1 unique case (st_q)
Tests: T1 T2 T3
144 StIdle: begin
145 1/1 if (sel_dp_i == DpReadJEDEC) begin
Tests: T1 T2 T3
146 1/1 st_d = (cc_needed) ? StCC : StJedecId ;
Tests: T18 T82 T42
147
148 // Send out the dat
149 1/1 p2s_valid = 1'b 1;
Tests: T18 T82 T42
150 end
MISSING_ELSE
151 end
152
153 StCC: begin
154
155 // cc_count is increased by 1 when outclk_p2s_sent_i is asserted
156 // outclk_p2s_sent_i asserts at the 7th beat, not 8th beat. When
157 // cc_count reaches to num_cc, it is the end of a byte transaction in
158 // SCK input clock domain. So, that time state machine moves to
159 // JedecId
160 1/1 if (cc_count == jedec.num_cc) begin
Tests: T18 T42 T69
161 1/1 st_d = StJedecId;
Tests: T18 T42 T69
162 end
MISSING_ELSE
163
164 1/1 p2s_valid = 1'b 1;
Tests: T18 T42 T69
165 end
166
167 StJedecId: begin
168 1/1 if (outclk_p2s_sent_i) begin
Tests: T18 T82 T42
169 1/1 st_d = StDevId;
Tests: T18 T82 T42
170 end
MISSING_ELSE
171
172 1/1 p2s_valid = 1'b 1;
Tests: T18 T82 T42
173 end
174
175 StDevId: begin
176 // TERMINAL_STATE
177
178 // Sends data
179 1/1 p2s_valid = 1'b 1;
Tests: T18 T82 T42
180
181 1/1 if (outclk_p2s_sent_i) begin
Tests: T18 T82 T42
182 1/1 next_byte = 1'b 1;
Tests: T18 T82 T42
183 end
MISSING_ELSE
184 end
185
186 default: begin
187 st_d = StIdle;
Cond Coverage for Module :
spid_jedec
| Total | Covered | Percent |
|---|
| Conditions | 29 | 29 | 100.00 |
| Logical | 29 | 29 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 84
EXPRESSION ((st_q == StCC) && outclk_p2s_sent_i)
-------1------ --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T18,T82,T42 |
| 1 | 0 | Covered | T18,T42,T69 |
| 1 | 1 | Covered | T18,T42,T69 |
LINE 84
SUB-EXPRESSION (st_q == StCC)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T6,T13,T14 |
| 1 | Covered | T18,T42,T69 |
LINE 103
EXPRESSION (st_q == StIdle)
--------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T18,T82,T42 |
| 1 | Covered | T1,T2,T3 |
LINE 105
EXPRESSION (cc_needed ? jedec.cc : jedec.jedec_id)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T13,T14,T18 |
LINE 106
EXPRESSION (st_q == StCC)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T18,T82,T42 |
| 1 | Covered | T18,T42,T69 |
LINE 108
EXPRESSION (st_q == StJedecId)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T18,T82,T42 |
| 1 | Covered | T18,T82,T42 |
LINE 113
EXPRESSION ((byte_sel_q >= 2'b10) ? 8'b0 : ((byte_sel_q == 2'b1) ? jedec.device_id[15:8] : jedec.device_id[7:0]))
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T18,T82,T42 |
| 1 | Covered | T18,T82,T42 |
LINE 113
SUB-EXPRESSION ((byte_sel_q == 2'b1) ? jedec.device_id[15:8] : jedec.device_id[7:0])
----------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T18,T82,T42 |
| 1 | Covered | T18,T82,T42 |
LINE 113
SUB-EXPRESSION (byte_sel_q == 2'b1)
----------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T18,T82,T42 |
| 1 | Covered | T18,T82,T42 |
LINE 125
EXPRESSION ((byte_sel_q == 2'b10) ? 2'b10 : ((byte_sel_q + 1'b1)))
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T18,T82,T42 |
LINE 125
SUB-EXPRESSION (byte_sel_q == 2'b10)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T18,T82,T42 |
LINE 145
EXPRESSION (sel_dp_i == DpReadJEDEC)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T18,T82,T42 |
LINE 146
EXPRESSION (cc_needed ? StCC : StJedecId)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T82,T42,T55 |
| 1 | Covered | T18,T42,T69 |
LINE 160
EXPRESSION (cc_count == jedec.num_cc)
-------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T18,T42,T69 |
| 1 | Covered | T18,T42,T69 |
FSM Coverage for Module :
spid_jedec
Summary for FSM :: st_q
| Total | Covered | Percent | |
| States |
4 |
4 |
100.00 |
(Not included in score) |
| Transitions |
4 |
4 |
100.00 |
|
| Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: st_q
| states | Line No. | Covered | Tests |
| StCC |
146 |
Covered |
T18,T42,T69 |
| StDevId |
169 |
Covered |
T18,T82,T42 |
| StIdle |
103 |
Covered |
T1,T2,T3 |
| StJedecId |
146 |
Covered |
T18,T82,T42 |
| transitions | Line No. | Covered | Tests |
| StCC->StJedecId |
161 |
Covered |
T18,T42,T69 |
| StIdle->StCC |
146 |
Covered |
T18,T42,T69 |
| StIdle->StJedecId |
146 |
Covered |
T82,T42,T55 |
| StJedecId->StDevId |
169 |
Covered |
T18,T82,T42 |
Branch Coverage for Module :
spid_jedec
| Line No. | Total | Covered | Percent |
| Branches |
|
32 |
31 |
96.88 |
| TERNARY |
125 |
2 |
2 |
100.00 |
| IF |
73 |
3 |
3 |
100.00 |
| IF |
83 |
3 |
3 |
100.00 |
| IF |
91 |
2 |
2 |
100.00 |
| IF |
103 |
7 |
7 |
100.00 |
| IF |
121 |
3 |
3 |
100.00 |
| IF |
132 |
2 |
2 |
100.00 |
| CASE |
143 |
10 |
9 |
90.00 |
125 assign byte_sel_d = (byte_sel_q == 2'b 10) ? 2'b 10 : byte_sel_q + 1'b 1;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T18,T82,T42 |
| 0 |
Covered |
T1,T2,T3 |
73 if (!rst_ni) jedec <= '{default: '0};
-1-
==>
74 else if (cmd_sync_pulse_i) jedec <= sys_jedec_i;
-2-
==>
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T6,T13,T14 |
| 0 |
0 |
Covered |
T6,T13,T14 |
83 if (!rst_ni) cc_count <= '0;
-1-
==>
84 else if (st_q == StCC && outclk_p2s_sent_i) begin
-2-
85 cc_count <= cc_count + 1'b 1;
==>
86 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T18,T42,T69 |
| 0 |
0 |
Covered |
T6,T13,T14 |
91 if (!rst_out_ni) begin
-1-
92 outclk_p2s_valid_o <= 1'b 0;
==>
93 outclk_p2s_byte_o <= 8'h 0;
94 end else begin
95 outclk_p2s_valid_o <= p2s_valid;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T6,T13,T14 |
103 if (st_q == StIdle) begin
-1-
104 // Manufacturer ID always
105 p2s_byte = (cc_needed) ? jedec.cc : jedec.jedec_id;
-2-
==>
==>
106 end else if (st_q == StCC) begin
-3-
107 p2s_byte = jedec.cc;
==>
108 end else if (st_q == StJedecId) begin
-4-
109 p2s_byte = jedec.jedec_id;
==>
110 end else begin
111 // based on byte_sel_q
112 // End of the transfer but host keep toggles SCK. Sending out 0 always
113 p2s_byte = (byte_sel_q >= 2'b 10) ? 8'h 0 :
-5-
==>
114 (byte_sel_q == 2'b 01) ? jedec.device_id[15:8] :
-6-
==>
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | Status | Tests |
| 1 |
1 |
- |
- |
- |
- |
Covered |
T13,T14,T18 |
| 1 |
0 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
- |
1 |
- |
- |
- |
Covered |
T18,T42,T69 |
| 0 |
- |
0 |
1 |
- |
- |
Covered |
T18,T82,T42 |
| 0 |
- |
0 |
0 |
1 |
- |
Covered |
T18,T82,T42 |
| 0 |
- |
0 |
0 |
0 |
1 |
Covered |
T18,T82,T42 |
| 0 |
- |
0 |
0 |
0 |
0 |
Covered |
T18,T82,T42 |
121 if (!rst_ni) byte_sel_q <= 2'h 0; // select manufacturer id
-1-
==>
122 else if (next_byte) byte_sel_q <= byte_sel_d;
-2-
==>
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T18,T82,T42 |
| 0 |
0 |
Covered |
T6,T13,T14 |
132 if (!rst_ni) st_q <= StIdle;
-1-
==>
133 else st_q <= st_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T6,T13,T14 |
143 unique case (st_q)
-1-
144 StIdle: begin
145 if (sel_dp_i == DpReadJEDEC) begin
-2-
146 st_d = (cc_needed) ? StCC : StJedecId ;
-3-
==>
==>
147
148 // Send out the dat
149 p2s_valid = 1'b 1;
150 end
MISSING_ELSE
==>
151 end
152
153 StCC: begin
154
155 // cc_count is increased by 1 when outclk_p2s_sent_i is asserted
156 // outclk_p2s_sent_i asserts at the 7th beat, not 8th beat. When
157 // cc_count reaches to num_cc, it is the end of a byte transaction in
158 // SCK input clock domain. So, that time state machine moves to
159 // JedecId
160 if (cc_count == jedec.num_cc) begin
-4-
161 st_d = StJedecId;
==>
162 end
MISSING_ELSE
==>
163
164 p2s_valid = 1'b 1;
165 end
166
167 StJedecId: begin
168 if (outclk_p2s_sent_i) begin
-5-
169 st_d = StDevId;
==>
170 end
MISSING_ELSE
==>
171
172 p2s_valid = 1'b 1;
173 end
174
175 StDevId: begin
176 // TERMINAL_STATE
177
178 // Sends data
179 p2s_valid = 1'b 1;
180
181 if (outclk_p2s_sent_i) begin
-6-
182 next_byte = 1'b 1;
==>
183 end
MISSING_ELSE
==>
184 end
185
186 default: begin
187 st_d = StIdle;
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | Status | Tests |
| StIdle |
1 |
1 |
- |
- |
- |
Covered |
T18,T42,T69 |
| StIdle |
1 |
0 |
- |
- |
- |
Covered |
T82,T42,T55 |
| StIdle |
0 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| StCC |
- |
- |
1 |
- |
- |
Covered |
T18,T42,T69 |
| StCC |
- |
- |
0 |
- |
- |
Covered |
T18,T42,T69 |
| StJedecId |
- |
- |
- |
1 |
- |
Covered |
T18,T82,T42 |
| StJedecId |
- |
- |
- |
0 |
- |
Covered |
T18,T82,T42 |
| StDevId |
- |
- |
- |
- |
1 |
Covered |
T18,T82,T42 |
| StDevId |
- |
- |
- |
- |
0 |
Covered |
T18,T82,T42 |
| default |
- |
- |
- |
- |
- |
Not Covered |
|
Assert Coverage for Module :
spid_jedec
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
JedecStKnown_A |
151971634 |
121758958 |
0 |
0 |
JedecStKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
151971634 |
121758958 |
0 |
0 |
| T6 |
6240 |
6240 |
0 |
0 |
| T12 |
7219 |
0 |
0 |
0 |
| T13 |
32 |
32 |
0 |
0 |
| T14 |
10634 |
10634 |
0 |
0 |
| T15 |
360 |
0 |
0 |
0 |
| T16 |
184 |
0 |
0 |
0 |
| T17 |
17487 |
0 |
0 |
0 |
| T18 |
20388 |
19990 |
0 |
0 |
| T19 |
19830 |
19536 |
0 |
0 |
| T20 |
55532 |
55232 |
0 |
0 |
| T21 |
0 |
24272 |
0 |
0 |
| T23 |
0 |
34464 |
0 |
0 |
| T24 |
0 |
62324 |
0 |
0 |
| T25 |
0 |
18795 |
0 |
0 |