Unified Coverage Report :: Module

Module : prim_edge_detector

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_intr_upload_edge	100.00	100.00				100.00
tb.dut.u_readcmd.u_addr_latch_pulse	100.00	100.00	100.00			100.00
tb.dut.u_spi_tpm.u_csb_sync_rst	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_intr_upload_edge

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.52	95.20	84.31	97.00		90.62	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_readcmd.u_addr_latch_pulse

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.19	96.32	100.00		80.00	84.62	100.00	u_readcmd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_spi_tpm.u_csb_sync_rst

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.79	99.29	91.20		91.67	96.77	100.00	u_spi_tpm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
g_sync.u_sync	100.00	100.00				100.00

Line Coverage for Module : prim_edge_detector ( parameter Width=2,ResetValue=0,EnSync=0 + Width=1,ResetValue=0,EnSync=0 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_intr_upload_edge

SCORE	LINE
100.00	100.00

tb.dut.u_readcmd.u_addr_latch_pulse

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	42	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
ALWAYS	48	3	3	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	53	1	1	100.00



41                        else begin : g_nosync
42         1/1              assign q_sync_d = d_i;
           Tests:       T1 T2 T3 
43                        end : g_nosync
44                      
45         1/1            assign q_sync_o = q_sync_d;
           Tests:       T1 T2 T3 
46                      
47                        always_ff @(posedge clk_i or negedge rst_ni) begin
48         2/2              if (!rst_ni) q_sync_q <= ResetValue;
           Tests:       T1 T2 T3  | T1 T2 T3 
49         1/1              else         q_sync_q <= q_sync_d;
           Tests:       T1 T2 T3 
50                        end
51                      
52         1/1            assign q_posedge_pulse_o = q_sync_d & ~q_sync_q;
           Tests:       T1 T2 T3 
53         1/1            assign q_negedge_pulse_o = ~q_sync_d & q_sync_q;
           Tests:       T1 T2 T3

Line Coverage for Module : prim_edge_detector ( parameter Width=1,ResetValue=0,EnSync=1 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_spi_tpm.u_csb_sync_rst

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	45	1	1	100.00
ALWAYS	48	3	3	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	53	1	1	100.00



44                      
45         1/1            assign q_sync_o = q_sync_d;
           Tests:       T1 T2 T3 
46                      
47                        always_ff @(posedge clk_i or negedge rst_ni) begin
48         2/2              if (!rst_ni) q_sync_q <= ResetValue;
           Tests:       T1 T2 T3  | T1 T2 T3 
49         1/1              else         q_sync_q <= q_sync_d;
           Tests:       T1 T2 T3 
50                        end
51                      
52         1/1            assign q_posedge_pulse_o = q_sync_d & ~q_sync_q;
           Tests:       T1 T2 T3 
53         1/1            assign q_negedge_pulse_o = ~q_sync_d & q_sync_q;
           Tests:       T1 T2 T3

Cond Coverage for Module : prim_edge_detector

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       52
 EXPRESSION (q_sync_d & ((~q_sync_q)))
             ----1---   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       53
 EXPRESSION (((~q_sync_d)) & q_sync_q)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

Branch Coverage for Module : prim_edge_detector

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	48	2	2	100.00



48             if (!rst_ni) q_sync_q <= ResetValue;
               -1-  
               ==>
49             else         q_sync_q <= q_sync_d;
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_intr_upload_edge

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	42	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
ALWAYS	48	3	3	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	53	1	1	100.00



41                        else begin : g_nosync
42         1/1              assign q_sync_d = d_i;
           Tests:       T1 T2 T3 
43                        end : g_nosync
44                      
45         1/1            assign q_sync_o = q_sync_d;
           Tests:       T1 T2 T3 
46                      
47                        always_ff @(posedge clk_i or negedge rst_ni) begin
48         2/2              if (!rst_ni) q_sync_q <= ResetValue;
           Tests:       T1 T2 T3  | T1 T2 T3 
49         1/1              else         q_sync_q <= q_sync_d;
           Tests:       T1 T2 T3 
50                        end
51                      
52         1/1            assign q_posedge_pulse_o = q_sync_d & ~q_sync_q;
           Tests:       T1 T2 T3 
53         1/1            assign q_negedge_pulse_o = ~q_sync_d & q_sync_q;
           Tests:       T1 T2 T3

Branch Coverage for Instance : tb.dut.u_intr_upload_edge

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	48	2	2	100.00



48             if (!rst_ni) q_sync_q <= ResetValue;
               -1-  
               ==>
49             else         q_sync_q <= q_sync_d;
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_readcmd.u_addr_latch_pulse

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	42	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
ALWAYS	48	3	3	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	53	1	1	100.00



41                        else begin : g_nosync
42         1/1              assign q_sync_d = d_i;
           Tests:       T1 T2 T3 
43                        end : g_nosync
44                      
45         1/1            assign q_sync_o = q_sync_d;
           Tests:       T1 T2 T3 
46                      
47                        always_ff @(posedge clk_i or negedge rst_ni) begin
48         2/2              if (!rst_ni) q_sync_q <= ResetValue;
           Tests:       T1 T2 T3  | T1 T2 T3 
49         1/1              else         q_sync_q <= q_sync_d;
           Tests:       T6 T13 T14 
50                        end
51                      
52         1/1            assign q_posedge_pulse_o = q_sync_d & ~q_sync_q;
           Tests:       T1 T2 T3 
53         1/1            assign q_negedge_pulse_o = ~q_sync_d & q_sync_q;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_readcmd.u_addr_latch_pulse

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       52
 EXPRESSION (q_sync_d & ((~q_sync_q)))
             ----1---   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T6,T18,T19
1	0	Covered	T6,T13,T14
1	1	Covered	T1,T2,T3

 LINE       53
 EXPRESSION (((~q_sync_d)) & q_sync_q)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T6,T13,T14
1	0	Covered	T6,T18,T19
1	1	Covered	T6,T18,T19

Branch Coverage for Instance : tb.dut.u_readcmd.u_addr_latch_pulse

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	48	2	2	100.00



48             if (!rst_ni) q_sync_q <= ResetValue;
               -1-  
               ==>
49             else         q_sync_q <= q_sync_d;
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T6,T13,T14

Line Coverage for Instance : tb.dut.u_spi_tpm.u_csb_sync_rst

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	45	1	1	100.00
ALWAYS	48	3	3	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	53	1	1	100.00



44                      
45         1/1            assign q_sync_o = q_sync_d;
           Tests:       T1 T2 T3 
46                      
47                        always_ff @(posedge clk_i or negedge rst_ni) begin
48         2/2              if (!rst_ni) q_sync_q <= ResetValue;
           Tests:       T1 T2 T3  | T1 T2 T3 
49         1/1              else         q_sync_q <= q_sync_d;
           Tests:       T1 T2 T3 
50                        end
51                      
52         1/1            assign q_posedge_pulse_o = q_sync_d & ~q_sync_q;
           Tests:       T1 T2 T3 
53         1/1            assign q_negedge_pulse_o = ~q_sync_d & q_sync_q;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_csb_sync_rst

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       52
 EXPRESSION (q_sync_d & ((~q_sync_q)))
             ----1---   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       53
 EXPRESSION (((~q_sync_d)) & q_sync_q)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_csb_sync_rst

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	48	2	2	100.00



48             if (!rst_ni) q_sync_q <= ResetValue;
               -1-  
               ==>
49             else         q_sync_q <= q_sync_d;
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3