Module Definition
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Module : prim_pulse_sync
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_flash_readbuf_watermark_pulse_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_flash_readbuf_flip_pulse_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_upload.u_payloadptr_clr_psync 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.52 95.20 84.31 97.00 90.62 95.45 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00


Module Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.52 95.20 84.31 97.00 90.62 95.45 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00


Module Instance : tb.dut.u_upload.u_payloadptr_clr_psync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.37 100.00 86.11 100.00 95.74 100.00 u_upload


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00

Line Coverage for Module : prim_pulse_sync
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00


30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
32         1/1                src_level <= 1'b0;
           Tests:       T1 T2 T3 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T3 T4 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T1 T2 T3 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3 
Cond Coverage for Module : prim_pulse_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT3,T4,T6
01CoveredT19,T25,T51
10CoveredT19,T25,T51
11CoveredT19,T25,T51 

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT19,T25,T51
10CoveredT19,T25,T51
11CoveredT19,T25,T51
Branch Coverage for Module : prim_pulse_sync
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00 



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T3,T4,T6 



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Assert Coverage for Module : prim_pulse_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1359396522 2920 0 0
SrcPulseCheck_M 455914902 2920 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1359396522 2920 0 0
T19 47598 7 0 0
T20 116626 0 0 0
T21 30258 0 0 0
T22 3564 0 0 0
T25 0 7 0 0
T27 3136 0 0 0
T28 597652 0 0 0
T31 15366 0 0 0
T40 9866 0 0 0
T41 0 2 0 0
T42 0 16 0 0
T45 5304 0 0 0
T46 176935 4 0 0
T47 385803 0 0 0
T51 0 4 0 0
T52 0 7 0 0
T53 0 6 0 0
T54 0 6 0 0
T55 0 9 0 0
T57 0 2 0 0
T58 387327 3 0 0
T69 0 13 0 0
T70 307186 0 0 0
T76 3173 0 0 0
T77 89616 0 0 0
T78 1336 0 0 0
T79 403942 0 0 0
T80 50440 7 0 0
T81 233320 0 0 0
T82 0 3 0 0
T93 0 20 0 0
T100 1942 0 0 0
T124 0 7 0 0
T168 0 2 0 0
T169 0 2 0 0
T170 0 7 0 0
T171 0 2 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 455914902 2920 0 0
T19 39660 7 0 0
T20 111064 0 0 0
T21 48544 0 0 0
T23 69862 0 0 0
T24 125394 0 0 0
T25 37590 7 0 0
T26 87248 0 0 0
T27 288 0 0 0
T28 175620 0 0 0
T29 7546 0 0 0
T41 0 2 0 0
T42 0 16 0 0
T46 141556 4 0 0
T47 62477 0 0 0
T51 0 4 0 0
T52 0 7 0 0
T53 0 6 0 0
T54 0 6 0 0
T55 0 9 0 0
T57 0 2 0 0
T58 77204 3 0 0
T69 0 13 0 0
T70 42231 0 0 0
T76 792 0 0 0
T77 14326 0 0 0
T78 1264 0 0 0
T79 49287 0 0 0
T80 14400 7 0 0
T81 53721 0 0 0
T82 0 3 0 0
T93 0 20 0 0
T124 0 7 0 0
T168 0 2 0 0
T169 0 2 0 0
T170 0 7 0 0
T171 0 2 0 0

Line Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00


30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
32         1/1                src_level <= 1'b0;
           Tests:       T1 T2 T3 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T3 T4 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T1 T2 T3 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT3,T4,T6
01CoveredT19,T25,T51
10CoveredT19,T25,T51
11CoveredT19,T25,T51 

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT19,T25,T51
10CoveredT19,T25,T51
11CoveredT19,T25,T51
Branch Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00 



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T3,T4,T6 



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 453132174 162 0 0
SrcPulseCheck_M 151971634 162 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 453132174 162 0 0
T19 23799 2 0 0
T20 58313 0 0 0
T21 15129 0 0 0
T22 1782 0 0 0
T25 0 2 0 0
T27 1568 0 0 0
T28 298826 0 0 0
T31 7683 0 0 0
T40 4933 0 0 0
T41 0 1 0 0
T45 2652 0 0 0
T51 0 2 0 0
T52 0 2 0 0
T80 0 2 0 0
T100 971 0 0 0
T124 0 2 0 0
T168 0 1 0 0
T170 0 2 0 0
T171 0 2 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 151971634 162 0 0
T19 19830 2 0 0
T20 55532 0 0 0
T21 24272 0 0 0
T23 34931 0 0 0
T24 62697 0 0 0
T25 18795 2 0 0
T26 43624 0 0 0
T27 144 0 0 0
T28 87810 0 0 0
T29 3773 0 0 0
T41 0 1 0 0
T51 0 2 0 0
T52 0 2 0 0
T80 0 2 0 0
T124 0 2 0 0
T168 0 1 0 0
T170 0 2 0 0
T171 0 2 0 0

Line Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00


30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
32         1/1                src_level <= 1'b0;
           Tests:       T1 T2 T3 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T3 T4 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T1 T2 T3 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT3,T4,T6
01CoveredT19,T25,T51
10CoveredT19,T25,T51
11CoveredT19,T25,T51 

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT19,T25,T51
10CoveredT19,T25,T51
11CoveredT19,T25,T51
Branch Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00 



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T3,T4,T6 



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 453132174 308 0 0
SrcPulseCheck_M 151971634 308 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 453132174 308 0 0
T19 23799 5 0 0
T20 58313 0 0 0
T21 15129 0 0 0
T22 1782 0 0 0
T25 0 5 0 0
T27 1568 0 0 0
T28 298826 0 0 0
T31 7683 0 0 0
T40 4933 0 0 0
T41 0 1 0 0
T45 2652 0 0 0
T51 0 2 0 0
T52 0 5 0 0
T80 0 5 0 0
T100 971 0 0 0
T124 0 5 0 0
T168 0 1 0 0
T169 0 2 0 0
T170 0 5 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 151971634 308 0 0
T19 19830 5 0 0
T20 55532 0 0 0
T21 24272 0 0 0
T23 34931 0 0 0
T24 62697 0 0 0
T25 18795 5 0 0
T26 43624 0 0 0
T27 144 0 0 0
T28 87810 0 0 0
T29 3773 0 0 0
T41 0 1 0 0
T51 0 2 0 0
T52 0 5 0 0
T80 0 5 0 0
T124 0 5 0 0
T168 0 1 0 0
T169 0 2 0 0
T170 0 5 0 0

Line Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00


30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
32         1/1                src_level <= 1'b0;
           Tests:       T1 T2 T3 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T3 T4 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T1 T2 T3 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT3,T4,T6
01CoveredT46,T58,T53
10CoveredT46,T58,T53
11CoveredT46,T58,T53 

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT46,T58,T53
10CoveredT46,T58,T53
11CoveredT46,T58,T53
Branch Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00 



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T3,T4,T6 



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 453132174 2450 0 0
SrcPulseCheck_M 151971634 2450 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 453132174 2450 0 0
T42 0 16 0 0
T46 176935 4 0 0
T47 385803 0 0 0
T53 0 6 0 0
T54 0 6 0 0
T55 0 9 0 0
T57 0 2 0 0
T58 387327 3 0 0
T69 0 13 0 0
T70 307186 0 0 0
T76 3173 0 0 0
T77 89616 0 0 0
T78 1336 0 0 0
T79 403942 0 0 0
T80 50440 0 0 0
T81 233320 0 0 0
T82 0 3 0 0
T93 0 20 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 151971634 2450 0 0
T42 0 16 0 0
T46 141556 4 0 0
T47 62477 0 0 0
T53 0 6 0 0
T54 0 6 0 0
T55 0 9 0 0
T57 0 2 0 0
T58 77204 3 0 0
T69 0 13 0 0
T70 42231 0 0 0
T76 792 0 0 0
T77 14326 0 0 0
T78 1264 0 0 0
T79 49287 0 0 0
T80 14400 0 0 0
T81 53721 0 0 0
T82 0 3 0 0
T93 0 20 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%