Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	455442118	3053594	0	0
DataKnown_AKnownEnable	455442118	455312318	0	0
DepthKnown_A	455442118	455312318	0	0
RvalidKnown_A	455442118	455312318	0	0
WreadyKnown_A	455442118	455312318	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455442118	3053594	0	0
T5	3191	100	0	0
T6	9154	832	0	0
T7	1029	0	0	0
T8	1202	0	0	0
T9	1093	0	0	0
T10	2692	100	0	0
T11	5867	0	0	0
T12	60544	0	0	0
T13	2780	1663	0	0
T14	88419	1671	0	0
T18	0	832	0	0
T19	0	832	0	0
T20	0	832	0	0
T21	0	832	0	0
T45	0	100	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	455442118	455312318	0	0
T1	1596	1540	0	0
T2	1231	1140	0	0
T3	2908	2842	0	0
T4	2964	2889	0	0
T5	3191	3103	0	0
T6	9154	9068	0	0
T7	1029	943	0	0
T8	1202	1148	0	0
T9	1093	1014	0	0
T10	2692	2631	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455442118	455312318	0	0
T1	1596	1540	0	0
T2	1231	1140	0	0
T3	2908	2842	0	0
T4	2964	2889	0	0
T5	3191	3103	0	0
T6	9154	9068	0	0
T7	1029	943	0	0
T8	1202	1148	0	0
T9	1093	1014	0	0
T10	2692	2631	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455442118	455312318	0	0
T1	1596	1540	0	0
T2	1231	1140	0	0
T3	2908	2842	0	0
T4	2964	2889	0	0
T5	3191	3103	0	0
T6	9154	9068	0	0
T7	1029	943	0	0
T8	1202	1148	0	0
T9	1093	1014	0	0
T10	2692	2631	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455442118	455312318	0	0
T1	1596	1540	0	0
T2	1231	1140	0	0
T3	2908	2842	0	0
T4	2964	2889	0	0
T5	3191	3103	0	0
T6	9154	9068	0	0
T7	1029	943	0	0
T8	1202	1148	0	0
T9	1093	1014	0	0
T10	2692	2631	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	455442118	3344735	0	0
DataKnown_AKnownEnable	455442118	455312318	0	0
DepthKnown_A	455442118	455312318	0	0
RvalidKnown_A	455442118	455312318	0	0
WreadyKnown_A	455442118	455312318	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455442118	3344735	0	0
T5	3191	416	0	0
T6	9154	832	0	0
T7	1029	0	0	0
T8	1202	0	0	0
T9	1093	0	0	0
T10	2692	100	0	0
T11	5867	0	0	0
T12	60544	0	0	0
T13	2780	832	0	0
T14	88419	841	0	0
T18	0	2530	0	0
T19	0	832	0	0
T20	0	832	0	0
T21	0	832	0	0
T45	0	100	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	455442118	455312318	0	0
T1	1596	1540	0	0
T2	1231	1140	0	0
T3	2908	2842	0	0
T4	2964	2889	0	0
T5	3191	3103	0	0
T6	9154	9068	0	0
T7	1029	943	0	0
T8	1202	1148	0	0
T9	1093	1014	0	0
T10	2692	2631	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455442118	455312318	0	0
T1	1596	1540	0	0
T2	1231	1140	0	0
T3	2908	2842	0	0
T4	2964	2889	0	0
T5	3191	3103	0	0
T6	9154	9068	0	0
T7	1029	943	0	0
T8	1202	1148	0	0
T9	1093	1014	0	0
T10	2692	2631	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455442118	455312318	0	0
T1	1596	1540	0	0
T2	1231	1140	0	0
T3	2908	2842	0	0
T4	2964	2889	0	0
T5	3191	3103	0	0
T6	9154	9068	0	0
T7	1029	943	0	0
T8	1202	1148	0	0
T9	1093	1014	0	0
T10	2692	2631	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455442118	455312318	0	0
T1	1596	1540	0	0
T2	1231	1140	0	0
T3	2908	2842	0	0
T4	2964	2889	0	0
T5	3191	3103	0	0
T6	9154	9068	0	0
T7	1029	943	0	0
T8	1202	1148	0	0
T9	1093	1014	0	0
T10	2692	2631	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	455442118	197280	0	0
DataKnown_AKnownEnable	455442118	455312318	0	0
DepthKnown_A	455442118	455312318	0	0
RvalidKnown_A	455442118	455312318	0	0
WreadyKnown_A	455442118	455312318	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455442118	197280	0	0
T4	2964	53	0	0
T5	3191	100	0	0
T6	9154	0	0	0
T7	1029	0	0	0
T8	1202	0	0	0
T9	1093	0	0	0
T10	2692	100	0	0
T11	5867	0	0	0
T12	60544	39	0	0
T13	2780	0	0	0
T16	0	1	0	0
T29	0	20	0	0
T45	0	100	0	0
T48	0	163	0	0
T49	0	100	0	0
T50	0	13	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	455442118	455312318	0	0
T1	1596	1540	0	0
T2	1231	1140	0	0
T3	2908	2842	0	0
T4	2964	2889	0	0
T5	3191	3103	0	0
T6	9154	9068	0	0
T7	1029	943	0	0
T8	1202	1148	0	0
T9	1093	1014	0	0
T10	2692	2631	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455442118	455312318	0	0
T1	1596	1540	0	0
T2	1231	1140	0	0
T3	2908	2842	0	0
T4	2964	2889	0	0
T5	3191	3103	0	0
T6	9154	9068	0	0
T7	1029	943	0	0
T8	1202	1148	0	0
T9	1093	1014	0	0
T10	2692	2631	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455442118	455312318	0	0
T1	1596	1540	0	0
T2	1231	1140	0	0
T3	2908	2842	0	0
T4	2964	2889	0	0
T5	3191	3103	0	0
T6	9154	9068	0	0
T7	1029	943	0	0
T8	1202	1148	0	0
T9	1093	1014	0	0
T10	2692	2631	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455442118	455312318	0	0
T1	1596	1540	0	0
T2	1231	1140	0	0
T3	2908	2842	0	0
T4	2964	2889	0	0
T5	3191	3103	0	0
T6	9154	9068	0	0
T7	1029	943	0	0
T8	1202	1148	0	0
T9	1093	1014	0	0
T10	2692	2631	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	455442118	439364	0	0
DataKnown_AKnownEnable	455442118	455312318	0	0
DepthKnown_A	455442118	455312318	0	0
RvalidKnown_A	455442118	455312318	0	0
WreadyKnown_A	455442118	455312318	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455442118	439364	0	0
T4	2964	53	0	0
T5	3191	501	0	0
T6	9154	0	0	0
T7	1029	0	0	0
T8	1202	0	0	0
T9	1093	0	0	0
T10	2692	100	0	0
T11	5867	0	0	0
T12	60544	39	0	0
T13	2780	0	0	0
T16	0	5	0	0
T29	0	78	0	0
T45	0	100	0	0
T48	0	482	0	0
T49	0	100	0	0
T50	0	61	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	455442118	455312318	0	0
T1	1596	1540	0	0
T2	1231	1140	0	0
T3	2908	2842	0	0
T4	2964	2889	0	0
T5	3191	3103	0	0
T6	9154	9068	0	0
T7	1029	943	0	0
T8	1202	1148	0	0
T9	1093	1014	0	0
T10	2692	2631	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455442118	455312318	0	0
T1	1596	1540	0	0
T2	1231	1140	0	0
T3	2908	2842	0	0
T4	2964	2889	0	0
T5	3191	3103	0	0
T6	9154	9068	0	0
T7	1029	943	0	0
T8	1202	1148	0	0
T9	1093	1014	0	0
T10	2692	2631	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455442118	455312318	0	0
T1	1596	1540	0	0
T2	1231	1140	0	0
T3	2908	2842	0	0
T4	2964	2889	0	0
T5	3191	3103	0	0
T6	9154	9068	0	0
T7	1029	943	0	0
T8	1202	1148	0	0
T9	1093	1014	0	0
T10	2692	2631	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455442118	455312318	0	0
T1	1596	1540	0	0
T2	1231	1140	0	0
T3	2908	2842	0	0
T4	2964	2889	0	0
T5	3191	3103	0	0
T6	9154	9068	0	0
T7	1029	943	0	0
T8	1202	1148	0	0
T9	1093	1014	0	0
T10	2692	2631	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	455442118	6166904	0	0
DataKnown_AKnownEnable	455442118	455312318	0	0
DepthKnown_A	455442118	455312318	0	0
RvalidKnown_A	455442118	455312318	0	0
WreadyKnown_A	455442118	455312318	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455442118	6166904	0	0
T1	1596	1	0	0
T2	1231	77	0	0
T3	2908	26	0	0
T4	2964	235	0	0
T5	3191	1	0	0
T6	9154	48	0	0
T7	1029	3	0	0
T8	1202	49	0	0
T9	1093	17	0	0
T10	2692	1	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	455442118	455312318	0	0
T1	1596	1540	0	0
T2	1231	1140	0	0
T3	2908	2842	0	0
T4	2964	2889	0	0
T5	3191	3103	0	0
T6	9154	9068	0	0
T7	1029	943	0	0
T8	1202	1148	0	0
T9	1093	1014	0	0
T10	2692	2631	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455442118	455312318	0	0
T1	1596	1540	0	0
T2	1231	1140	0	0
T3	2908	2842	0	0
T4	2964	2889	0	0
T5	3191	3103	0	0
T6	9154	9068	0	0
T7	1029	943	0	0
T8	1202	1148	0	0
T9	1093	1014	0	0
T10	2692	2631	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455442118	455312318	0	0
T1	1596	1540	0	0
T2	1231	1140	0	0
T3	2908	2842	0	0
T4	2964	2889	0	0
T5	3191	3103	0	0
T6	9154	9068	0	0
T7	1029	943	0	0
T8	1202	1148	0	0
T9	1093	1014	0	0
T10	2692	2631	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455442118	455312318	0	0
T1	1596	1540	0	0
T2	1231	1140	0	0
T3	2908	2842	0	0
T4	2964	2889	0	0
T5	3191	3103	0	0
T6	9154	9068	0	0
T7	1029	943	0	0
T8	1202	1148	0	0
T9	1093	1014	0	0
T10	2692	2631	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	455442118	12942080	0	0
DataKnown_AKnownEnable	455442118	455312318	0	0
DepthKnown_A	455442118	455312318	0	0
RvalidKnown_A	455442118	455312318	0	0
WreadyKnown_A	455442118	455312318	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455442118	12942080	0	0
T1	1596	1	0	0
T2	1231	77	0	0
T3	2908	26	0	0
T4	2964	235	0	0
T5	3191	2	0	0
T6	9154	48	0	0
T7	1029	3	0	0
T8	1202	49	0	0
T9	1093	17	0	0
T10	2692	1	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	455442118	455312318	0	0
T1	1596	1540	0	0
T2	1231	1140	0	0
T3	2908	2842	0	0
T4	2964	2889	0	0
T5	3191	3103	0	0
T6	9154	9068	0	0
T7	1029	943	0	0
T8	1202	1148	0	0
T9	1093	1014	0	0
T10	2692	2631	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455442118	455312318	0	0
T1	1596	1540	0	0
T2	1231	1140	0	0
T3	2908	2842	0	0
T4	2964	2889	0	0
T5	3191	3103	0	0
T6	9154	9068	0	0
T7	1029	943	0	0
T8	1202	1148	0	0
T9	1093	1014	0	0
T10	2692	2631	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455442118	455312318	0	0
T1	1596	1540	0	0
T2	1231	1140	0	0
T3	2908	2842	0	0
T4	2964	2889	0	0
T5	3191	3103	0	0
T6	9154	9068	0	0
T7	1029	943	0	0
T8	1202	1148	0	0
T9	1093	1014	0	0
T10	2692	2631	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455442118	455312318	0	0
T1	1596	1540	0	0
T2	1231	1140	0	0
T3	2908	2842	0	0
T4	2964	2889	0	0
T5	3191	3103	0	0
T6	9154	9068	0	0
T7	1029	943	0	0
T8	1202	1148	0	0
T9	1093	1014	0	0
T10	2692	2631	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0