Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3185825	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4019043

1

T1

1

T3

103

T4

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3919294	1			T1	69		T2	1		T3	101
values[0x0]	1640663	1			T3	48		T4	1		T5	1
values[0x1]	1644911	1			T3	52		T4	3		T5	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2268458	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4936410

1

T1

20

T3

150

T4

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29857	1			T6	8		T8	3		T12	4
valid_sources[0x01]	30438	1			T6	7		T8	6		T11	4
valid_sources[0x02]	28452	1			T6	7		T8	7		T11	9
valid_sources[0x03]	24966	1			T6	12		T11	6		T12	9
valid_sources[0x04]	28073	1			T1	1		T6	14		T8	1
valid_sources[0x05]	28143	1			T3	1		T6	6		T8	4
valid_sources[0x06]	26140	1			T6	16		T8	6		T11	11
valid_sources[0x07]	26375	1			T6	6		T8	2		T12	3
valid_sources[0x08]	29642	1			T6	14		T8	9		T11	7
valid_sources[0x09]	29740	1			T1	1		T6	12		T8	3
valid_sources[0x0a]	29300	1			T6	10		T8	4		T11	9
valid_sources[0x0b]	31169	1			T6	4		T8	4		T12	4
valid_sources[0x0c]	28145	1			T6	5		T8	5		T11	8
valid_sources[0x0d]	26314	1			T6	9		T8	3		T12	8
valid_sources[0x0e]	30240	1			T6	12		T8	8		T11	3
valid_sources[0x0f]	31077	1			T1	3		T6	11		T8	3
valid_sources[0x10]	26089	1			T3	25		T6	4		T8	2
valid_sources[0x11]	26899	1			T1	1		T6	8		T8	1
valid_sources[0x12]	29839	1			T6	7		T8	3		T11	3
valid_sources[0x13]	25238	1			T6	6		T8	2		T11	4
valid_sources[0x14]	26716	1			T6	6		T8	8		T11	4
valid_sources[0x15]	27849	1			T1	1		T6	7		T8	3
valid_sources[0x16]	28856	1			T6	6		T8	9		T11	2
valid_sources[0x17]	26772	1			T6	11		T8	4		T10	783
valid_sources[0x18]	26472	1			T1	2		T3	9		T6	9
valid_sources[0x19]	31012	1			T1	1		T6	10		T8	3
valid_sources[0x1a]	25411	1			T6	15		T8	2		T11	4
valid_sources[0x1b]	26920	1			T1	2		T6	7		T8	1
valid_sources[0x1c]	31848	1			T1	1		T6	12		T8	3
valid_sources[0x1d]	24715	1			T1	1		T6	15		T8	3
valid_sources[0x1e]	25118	1			T1	1		T6	16		T8	1
valid_sources[0x1f]	24496	1			T6	4		T8	3		T11	6
valid_sources[0x20]	29612	1			T1	1		T6	6		T8	6
valid_sources[0x21]	25456	1			T6	7		T8	2		T11	15
valid_sources[0x22]	29502	1			T6	10		T8	1		T11	3
valid_sources[0x23]	28409	1			T6	9		T8	1		T12	5
valid_sources[0x24]	29081	1			T6	12		T8	1		T11	4
valid_sources[0x25]	25733	1			T1	1		T6	7		T8	4
valid_sources[0x26]	30527	1			T1	1		T6	11		T8	1
valid_sources[0x27]	24756	1			T3	9		T6	9		T11	4
valid_sources[0x28]	26029	1			T6	12		T8	3		T11	4
valid_sources[0x29]	26705	1			T6	6		T11	1		T12	5
valid_sources[0x2a]	25898	1			T1	1		T6	7		T8	3
valid_sources[0x2b]	27258	1			T6	8		T8	3		T11	9
valid_sources[0x2c]	30584	1			T6	10		T8	2		T12	3
valid_sources[0x2d]	34741	1			T1	1		T6	7		T8	1
valid_sources[0x2e]	29430	1			T6	8		T8	1		T11	1
valid_sources[0x2f]	25104	1			T6	6		T8	4		T11	4
valid_sources[0x30]	29119	1			T5	1		T6	4		T8	5
valid_sources[0x31]	29468	1			T6	9		T8	1		T11	1
valid_sources[0x32]	27604	1			T6	10		T8	1		T11	5
valid_sources[0x33]	28645	1			T6	6		T8	2		T12	7
valid_sources[0x34]	30425	1			T6	11		T8	5		T11	5
valid_sources[0x35]	26708	1			T6	2		T8	2		T11	12
valid_sources[0x36]	27337	1			T6	4		T8	5		T11	4
valid_sources[0x37]	26717	1			T6	11		T8	2		T12	5
valid_sources[0x38]	30017	1			T6	8		T8	2		T11	3
valid_sources[0x39]	26279	1			T6	11		T8	4		T11	5
valid_sources[0x3a]	26765	1			T6	9		T8	5		T11	5
valid_sources[0x3b]	26797	1			T6	3		T8	1		T11	1
valid_sources[0x3c]	27530	1			T6	7		T8	3		T11	3
valid_sources[0x3d]	29674	1			T6	6		T8	2		T11	10
valid_sources[0x3e]	26594	1			T6	8		T8	1		T11	10
valid_sources[0x3f]	29521	1			T6	4		T8	3		T11	5
valid_sources[0x40]	27302	1			T6	6		T8	4		T11	33
valid_sources[0x41]	27581	1			T6	5		T11	1		T12	6
valid_sources[0x42]	26862	1			T6	19		T8	4		T11	9
valid_sources[0x43]	26812	1			T6	14		T8	3		T11	2
valid_sources[0x44]	30153	1			T1	1		T6	7		T8	1
valid_sources[0x45]	33559	1			T6	8		T8	7		T11	9
valid_sources[0x46]	29544	1			T1	1		T6	10		T8	3
valid_sources[0x47]	26424	1			T6	7		T8	4		T11	4
valid_sources[0x48]	29573	1			T6	11		T8	2		T11	1
valid_sources[0x49]	27961	1			T3	11		T6	12		T8	3
valid_sources[0x4a]	25002	1			T3	5		T6	13		T8	15
valid_sources[0x4b]	26804	1			T6	8		T8	6		T11	2
valid_sources[0x4c]	27046	1			T6	5		T8	6		T11	3
valid_sources[0x4d]	26593	1			T6	9		T8	5		T11	3
valid_sources[0x4e]	26636	1			T6	6		T8	3		T11	6
valid_sources[0x4f]	26152	1			T1	1		T6	7		T8	1
valid_sources[0x50]	29786	1			T6	10		T8	2		T11	2
valid_sources[0x51]	30174	1			T6	6		T8	2		T11	9
valid_sources[0x52]	27007	1			T6	4		T8	2		T11	3
valid_sources[0x53]	27661	1			T1	2		T6	11		T8	3
valid_sources[0x54]	29690	1			T6	5		T8	3		T11	1
valid_sources[0x55]	24599	1			T3	19		T6	2		T8	2
valid_sources[0x56]	26034	1			T1	2		T6	9		T8	1
valid_sources[0x57]	24790	1			T6	7		T8	5		T11	1
valid_sources[0x58]	28958	1			T1	2		T6	9		T8	2
valid_sources[0x59]	28016	1			T6	10		T8	11		T11	8
valid_sources[0x5a]	28554	1			T1	1		T6	6		T8	2
valid_sources[0x5b]	27810	1			T6	12		T8	7		T11	10
valid_sources[0x5c]	25208	1			T6	9		T8	9		T11	2
valid_sources[0x5d]	25494	1			T6	8		T8	7		T12	6
valid_sources[0x5e]	30519	1			T6	10		T12	6		T14	9
valid_sources[0x5f]	28588	1			T6	12		T8	6		T11	7
valid_sources[0x60]	28246	1			T1	1		T6	11		T8	5
valid_sources[0x61]	32212	1			T6	14		T8	2		T11	1
valid_sources[0x62]	28907	1			T6	13		T11	6		T12	10
valid_sources[0x63]	27863	1			T4	5		T6	7		T11	4
valid_sources[0x64]	28151	1			T6	10		T8	4		T11	3
valid_sources[0x65]	31077	1			T6	4		T8	1		T11	12
valid_sources[0x66]	26808	1			T1	1		T3	19		T6	2
valid_sources[0x67]	27677	1			T3	5		T6	7		T8	6
valid_sources[0x68]	27440	1			T6	5		T11	7		T12	4
valid_sources[0x69]	27959	1			T6	10		T8	10		T11	2
valid_sources[0x6a]	29585	1			T6	12		T8	3		T11	7
valid_sources[0x6b]	25297	1			T6	8		T8	4		T11	2
valid_sources[0x6c]	29000	1			T6	9		T8	2		T12	5
valid_sources[0x6d]	25837	1			T6	13		T8	5		T11	1
valid_sources[0x6e]	29152	1			T6	5		T8	1		T12	10
valid_sources[0x6f]	26677	1			T6	7		T8	5		T12	8
valid_sources[0x70]	27597	1			T6	8		T11	4		T12	11
valid_sources[0x71]	30149	1			T6	16		T8	6		T11	6
valid_sources[0x72]	28320	1			T6	11		T11	3		T12	4
valid_sources[0x73]	27414	1			T1	1		T6	11		T8	8
valid_sources[0x74]	24825	1			T6	12		T8	5		T11	3
valid_sources[0x75]	28062	1			T6	8		T8	4		T12	5
valid_sources[0x76]	30311	1			T3	9		T6	8		T8	6
valid_sources[0x77]	29777	1			T6	7		T8	2		T11	1
valid_sources[0x78]	36044	1			T6	6		T8	2		T11	1
valid_sources[0x79]	27318	1			T3	26		T6	11		T8	1
valid_sources[0x7a]	29460	1			T6	6		T8	5		T12	6
valid_sources[0x7b]	27026	1			T6	13		T8	3		T11	4
valid_sources[0x7c]	26264	1			T6	6		T8	7		T11	1
valid_sources[0x7d]	26939	1			T6	7		T8	7		T11	18
valid_sources[0x7e]	25932	1			T6	8		T7	442		T8	5
valid_sources[0x7f]	27049	1			T1	1		T6	9		T8	3
valid_sources[0x80]	25564	1			T6	7		T8	2		T11	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1019467

1

T1

1

T3

3

T4

1

values[0x0]

all_enables

biggest_size

1509514

1

T3

48

T6

401

T7

424

values[0x1]

all_enables

biggest_size

1490062

1

T3

52

T4

2

T5

2