Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3206929

1

T1

68

T2

1

T4

2

full_word

4018117

1

T1

1

T4

3

T5

3

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7224616	1			T1	69		T2	1		T4	5
auto[TlIntgErrCmd]	140	1			T112	7		T113	10		T114	5
auto[TlIntgErrData]	135	1			T112	8		T113	5		T114	2
auto[TlIntgErrBoth]	155	1			T112	5		T113	5		T114	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3922279

1

T1

69

T2

1

T4

1

auto[1]

3302767

1

T4

4

T5

4

T6

1072

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	2902463	1			T1	68		T2	1		T5	4
auto[TlIntgErrNone]	partial	auto[1]	304064	1			T4	2		T5	2		T6	291
auto[TlIntgErrNone]	full_word	auto[0]	1019615	1			T1	1		T4	1		T5	1
auto[TlIntgErrNone]	full_word	auto[1]	2998474	1			T4	2		T5	2		T6	781
auto[TlIntgErrCmd]	partial	auto[0]	59	1			T112	2		T113	6		T114	2
auto[TlIntgErrCmd]	partial	auto[1]	72	1			T112	4		T113	4		T114	3
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T156	1		T189	1		T188	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T112	1		T156	1		T190	1
auto[TlIntgErrData]	partial	auto[0]	62	1			T112	2		T113	3		T114	1
auto[TlIntgErrData]	partial	auto[1]	66	1			T112	5		T113	2		T114	1
auto[TlIntgErrData]	full_word	auto[0]	2	1			T189	1		T192	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	5	1			T112	1		T156	1		T189	1
auto[TlIntgErrBoth]	partial	auto[0]	65	1			T112	2		T113	3		T114	1
auto[TlIntgErrBoth]	partial	auto[1]	78	1			T112	3		T113	2		T114	2
auto[TlIntgErrBoth]	full_word	auto[0]	9	1			T156	2		T188	1		T120	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T190	1		T193	1		T192	1