Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	419996797	2814187	0	0
DataKnown_AKnownEnable	419996797	419860695	0	0
DepthKnown_A	419996797	419860695	0	0
RvalidKnown_A	419996797	419860695	0	0
WreadyKnown_A	419996797	419860695	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419996797	2814187	0	0
T3	1783	100	0	0
T4	1281	0	0	0
T5	1069	0	0	0
T6	69410	0	0	0
T7	96749	1666	0	0
T8	13829	1663	0	0
T9	53869	832	0	0
T10	440049	0	0	0
T11	7176	1669	0	0
T12	13983	2174	0	0
T13	0	832	0	0
T14	0	1663	0	0
T25	0	100	0	0
T40	0	1663	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	419996797	419860695	0	0
T1	1548	1484	0	0
T2	999	912	0	0
T3	1783	1683	0	0
T4	1281	1224	0	0
T5	1069	999	0	0
T6	69410	69310	0	0
T7	96749	96678	0	0
T8	13829	13734	0	0
T9	53869	53784	0	0
T10	440049	439974	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419996797	419860695	0	0
T1	1548	1484	0	0
T2	999	912	0	0
T3	1783	1683	0	0
T4	1281	1224	0	0
T5	1069	999	0	0
T6	69410	69310	0	0
T7	96749	96678	0	0
T8	13829	13734	0	0
T9	53869	53784	0	0
T10	440049	439974	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419996797	419860695	0	0
T1	1548	1484	0	0
T2	999	912	0	0
T3	1783	1683	0	0
T4	1281	1224	0	0
T5	1069	999	0	0
T6	69410	69310	0	0
T7	96749	96678	0	0
T8	13829	13734	0	0
T9	53869	53784	0	0
T10	440049	439974	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419996797	419860695	0	0
T1	1548	1484	0	0
T2	999	912	0	0
T3	1783	1683	0	0
T4	1281	1224	0	0
T5	1069	999	0	0
T6	69410	69310	0	0
T7	96749	96678	0	0
T8	13829	13734	0	0
T9	53869	53784	0	0
T10	440049	439974	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	419996797	3196228	0	0
DataKnown_AKnownEnable	419996797	419860695	0	0
DepthKnown_A	419996797	419860695	0	0
RvalidKnown_A	419996797	419860695	0	0
WreadyKnown_A	419996797	419860695	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419996797	3196228	0	0
T3	1783	100	0	0
T4	1281	0	0	0
T5	1069	0	0	0
T6	69410	0	0	0
T7	96749	835	0	0
T8	13829	832	0	0
T9	53869	2588	0	0
T10	440049	0	0	0
T11	7176	838	0	0
T12	13983	1088	0	0
T13	0	832	0	0
T14	0	832	0	0
T25	0	100	0	0
T40	0	832	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	419996797	419860695	0	0
T1	1548	1484	0	0
T2	999	912	0	0
T3	1783	1683	0	0
T4	1281	1224	0	0
T5	1069	999	0	0
T6	69410	69310	0	0
T7	96749	96678	0	0
T8	13829	13734	0	0
T9	53869	53784	0	0
T10	440049	439974	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419996797	419860695	0	0
T1	1548	1484	0	0
T2	999	912	0	0
T3	1783	1683	0	0
T4	1281	1224	0	0
T5	1069	999	0	0
T6	69410	69310	0	0
T7	96749	96678	0	0
T8	13829	13734	0	0
T9	53869	53784	0	0
T10	440049	439974	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419996797	419860695	0	0
T1	1548	1484	0	0
T2	999	912	0	0
T3	1783	1683	0	0
T4	1281	1224	0	0
T5	1069	999	0	0
T6	69410	69310	0	0
T7	96749	96678	0	0
T8	13829	13734	0	0
T9	53869	53784	0	0
T10	440049	439974	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419996797	419860695	0	0
T1	1548	1484	0	0
T2	999	912	0	0
T3	1783	1683	0	0
T4	1281	1224	0	0
T5	1069	999	0	0
T6	69410	69310	0	0
T7	96749	96678	0	0
T8	13829	13734	0	0
T9	53869	53784	0	0
T10	440049	439974	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	419996797	173562	0	0
DataKnown_AKnownEnable	419996797	419860695	0	0
DepthKnown_A	419996797	419860695	0	0
RvalidKnown_A	419996797	419860695	0	0
WreadyKnown_A	419996797	419860695	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419996797	173562	0	0
T3	1783	100	0	0
T4	1281	0	0	0
T5	1069	0	0	0
T6	69410	298	0	0
T7	96749	0	0	0
T8	13829	0	0	0
T9	53869	0	0	0
T10	440049	0	0	0
T11	7176	0	0	0
T12	13983	0	0	0
T19	0	65	0	0
T25	0	100	0	0
T27	0	30	0	0
T28	0	450	0	0
T30	0	575	0	0
T32	0	939	0	0
T34	0	8	0	0
T44	0	100	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	419996797	419860695	0	0
T1	1548	1484	0	0
T2	999	912	0	0
T3	1783	1683	0	0
T4	1281	1224	0	0
T5	1069	999	0	0
T6	69410	69310	0	0
T7	96749	96678	0	0
T8	13829	13734	0	0
T9	53869	53784	0	0
T10	440049	439974	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419996797	419860695	0	0
T1	1548	1484	0	0
T2	999	912	0	0
T3	1783	1683	0	0
T4	1281	1224	0	0
T5	1069	999	0	0
T6	69410	69310	0	0
T7	96749	96678	0	0
T8	13829	13734	0	0
T9	53869	53784	0	0
T10	440049	439974	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419996797	419860695	0	0
T1	1548	1484	0	0
T2	999	912	0	0
T3	1783	1683	0	0
T4	1281	1224	0	0
T5	1069	999	0	0
T6	69410	69310	0	0
T7	96749	96678	0	0
T8	13829	13734	0	0
T9	53869	53784	0	0
T10	440049	439974	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419996797	419860695	0	0
T1	1548	1484	0	0
T2	999	912	0	0
T3	1783	1683	0	0
T4	1281	1224	0	0
T5	1069	999	0	0
T6	69410	69310	0	0
T7	96749	96678	0	0
T8	13829	13734	0	0
T9	53869	53784	0	0
T10	440049	439974	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	419996797	417436	0	0
DataKnown_AKnownEnable	419996797	419860695	0	0
DepthKnown_A	419996797	419860695	0	0
RvalidKnown_A	419996797	419860695	0	0
WreadyKnown_A	419996797	419860695	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419996797	417436	0	0
T3	1783	100	0	0
T4	1281	0	0	0
T5	1069	0	0	0
T6	69410	1348	0	0
T7	96749	0	0	0
T8	13829	0	0	0
T9	53869	0	0	0
T10	440049	0	0	0
T11	7176	0	0	0
T12	13983	0	0	0
T19	0	240	0	0
T25	0	100	0	0
T27	0	141	0	0
T28	0	1992	0	0
T30	0	2583	0	0
T32	0	4411	0	0
T34	0	26	0	0
T44	0	100	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	419996797	419860695	0	0
T1	1548	1484	0	0
T2	999	912	0	0
T3	1783	1683	0	0
T4	1281	1224	0	0
T5	1069	999	0	0
T6	69410	69310	0	0
T7	96749	96678	0	0
T8	13829	13734	0	0
T9	53869	53784	0	0
T10	440049	439974	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419996797	419860695	0	0
T1	1548	1484	0	0
T2	999	912	0	0
T3	1783	1683	0	0
T4	1281	1224	0	0
T5	1069	999	0	0
T6	69410	69310	0	0
T7	96749	96678	0	0
T8	13829	13734	0	0
T9	53869	53784	0	0
T10	440049	439974	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419996797	419860695	0	0
T1	1548	1484	0	0
T2	999	912	0	0
T3	1783	1683	0	0
T4	1281	1224	0	0
T5	1069	999	0	0
T6	69410	69310	0	0
T7	96749	96678	0	0
T8	13829	13734	0	0
T9	53869	53784	0	0
T10	440049	439974	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419996797	419860695	0	0
T1	1548	1484	0	0
T2	999	912	0	0
T3	1783	1683	0	0
T4	1281	1224	0	0
T5	1069	999	0	0
T6	69410	69310	0	0
T7	96749	96678	0	0
T8	13829	13734	0	0
T9	53869	53784	0	0
T10	440049	439974	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	419996797	5654683	0	0
DataKnown_AKnownEnable	419996797	419860695	0	0
DepthKnown_A	419996797	419860695	0	0
RvalidKnown_A	419996797	419860695	0	0
WreadyKnown_A	419996797	419860695	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419996797	5654683	0	0
T1	1548	69	0	0
T2	999	1	0	0
T3	1783	1	0	0
T4	1281	5	0	0
T5	1069	9	0	0
T6	69410	2085	0	0
T7	96749	61	0	0
T8	13829	50	0	0
T9	53869	1147	0	0
T10	440049	783	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	419996797	419860695	0	0
T1	1548	1484	0	0
T2	999	912	0	0
T3	1783	1683	0	0
T4	1281	1224	0	0
T5	1069	999	0	0
T6	69410	69310	0	0
T7	96749	96678	0	0
T8	13829	13734	0	0
T9	53869	53784	0	0
T10	440049	439974	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419996797	419860695	0	0
T1	1548	1484	0	0
T2	999	912	0	0
T3	1783	1683	0	0
T4	1281	1224	0	0
T5	1069	999	0	0
T6	69410	69310	0	0
T7	96749	96678	0	0
T8	13829	13734	0	0
T9	53869	53784	0	0
T10	440049	439974	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419996797	419860695	0	0
T1	1548	1484	0	0
T2	999	912	0	0
T3	1783	1683	0	0
T4	1281	1224	0	0
T5	1069	999	0	0
T6	69410	69310	0	0
T7	96749	96678	0	0
T8	13829	13734	0	0
T9	53869	53784	0	0
T10	440049	439974	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419996797	419860695	0	0
T1	1548	1484	0	0
T2	999	912	0	0
T3	1783	1683	0	0
T4	1281	1224	0	0
T5	1069	999	0	0
T6	69410	69310	0	0
T7	96749	96678	0	0
T8	13829	13734	0	0
T9	53869	53784	0	0
T10	440049	439974	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	419996797	12036137	0	0
DataKnown_AKnownEnable	419996797	419860695	0	0
DepthKnown_A	419996797	419860695	0	0
RvalidKnown_A	419996797	419860695	0	0
WreadyKnown_A	419996797	419860695	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419996797	12036137	0	0
T1	1548	69	0	0
T2	999	1	0	0
T3	1783	1	0	0
T4	1281	24	0	0
T5	1069	25	0	0
T6	69410	8497	0	0
T7	96749	202	0	0
T8	13829	106	0	0
T9	53869	3579	0	0
T10	440049	783	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	419996797	419860695	0	0
T1	1548	1484	0	0
T2	999	912	0	0
T3	1783	1683	0	0
T4	1281	1224	0	0
T5	1069	999	0	0
T6	69410	69310	0	0
T7	96749	96678	0	0
T8	13829	13734	0	0
T9	53869	53784	0	0
T10	440049	439974	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419996797	419860695	0	0
T1	1548	1484	0	0
T2	999	912	0	0
T3	1783	1683	0	0
T4	1281	1224	0	0
T5	1069	999	0	0
T6	69410	69310	0	0
T7	96749	96678	0	0
T8	13829	13734	0	0
T9	53869	53784	0	0
T10	440049	439974	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419996797	419860695	0	0
T1	1548	1484	0	0
T2	999	912	0	0
T3	1783	1683	0	0
T4	1281	1224	0	0
T5	1069	999	0	0
T6	69410	69310	0	0
T7	96749	96678	0	0
T8	13829	13734	0	0
T9	53869	53784	0	0
T10	440049	439974	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419996797	419860695	0	0
T1	1548	1484	0	0
T2	999	912	0	0
T3	1783	1683	0	0
T4	1281	1224	0	0
T5	1069	999	0	0
T6	69410	69310	0	0
T7	96749	96678	0	0
T8	13829	13734	0	0
T9	53869	53784	0	0
T10	440049	439974	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0