Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3514320	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4234050

1

T1

1

T2

107

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4150784	1			T1	77		T2	101		T3	1
values[0x0]	1796039	1			T2	48		T4	184		T5	5
values[0x1]	1801547	1			T2	52		T4	196		T5	11

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2483057	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5265313

1

T1

38

T2

154

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27419	1			T4	1		T8	3		T12	9
valid_sources[0x01]	27991	1			T12	4		T15	6		T17	1
valid_sources[0x02]	27535	1			T8	6		T12	3		T15	5
valid_sources[0x03]	27166	1			T2	2		T4	2		T8	1
valid_sources[0x04]	29862	1			T4	2		T9	6		T12	13
valid_sources[0x05]	29729	1			T4	3		T8	2		T12	9
valid_sources[0x06]	28291	1			T2	2		T9	2		T11	37
valid_sources[0x07]	26343	1			T1	1		T2	1		T4	2
valid_sources[0x08]	33285	1			T4	1		T9	3		T12	9
valid_sources[0x09]	27858	1			T4	1		T9	3		T11	12
valid_sources[0x0a]	28701	1			T1	3		T9	4		T11	7
valid_sources[0x0b]	30748	1			T1	1		T12	8		T15	4
valid_sources[0x0c]	28887	1			T8	5		T9	3		T12	6
valid_sources[0x0d]	31189	1			T2	1		T4	1		T9	4
valid_sources[0x0e]	27251	1			T2	2		T4	1		T9	1
valid_sources[0x0f]	28796	1			T8	15		T9	1		T12	6
valid_sources[0x10]	31667	1			T2	4		T4	1		T9	5
valid_sources[0x11]	27167	1			T2	7		T4	1		T8	2
valid_sources[0x12]	26050	1			T1	3		T2	1		T4	1
valid_sources[0x13]	30457	1			T2	1		T4	3		T11	22
valid_sources[0x14]	27709	1			T4	4		T8	13		T9	3
valid_sources[0x15]	29588	1			T4	4		T8	17		T11	7
valid_sources[0x16]	28352	1			T4	5		T11	22		T12	4
valid_sources[0x17]	30960	1			T1	1		T4	4		T11	9
valid_sources[0x18]	29563	1			T2	1		T4	2		T8	2
valid_sources[0x19]	32978	1			T1	2		T2	1		T4	1
valid_sources[0x1a]	29965	1			T2	5		T4	2		T9	27
valid_sources[0x1b]	27254	1			T2	2		T4	1		T9	5
valid_sources[0x1c]	33046	1			T4	2		T9	3		T11	1
valid_sources[0x1d]	30087	1			T4	2		T11	8		T12	7
valid_sources[0x1e]	27533	1			T9	4		T11	1		T12	11
valid_sources[0x1f]	29962	1			T4	2		T11	8		T12	3
valid_sources[0x20]	27504	1			T4	2		T11	8		T12	8
valid_sources[0x21]	30275	1			T4	1		T9	7		T12	11
valid_sources[0x22]	30783	1			T4	3		T5	1		T9	3
valid_sources[0x23]	31780	1			T1	3		T2	2		T4	1
valid_sources[0x24]	31571	1			T2	1		T4	2		T9	8
valid_sources[0x25]	32476	1			T1	1		T2	2		T4	1
valid_sources[0x26]	30571	1			T1	2		T4	2		T9	3
valid_sources[0x27]	26640	1			T4	2		T12	4		T15	5
valid_sources[0x28]	33147	1			T4	1		T9	4		T12	5
valid_sources[0x29]	29785	1			T4	2		T5	2		T11	7
valid_sources[0x2a]	26978	1			T2	5		T4	1		T9	5
valid_sources[0x2b]	49309	1			T2	5		T5	1		T8	3
valid_sources[0x2c]	42599	1			T2	1		T5	1		T9	8
valid_sources[0x2d]	32602	1			T8	2		T11	14		T12	8
valid_sources[0x2e]	28037	1			T2	1		T4	2		T8	3
valid_sources[0x2f]	26423	1			T2	2		T4	1		T9	1
valid_sources[0x30]	31034	1			T2	2		T11	2		T12	12
valid_sources[0x31]	26800	1			T4	2		T11	30		T12	4
valid_sources[0x32]	31957	1			T9	1		T11	6		T12	15
valid_sources[0x33]	28941	1			T2	1		T4	1		T9	14
valid_sources[0x34]	28799	1			T4	3		T9	3		T11	3
valid_sources[0x35]	32306	1			T1	1		T4	1		T11	7
valid_sources[0x36]	28383	1			T2	1		T4	1		T11	2
valid_sources[0x37]	26548	1			T4	2		T8	13		T9	5
valid_sources[0x38]	40490	1			T4	2		T9	2		T12	9
valid_sources[0x39]	27672	1			T5	1		T11	7		T12	2
valid_sources[0x3a]	29225	1			T2	3		T12	6		T15	5
valid_sources[0x3b]	28766	1			T2	1		T4	2		T9	1
valid_sources[0x3c]	29396	1			T4	3		T8	9		T9	13
valid_sources[0x3d]	32615	1			T4	5		T11	1		T12	14
valid_sources[0x3e]	28202	1			T11	25		T12	3		T15	5
valid_sources[0x3f]	28620	1			T2	1		T12	13		T15	9
valid_sources[0x40]	26924	1			T2	1		T4	1		T9	5
valid_sources[0x41]	28668	1			T4	1		T12	8		T15	3
valid_sources[0x42]	30103	1			T2	3		T11	7		T12	7
valid_sources[0x43]	26885	1			T1	1		T4	4		T9	5
valid_sources[0x44]	29202	1			T4	5		T12	12		T15	5
valid_sources[0x45]	33188	1			T4	1		T8	2		T9	2
valid_sources[0x46]	26614	1			T2	4		T4	3		T9	8
valid_sources[0x47]	27349	1			T2	2		T4	3		T8	15
valid_sources[0x48]	28728	1			T4	1		T9	4		T12	7
valid_sources[0x49]	27877	1			T4	3		T12	14		T15	2
valid_sources[0x4a]	29328	1			T4	1		T12	10		T17	1
valid_sources[0x4b]	28868	1			T4	3		T9	6		T11	6
valid_sources[0x4c]	30256	1			T4	1		T11	3		T12	12
valid_sources[0x4d]	29757	1			T4	1		T5	1		T7	1
valid_sources[0x4e]	29358	1			T4	2		T11	2		T12	13
valid_sources[0x4f]	29407	1			T4	1		T5	1		T11	3
valid_sources[0x50]	28624	1			T2	1		T4	1		T12	5
valid_sources[0x51]	28830	1			T4	1		T9	9		T12	11
valid_sources[0x52]	32797	1			T8	7		T9	1		T11	3
valid_sources[0x53]	26288	1			T1	2		T4	1		T9	2
valid_sources[0x54]	30090	1			T2	1		T4	3		T8	11
valid_sources[0x55]	27937	1			T1	1		T2	2		T4	3
valid_sources[0x56]	28876	1			T4	1		T12	8		T15	10
valid_sources[0x57]	27687	1			T4	1		T9	7		T11	12
valid_sources[0x58]	29008	1			T4	1		T11	3		T12	8
valid_sources[0x59]	35948	1			T4	5		T11	6		T12	10
valid_sources[0x5a]	32426	1			T2	4		T4	2		T9	5
valid_sources[0x5b]	31818	1			T1	6		T4	3		T8	4
valid_sources[0x5c]	33471	1			T4	1		T11	3		T12	9
valid_sources[0x5d]	30859	1			T2	4		T4	2		T8	15
valid_sources[0x5e]	31143	1			T2	2		T4	1		T9	6
valid_sources[0x5f]	27453	1			T2	1		T9	11		T12	14
valid_sources[0x60]	29323	1			T8	5		T11	2		T12	3
valid_sources[0x61]	32082	1			T2	1		T11	19		T12	11
valid_sources[0x62]	31179	1			T2	1		T4	3		T8	1
valid_sources[0x63]	31501	1			T4	1		T5	1		T11	1
valid_sources[0x64]	30347	1			T4	3		T8	5		T9	3
valid_sources[0x65]	28541	1			T4	1		T9	18		T11	31
valid_sources[0x66]	27088	1			T1	1		T2	1		T4	2
valid_sources[0x67]	30312	1			T2	1		T4	4		T9	8
valid_sources[0x68]	31091	1			T1	3		T4	1		T9	9
valid_sources[0x69]	30947	1			T4	1		T9	4		T11	3
valid_sources[0x6a]	32536	1			T4	3		T8	2		T9	33
valid_sources[0x6b]	28069	1			T1	1		T11	6		T12	10
valid_sources[0x6c]	29368	1			T1	3		T4	4		T9	2
valid_sources[0x6d]	30403	1			T2	2		T4	2		T11	16
valid_sources[0x6e]	30147	1			T2	2		T4	1		T8	2
valid_sources[0x6f]	28617	1			T2	2		T4	3		T11	1
valid_sources[0x70]	28210	1			T2	1		T9	1		T12	5
valid_sources[0x71]	31141	1			T2	1		T4	1		T8	27
valid_sources[0x72]	27970	1			T4	2		T8	3		T11	4
valid_sources[0x73]	28604	1			T1	2		T2	2		T4	1
valid_sources[0x74]	28134	1			T2	2		T4	1		T8	7
valid_sources[0x75]	28030	1			T2	3		T4	2		T8	2
valid_sources[0x76]	30867	1			T11	4		T12	5		T26	3
valid_sources[0x77]	30094	1			T11	1		T12	6		T15	12
valid_sources[0x78]	28663	1			T1	1		T4	5		T9	18
valid_sources[0x79]	51288	1			T4	2		T9	1		T11	10
valid_sources[0x7a]	30764	1			T2	1		T3	1		T4	2
valid_sources[0x7b]	29758	1			T1	1		T8	6		T9	9
valid_sources[0x7c]	36338	1			T11	1		T12	4		T15	1
valid_sources[0x7d]	28356	1			T4	3		T11	11		T12	14
valid_sources[0x7e]	30424	1			T1	1		T4	3		T11	41
valid_sources[0x7f]	25458	1			T4	3		T8	6		T9	16
valid_sources[0x80]	34165	1			T1	1		T4	3		T8	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

968007

1

T1

1

T2

7

T3

1

values[0x0]

all_enables

biggest_size

1643021

1

T2

48

T4

144

T5

2

values[0x1]

all_enables

biggest_size

1623022

1

T2

52

T4

158

T5

10