Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3536153

1

T1

76

T4

79

T5

4

full_word

4233321

1

T1

1

T3

1

T4

302

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7769064	1			T1	77		T3	1		T4	381
auto[TlIntgErrCmd]	137	1			T133	3		T136	4		T137	1
auto[TlIntgErrData]	135	1			T133	1		T136	3		T137	4
auto[TlIntgErrBoth]	138	1			T133	6		T136	3		T137	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4153573

1

T1

77

T3

1

T4

1

auto[1]

3615901

1

T4

380

T5

16

T8

78

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3185165	1			T1	76		T4	1		T7	1
auto[TlIntgErrNone]	partial	auto[1]	350605	1			T4	78		T5	4		T8	47
auto[TlIntgErrNone]	full_word	auto[0]	968236	1			T1	1		T3	1		T5	1
auto[TlIntgErrNone]	full_word	auto[1]	3265058	1			T4	302		T5	12		T8	31
auto[TlIntgErrCmd]	partial	auto[0]	50	1			T136	1		T194	1		T215	1
auto[TlIntgErrCmd]	partial	auto[1]	79	1			T133	2		T136	3		T137	1
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T218	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T133	1		T215	1		T219	2
auto[TlIntgErrData]	partial	auto[0]	58	1			T133	1		T136	1		T137	2
auto[TlIntgErrData]	partial	auto[1]	67	1			T136	1		T137	2		T220	3
auto[TlIntgErrData]	full_word	auto[0]	6	1			T136	1		T194	1		T215	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T221	1		T222	1		T223	1
auto[TlIntgErrBoth]	partial	auto[0]	56	1			T133	5		T137	4		T220	1
auto[TlIntgErrBoth]	partial	auto[1]	73	1			T133	1		T136	3		T137	1
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T219	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T194	1		T221	1		T224	1