Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	461956249	2968714	0	0
DataKnown_AKnownEnable	461956249	461820799	0	0
DepthKnown_A	461956249	461820799	0	0
RvalidKnown_A	461956249	461820799	0	0
WreadyKnown_A	461956249	461820799	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461956249	2968714	0	0
T2	2418	100	0	0
T3	1718	0	0	0
T4	67232	0	0	0
T5	2198	0	0	0
T6	5598	0	0	0
T7	1923	0	0	0
T8	4287	0	0	0
T9	9735	1663	0	0
T10	9668	832	0	0
T11	42259	832	0	0
T12	0	2687	0	0
T14	0	832	0	0
T16	0	1663	0	0
T17	0	832	0	0
T21	0	1663	0	0
T26	0	100	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	461956249	461820799	0	0
T1	952	886	0	0
T2	2418	2357	0	0
T3	1718	1635	0	0
T4	67232	67166	0	0
T5	2198	2107	0	0
T6	5598	4103	0	0
T7	1923	1826	0	0
T8	4287	4217	0	0
T9	9735	9655	0	0
T10	9668	9605	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461956249	461820799	0	0
T1	952	886	0	0
T2	2418	2357	0	0
T3	1718	1635	0	0
T4	67232	67166	0	0
T5	2198	2107	0	0
T6	5598	4103	0	0
T7	1923	1826	0	0
T8	4287	4217	0	0
T9	9735	9655	0	0
T10	9668	9605	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461956249	461820799	0	0
T1	952	886	0	0
T2	2418	2357	0	0
T3	1718	1635	0	0
T4	67232	67166	0	0
T5	2198	2107	0	0
T6	5598	4103	0	0
T7	1923	1826	0	0
T8	4287	4217	0	0
T9	9735	9655	0	0
T10	9668	9605	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461956249	461820799	0	0
T1	952	886	0	0
T2	2418	2357	0	0
T3	1718	1635	0	0
T4	67232	67166	0	0
T5	2198	2107	0	0
T6	5598	4103	0	0
T7	1923	1826	0	0
T8	4287	4217	0	0
T9	9735	9655	0	0
T10	9668	9605	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	461956249	3226499	0	0
DataKnown_AKnownEnable	461956249	461820799	0	0
DepthKnown_A	461956249	461820799	0	0
RvalidKnown_A	461956249	461820799	0	0
WreadyKnown_A	461956249	461820799	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461956249	3226499	0	0
T2	2418	100	0	0
T3	1718	0	0	0
T4	67232	0	0	0
T5	2198	0	0	0
T6	5598	0	0	0
T7	1923	0	0	0
T8	4287	0	0	0
T9	9735	832	0	0
T10	9668	832	0	0
T11	42259	3825	0	0
T12	0	1346	0	0
T14	0	832	0	0
T16	0	832	0	0
T17	0	3645	0	0
T21	0	832	0	0
T26	0	100	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	461956249	461820799	0	0
T1	952	886	0	0
T2	2418	2357	0	0
T3	1718	1635	0	0
T4	67232	67166	0	0
T5	2198	2107	0	0
T6	5598	4103	0	0
T7	1923	1826	0	0
T8	4287	4217	0	0
T9	9735	9655	0	0
T10	9668	9605	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461956249	461820799	0	0
T1	952	886	0	0
T2	2418	2357	0	0
T3	1718	1635	0	0
T4	67232	67166	0	0
T5	2198	2107	0	0
T6	5598	4103	0	0
T7	1923	1826	0	0
T8	4287	4217	0	0
T9	9735	9655	0	0
T10	9668	9605	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461956249	461820799	0	0
T1	952	886	0	0
T2	2418	2357	0	0
T3	1718	1635	0	0
T4	67232	67166	0	0
T5	2198	2107	0	0
T6	5598	4103	0	0
T7	1923	1826	0	0
T8	4287	4217	0	0
T9	9735	9655	0	0
T10	9668	9605	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461956249	461820799	0	0
T1	952	886	0	0
T2	2418	2357	0	0
T3	1718	1635	0	0
T4	67232	67166	0	0
T5	2198	2107	0	0
T6	5598	4103	0	0
T7	1923	1826	0	0
T8	4287	4217	0	0
T9	9735	9655	0	0
T10	9668	9605	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	461956249	192764	0	0
DataKnown_AKnownEnable	461956249	461820799	0	0
DepthKnown_A	461956249	461820799	0	0
RvalidKnown_A	461956249	461820799	0	0
WreadyKnown_A	461956249	461820799	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461956249	192764	0	0
T2	2418	100	0	0
T3	1718	0	0	0
T4	67232	0	0	0
T5	2198	0	0	0
T6	5598	0	0	0
T7	1923	0	0	0
T8	4287	52	0	0
T9	9735	0	0	0
T10	9668	0	0	0
T11	42259	0	0	0
T15	0	20	0	0
T26	0	100	0	0
T27	0	34	0	0
T28	0	231	0	0
T29	0	17	0	0
T30	0	740	0	0
T44	0	100	0	0
T46	0	100	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	461956249	461820799	0	0
T1	952	886	0	0
T2	2418	2357	0	0
T3	1718	1635	0	0
T4	67232	67166	0	0
T5	2198	2107	0	0
T6	5598	4103	0	0
T7	1923	1826	0	0
T8	4287	4217	0	0
T9	9735	9655	0	0
T10	9668	9605	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461956249	461820799	0	0
T1	952	886	0	0
T2	2418	2357	0	0
T3	1718	1635	0	0
T4	67232	67166	0	0
T5	2198	2107	0	0
T6	5598	4103	0	0
T7	1923	1826	0	0
T8	4287	4217	0	0
T9	9735	9655	0	0
T10	9668	9605	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461956249	461820799	0	0
T1	952	886	0	0
T2	2418	2357	0	0
T3	1718	1635	0	0
T4	67232	67166	0	0
T5	2198	2107	0	0
T6	5598	4103	0	0
T7	1923	1826	0	0
T8	4287	4217	0	0
T9	9735	9655	0	0
T10	9668	9605	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461956249	461820799	0	0
T1	952	886	0	0
T2	2418	2357	0	0
T3	1718	1635	0	0
T4	67232	67166	0	0
T5	2198	2107	0	0
T6	5598	4103	0	0
T7	1923	1826	0	0
T8	4287	4217	0	0
T9	9735	9655	0	0
T10	9668	9605	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	461956249	424439	0	0
DataKnown_AKnownEnable	461956249	461820799	0	0
DepthKnown_A	461956249	461820799	0	0
RvalidKnown_A	461956249	461820799	0	0
WreadyKnown_A	461956249	461820799	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461956249	424439	0	0
T2	2418	100	0	0
T3	1718	0	0	0
T4	67232	0	0	0
T5	2198	0	0	0
T6	5598	0	0	0
T7	1923	0	0	0
T8	4287	52	0	0
T9	9735	0	0	0
T10	9668	0	0	0
T11	42259	0	0	0
T15	0	20	0	0
T26	0	100	0	0
T27	0	169	0	0
T28	0	231	0	0
T29	0	85	0	0
T30	0	740	0	0
T44	0	479	0	0
T46	0	100	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	461956249	461820799	0	0
T1	952	886	0	0
T2	2418	2357	0	0
T3	1718	1635	0	0
T4	67232	67166	0	0
T5	2198	2107	0	0
T6	5598	4103	0	0
T7	1923	1826	0	0
T8	4287	4217	0	0
T9	9735	9655	0	0
T10	9668	9605	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461956249	461820799	0	0
T1	952	886	0	0
T2	2418	2357	0	0
T3	1718	1635	0	0
T4	67232	67166	0	0
T5	2198	2107	0	0
T6	5598	4103	0	0
T7	1923	1826	0	0
T8	4287	4217	0	0
T9	9735	9655	0	0
T10	9668	9605	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461956249	461820799	0	0
T1	952	886	0	0
T2	2418	2357	0	0
T3	1718	1635	0	0
T4	67232	67166	0	0
T5	2198	2107	0	0
T6	5598	4103	0	0
T7	1923	1826	0	0
T8	4287	4217	0	0
T9	9735	9655	0	0
T10	9668	9605	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461956249	461820799	0	0
T1	952	886	0	0
T2	2418	2357	0	0
T3	1718	1635	0	0
T4	67232	67166	0	0
T5	2198	2107	0	0
T6	5598	4103	0	0
T7	1923	1826	0	0
T8	4287	4217	0	0
T9	9735	9655	0	0
T10	9668	9605	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	461956249	6007991	0	0
DataKnown_AKnownEnable	461956249	461820799	0	0
DepthKnown_A	461956249	461820799	0	0
RvalidKnown_A	461956249	461820799	0	0
WreadyKnown_A	461956249	461820799	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461956249	6007991	0	0
T1	952	77	0	0
T2	2418	1	0	0
T3	1718	1	0	0
T4	67232	381	0	0
T5	2198	17	0	0
T6	5598	1	0	0
T7	1923	3	0	0
T8	4287	375	0	0
T9	9735	50	0	0
T10	9668	413	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	461956249	461820799	0	0
T1	952	886	0	0
T2	2418	2357	0	0
T3	1718	1635	0	0
T4	67232	67166	0	0
T5	2198	2107	0	0
T6	5598	4103	0	0
T7	1923	1826	0	0
T8	4287	4217	0	0
T9	9735	9655	0	0
T10	9668	9605	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461956249	461820799	0	0
T1	952	886	0	0
T2	2418	2357	0	0
T3	1718	1635	0	0
T4	67232	67166	0	0
T5	2198	2107	0	0
T6	5598	4103	0	0
T7	1923	1826	0	0
T8	4287	4217	0	0
T9	9735	9655	0	0
T10	9668	9605	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461956249	461820799	0	0
T1	952	886	0	0
T2	2418	2357	0	0
T3	1718	1635	0	0
T4	67232	67166	0	0
T5	2198	2107	0	0
T6	5598	4103	0	0
T7	1923	1826	0	0
T8	4287	4217	0	0
T9	9735	9655	0	0
T10	9668	9605	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461956249	461820799	0	0
T1	952	886	0	0
T2	2418	2357	0	0
T3	1718	1635	0	0
T4	67232	67166	0	0
T5	2198	2107	0	0
T6	5598	4103	0	0
T7	1923	1826	0	0
T8	4287	4217	0	0
T9	9735	9655	0	0
T10	9668	9605	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	461956249	11901996	0	0
DataKnown_AKnownEnable	461956249	461820799	0	0
DepthKnown_A	461956249	461820799	0	0
RvalidKnown_A	461956249	461820799	0	0
WreadyKnown_A	461956249	461820799	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461956249	11901996	0	0
T1	952	77	0	0
T2	2418	1	0	0
T3	1718	7	0	0
T4	67232	1113	0	0
T5	2198	61	0	0
T6	5598	4	0	0
T7	1923	3	0	0
T8	4287	375	0	0
T9	9735	50	0	0
T10	9668	412	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	461956249	461820799	0	0
T1	952	886	0	0
T2	2418	2357	0	0
T3	1718	1635	0	0
T4	67232	67166	0	0
T5	2198	2107	0	0
T6	5598	4103	0	0
T7	1923	1826	0	0
T8	4287	4217	0	0
T9	9735	9655	0	0
T10	9668	9605	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461956249	461820799	0	0
T1	952	886	0	0
T2	2418	2357	0	0
T3	1718	1635	0	0
T4	67232	67166	0	0
T5	2198	2107	0	0
T6	5598	4103	0	0
T7	1923	1826	0	0
T8	4287	4217	0	0
T9	9735	9655	0	0
T10	9668	9605	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461956249	461820799	0	0
T1	952	886	0	0
T2	2418	2357	0	0
T3	1718	1635	0	0
T4	67232	67166	0	0
T5	2198	2107	0	0
T6	5598	4103	0	0
T7	1923	1826	0	0
T8	4287	4217	0	0
T9	9735	9655	0	0
T10	9668	9605	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461956249	461820799	0	0
T1	952	886	0	0
T2	2418	2357	0	0
T3	1718	1635	0	0
T4	67232	67166	0	0
T5	2198	2107	0	0
T6	5598	4103	0	0
T7	1923	1826	0	0
T8	4287	4217	0	0
T9	9735	9655	0	0
T10	9668	9605	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0