Line Coverage for Module :
tlul_adapter_sram ( parameter SramAw=10,SramDw=32,Outstanding=1,SramBusBankAW=12,ByteAccess=0,ErrOnWrite=0,ErrOnRead=1,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=0,SecFifoPtr=0,EnableReadback=0,DataXorAddr=0,WidthMult=1,DataOutW=32,DataBitWidth=2,WoffsetWidth=1,DataWidth=32 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 73 | 69 | 94.52 |
| CONT_ASSIGN | 107 | 0 | 0 | |
| CONT_ASSIGN | 114 | 0 | 0 | |
| ALWAYS | 129 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 176 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 272 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 273 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 274 | 1 | 1 | 100.00 |
| ALWAYS | 279 | 8 | 6 | 75.00 |
| ALWAYS | 299 | 6 | 5 | 83.33 |
| CONT_ASSIGN | 313 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 317 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 336 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 341 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 347 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 359 | 1 | 1 | 100.00 |
| ALWAYS | 362 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 369 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 390 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 391 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 392 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 393 | 1 | 1 | 100.00 |
| ALWAYS | 423 | 6 | 6 | 100.00 |
| ALWAYS | 435 | 5 | 5 | 100.00 |
| CONT_ASSIGN | 450 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 451 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 452 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 456 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 457 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 459 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 460 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 467 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 470 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 474 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 475 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 477 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 479 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 486 | 1 | 1 | 100.00 |
| ALWAYS | 517 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 523 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 526 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 531 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 536 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 620 | 1 | 1 | 100.00 |
106 logic unused_sram_byte_readback_error;
107 unreachable assign unused_sram_byte_readback_error = sram_byte_readback_error;
108 assign readback_error = '0;
109 assign readback_error_q = '0;
110 end
111
112 // readback error output is permanent and should be used for alert generation
113 // or other downstream effects
114 unreachable assign readback_error_o = readback_error | readback_error_q;
115
116 // integrity check
117 if (CmdIntgCheck) begin : gen_cmd_intg_check
118 tlul_cmd_intg_chk u_cmd_intg_chk (
119 .tl_i(tl_i),
120 .err_o (intg_error)
121 );
122 end else begin : gen_no_cmd_intg_check
123 assign intg_error = '0;
124 end
125
126 // permanently latch integrity error until reset
127 logic intg_error_q;
128 always_ff @(posedge clk_i or negedge rst_ni) begin
129 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
130 1/1 intg_error_q <= '0;
Tests: T1 T2 T3
131 1/1 end else if (intg_error || rsp_fifo_error || sramreqfifo_error || reqfifo_error) begin
Tests: T1 T2 T3
132 unreachable intg_error_q <= 1'b1;
133 end
MISSING_ELSE
134 end
135
136 // integrity error output is permanent and should be used for alert generation
137 // or other downstream effects
138 1/1 assign intg_error_o = intg_error | rsp_fifo_error | sramreqfifo_error |
Tests: T1 T2 T3
139 reqfifo_error | intg_error_q;
140
141 // wr_attr_error: Check if the request size, mask are permitted.
142 // Basic check of size, mask, addr align is done in tlul_err module.
143 // Here it checks any partial write if ByteAccess isn't allowed.
144 1/1 assign wr_attr_error = (tl_i.a_opcode == PutFullData || tl_i.a_opcode == PutPartialData)
Tests: T1 T2 T3
145 ? ((ByteAccess == 0) ?
146 (tl_i.a_mask != '1 || tl_i.a_size != 2'h2) : 1'b0)
147 : 1'b0;
148
149 // An instruction type transaction is only valid if en_ifetch is enabled
150 // If the instruction type is completely invalid, also considered an instruction error
151 1/1 assign instr_error = prim_mubi_pkg::mubi4_test_invalid(tl_i.a_user.instr_type) |
Tests: T1 T2 T3
152 (prim_mubi_pkg::mubi4_test_true_strict(tl_i.a_user.instr_type) &
153 prim_mubi_pkg::mubi4_test_false_loose(en_ifetch_i));
154
155 if (ErrOnWrite == 1) begin : gen_no_writes
156 assign wr_vld_error = tl_i.a_opcode != Get;
157 end else begin : gen_writes_allowed
158 assign wr_vld_error = 1'b0;
159 end
160
161 if (ErrOnRead == 1) begin: gen_no_reads
162 1/1 assign rd_vld_error = tl_i.a_opcode == Get;
Tests: T1 T2 T3
163 end else begin : gen_reads_allowed
164 assign rd_vld_error = 1'b0;
165 end
166
167 // tlul protocol check
168 tlul_err u_err (
169 .clk_i,
170 .rst_ni,
171 .tl_i(tl_i),
172 .err_o (tlul_error)
173 );
174
175 // error return is transactional and thus does not used the "latched" intg_err signal
176 1/1 assign error_det = wr_attr_error | wr_vld_error | rd_vld_error | instr_error |
Tests: T1 T2 T3
177 tlul_error | intg_error;
178
179 // from sram_byte to adapter logic
180 tl_h2d_t tl_i_int;
181 // from adapter logic to sram_byte
182 tl_d2h_t tl_o_int;
183 // from sram_byte to rsp_gen
184 tl_d2h_t tl_out;
185
186 // not all parts of tl_i_int are used
187 logic unused_tl_i_int;
188 1/1 assign unused_tl_i_int = ^tl_i_int;
Tests: T1 T2 T3
189
190 tlul_rsp_intg_gen #(
191 .EnableRspIntgGen(EnableRspIntgGen),
192 .EnableDataIntgGen(EnableDataIntgGen)
193 ) u_rsp_gen (
194 .tl_i(tl_out),
195 .tl_o
196 );
197
198 // byte handling for integrity
199 tlul_sram_byte #(
200 .EnableIntg(ByteAccess & EnableDataIntgPt & !ErrOnWrite),
201 .Outstanding(Outstanding),
202 .EnableReadback(EnableReadback)
203 ) u_sram_byte (
204 .clk_i,
205 .rst_ni,
206 .tl_i,
207 .tl_o(tl_out),
208 .tl_sram_o(tl_i_int),
209 .tl_sram_i(tl_o_int),
210 .error_i(error_det),
211 .error_o(error_internal),
212 .alert_o(sram_byte_readback_error),
213 .compound_txn_in_progress_o,
214 .readback_en_i,
215 .wr_collision_i,
216 .write_pending_i
217 );
218
219 typedef struct packed {
220 logic [top_pkg::TL_DBW-1:0] mask ; // Byte mask within the TL-UL word
221 logic [WoffsetWidth-1:0] woffset ; // Offset of the TL-UL word within the SRAM word
222 } sram_req_t ;
223
224 typedef struct packed {
225 logic [SramBusBankAW-1:0] addr; // Address of the request going to the memory.
226 } sram_req_addr_t ;
227
228 typedef enum logic [1:0] {
229 OpWrite,
230 OpRead,
231 OpUnknown
232 } req_op_e ;
233
234 typedef struct packed {
235 req_op_e op ;
236 logic error ;
237 prim_mubi_pkg::mubi4_t instr_type;
238 logic [top_pkg::TL_SZW-1:0] size ;
239 logic [top_pkg::TL_AIW-1:0] source ;
240 } req_t ;
241
242 typedef struct packed {
243 logic [top_pkg::TL_DW-1:0] data ;
244 logic [DataIntgWidth-1:0] data_intg ;
245 logic error ;
246 } rsp_t ;
247
248 localparam int SramReqFifoWidth = $bits(sram_req_t) ;
249 localparam int ReqFifoWidth = $bits(req_t) ;
250 localparam int RspFifoWidth = $bits(rsp_t) ;
251
252 // FIFO signal in case OutStand is greater than 1
253 // If request is latched, {write, source} is pushed to req fifo.
254 // Req fifo is popped when D channel is acknowledged (v & r)
255 // D channel valid is asserted if it is write request or rsp fifo not empty if read.
256 logic reqfifo_wvalid, reqfifo_wready;
257 logic reqfifo_rvalid, reqfifo_rready;
258 req_t reqfifo_wdata, reqfifo_rdata;
259
260 logic sramreqfifo_wvalid, sramreqfifo_wready;
261 logic sramreqfifo_rready;
262 sram_req_t sramreqfifo_wdata, sramreqfifo_rdata;
263
264 logic sramreqaddrfifo_wready;
265 logic [SramBusBankAW-1:0] sramreqaddrfifo_wdata, sramreqaddrfifo_rdata;
266
267 logic rspfifo_wvalid, rspfifo_wready;
268 logic rspfifo_rvalid, rspfifo_rready;
269 rsp_t rspfifo_wdata, rspfifo_rdata;
270
271 logic a_ack, d_ack, sram_ack;
272 1/1 assign a_ack = tl_i_int.a_valid & tl_o_int.a_ready ;
Tests: T1 T2 T3
273 1/1 assign d_ack = tl_o_int.d_valid & tl_i_int.d_ready ;
Tests: T1 T2 T3
274 1/1 assign sram_ack = req_o & gnt_i ;
Tests: T1 T2 T3
275
276 // Valid handling
277 logic d_valid, d_error;
278 always_comb begin
279 1/1 d_valid = 1'b0;
Tests: T1 T2 T3
280
281 1/1 if (reqfifo_rvalid) begin
Tests: T1 T2 T3
282 1/1 if (reqfifo_rdata.error) begin
Tests: T2 T9 T10
283 // Return error response. Assume no request went out to SRAM
284 0/1 ==> d_valid = 1'b1;
285 1/1 end else if (reqfifo_rdata.op == OpRead) begin
Tests: T2 T9 T10
286 0/1 ==> d_valid = rspfifo_rvalid;
287 end else begin
288 // Write without error
289 1/1 d_valid = 1'b1;
Tests: T2 T9 T10
290 end
291 end else begin
292 1/1 d_valid = 1'b0;
Tests: T1 T2 T3
293 end
294 end
295
296
297
298 always_comb begin
299 1/1 d_error = 1'b0;
Tests: T1 T2 T3
300
301 1/1 if (reqfifo_rvalid) begin
Tests: T1 T2 T3
302 1/1 if (reqfifo_rdata.op == OpRead) begin
Tests: T2 T9 T10
303 0/1 ==> d_error = rspfifo_rdata.error | reqfifo_rdata.error;
304 end else begin
305 1/1 d_error = reqfifo_rdata.error;
Tests: T2 T9 T10
306 end
307 end else begin
308 1/1 d_error = 1'b0;
Tests: T1 T2 T3
309 end
310 end
311
312 logic vld_rd_rsp;
313 1/1 assign vld_rd_rsp = d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead);
Tests: T1 T2 T3
314 // If the response data is not valid, we set it to an illegal blanking value which is determined
315 // by whether the current transaction is an instruction fetch or a regular read operation.
316 logic [top_pkg::TL_DW-1:0] error_blanking_data;
317 1/1 assign error_blanking_data = (prim_mubi_pkg::mubi4_test_true_strict(reqfifo_rdata.instr_type)) ?
Tests: T1 T2 T3
318 DataWhenInstrError :
319 DataWhenError;
320
321 // Since DataWhenInstrError and DataWhenError can be arbitrary parameters
322 // we statically calculate the correct integrity values for these parameters here so that
323 // they do not have to be supplied externally.
324 logic [top_pkg::TL_DW-1:0] unused_instr, unused_data;
325 logic [DataIntgWidth-1:0] error_instr_integ, error_data_integ;
326 tlul_data_integ_enc u_tlul_data_integ_enc_instr (
327 .data_i(DataMaxWidth'(DataWhenInstrError)),
328 .data_intg_o({error_instr_integ, unused_instr})
329 );
330 tlul_data_integ_enc u_tlul_data_integ_enc_data (
331 .data_i(DataMaxWidth'(DataWhenError)),
332 .data_intg_o({error_data_integ, unused_data})
333 );
334
335 logic [DataIntgWidth-1:0] error_blanking_integ;
336 1/1 assign error_blanking_integ = (prim_mubi_pkg::mubi4_test_true_strict(reqfifo_rdata.instr_type)) ?
Tests: T1 T2 T3
337 error_instr_integ :
338 error_data_integ;
339
340 logic [top_pkg::TL_DW-1:0] d_data;
341 1/1 assign d_data = (vld_rd_rsp & ~d_error) ? rspfifo_rdata.data // valid read
Tests: T1 T2 T3
342 : error_blanking_data; // write or TL-UL error
343
344 // If this a write response with data fields set to 0, we have to set all ECC bits correctly
345 // since we are using an inverted Hsiao code.
346 logic [DataIntgWidth-1:0] data_intg;
347 1/1 assign data_intg = (vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : // TL-UL error
Tests: T1 T2 T3
348 (vld_rd_rsp) ? rspfifo_rdata.data_intg : // valid read
349 prim_secded_pkg::SecdedInv3932ZeroEcc; // valid write
350
351 // When an error is seen on an incoming transaction it gets an immediate response without
352 // performing an SRAM request. It may be the transaction receives a ready the first cycle it is
353 // seen, but if not we force a ready the following cycle. This avoids factoring the error
354 // calculation into the outgoing ready preventing a feedthrough path from the incoming tilelink
355 // signals to the outgoing tilelink signals.
356 logic missed_err_gnt_d, missed_err_gnt_q;
357
358 // Track whether we've seen an incoming transaction with an error that didn't get a ready
359 1/1 assign missed_err_gnt_d = error_internal & tl_i_int.a_valid & ~tl_o_int.a_ready;
Tests: T1 T2 T3
360
361 always_ff @(posedge clk_i or negedge rst_ni) begin
362 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
363 1/1 missed_err_gnt_q <= 1'b0;
Tests: T1 T2 T3
364 end else begin
365 1/1 missed_err_gnt_q <= missed_err_gnt_d;
Tests: T1 T2 T3
366 end
367 end
368
369 1/1 assign tl_o_int = '{
Tests: T1 T2 T3
370 d_valid : d_valid ,
371 d_opcode : (d_valid && reqfifo_rdata.op != OpRead) ? AccessAck : AccessAckData,
372 d_param : '0,
373 d_size : (d_valid) ? reqfifo_rdata.size : '0,
374 d_source : (d_valid) ? reqfifo_rdata.source : '0,
375 d_sink : 1'b0,
376 d_data : d_data,
377 d_user : '{default: '0, data_intg: data_intg},
378 d_error : d_valid && d_error,
379 a_ready : (gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready &
380 sramreqaddrfifo_wready
381 };
382
383 // a_ready depends on the FIFO full condition and grant from SRAM (or SRAM arbiter)
384 // assemble response, including read response, write response, and error for unsupported stuff
385
386 // Output to SRAM:
387 // Generate request only when no internal error occurs. If error occurs, the request should be
388 // dropped and returned error response to the host. So, error to be pushed to reqfifo.
389 // In this case, it is assumed the request is granted (may cause ordering issue later?)
390 1/1 assign req_o = tl_i_int.a_valid & reqfifo_wready & ~error_internal;
Tests: T1 T2 T3
391 1/1 assign req_type_o = tl_i_int.a_user.instr_type;
Tests: T1 T2 T3
392 1/1 assign we_o = tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData});
Tests: T1 T2 T3
393 1/1 assign addr_o = (tl_i_int.a_valid) ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0;
Tests: T1 T2 T3
394
395 // Support SRAMs wider than the TL-UL word width by mapping the parts of the
396 // TL-UL address which are more fine-granular than the SRAM width to the
397 // SRAM write mask.
398 logic [WoffsetWidth-1:0] woffset;
399 if (top_pkg::TL_DW != SramDw) begin : gen_wordwidthadapt
400 assign woffset = tl_i_int.a_address[DataBitWidth-1:prim_util_pkg::vbits(top_pkg::TL_DBW)];
401 end else begin : gen_no_wordwidthadapt
402 assign woffset = '0;
403 end
404
405 // The size of the data/wmask depends on whether passthrough integrity is enabled.
406 // If passthrough integrity is enabled, the data is concatenated with the integrity passed through
407 // the user bits. Otherwise, it is the data only.
408 localparam int DataWidth = EnableDataIntgPt ? top_pkg::TL_DW + DataIntgWidth : top_pkg::TL_DW;
409
410 // Final combined wmask / wdata
411 logic [WidthMult-1:0][DataWidth-1:0] wmask_combined;
412 logic [WidthMult-1:0][DataWidth-1:0] wdata_combined;
413
414 // Original tlul portion
415 logic [WidthMult-1:0][top_pkg::TL_DW-1:0] wmask_int;
416 logic [WidthMult-1:0][top_pkg::TL_DW-1:0] wdata_int;
417
418 // Integrity portion
419 logic [WidthMult-1:0][DataIntgWidth-1:0] wmask_intg;
420 logic [WidthMult-1:0][DataIntgWidth-1:0] wdata_intg;
421
422 always_comb begin
423 1/1 wmask_int = '0;
Tests: T1 T2 T3
424 1/1 wdata_int = '0;
Tests: T1 T2 T3
425
426 1/1 if (tl_i_int.a_valid) begin
Tests: T1 T2 T3
427 1/1 for (int i = 0 ; i < top_pkg::TL_DW/8 ; i++) begin
Tests: T2 T9 T10
428 1/1 wmask_int[woffset][8*i +: 8] = {8{tl_i_int.a_mask[i]}};
Tests: T2 T9 T10
429 1/1 wdata_int[woffset][8*i +: 8] = (tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[8*i+:8] : '0;
Tests: T2 T9 T10
430 end
431 end
MISSING_ELSE
432 end
433
434 always_comb begin
435 1/1 wmask_intg = '0;
Tests: T1 T2 T3
436 1/1 wdata_intg = '0;
Tests: T1 T2 T3
437
438 1/1 if (tl_i_int.a_valid) begin
Tests: T1 T2 T3
439 1/1 wmask_intg[woffset] = {DataIntgWidth{1'b1}};
Tests: T2 T9 T10
440 1/1 wdata_intg[woffset] = tl_i_int.a_user.data_intg;
Tests: T2 T9 T10
441 end
MISSING_ELSE
442 end
443
444 for (genvar i = 0; i < WidthMult; i++) begin : gen_write_output
445 if (EnableDataIntgPt) begin : gen_combined_output
446 assign wmask_combined[i] = {wmask_intg[i], wmask_int[i]};
447 assign wdata_combined[i] = {wdata_intg[i], wdata_int[i]};
448 end else begin : gen_ft_output
449 logic unused_w;
450 1/1 assign wmask_combined[i] = wmask_int[i];
Tests: T1 T2 T3
451 1/1 assign wdata_combined[i] = wdata_int[i];
Tests: T1 T2 T3
452 1/1 assign unused_w = |wmask_intg & |wdata_intg;
Tests: T1 T2 T3
453 end
454 end
455
456 1/1 assign wmask_o = wmask_combined;
Tests: T1 T2 T3
457 1/1 assign wdata_o = wdata_combined;
Tests: T1 T2 T3
458
459 1/1 assign reqfifo_wvalid = a_ack ; // Push to FIFO only when granted
Tests: T2 T9 T10
460 1/1 assign reqfifo_wdata = '{
Tests: T1 T2 T3
461 op: (tl_i_int.a_opcode != Get) ? OpWrite : OpRead, // To return AccessAck for opcode error
462 error: error_internal,
463 instr_type: tl_i_int.a_user.instr_type,
464 size: tl_i_int.a_size,
465 source: tl_i_int.a_source
466 }; // Store the request only. Doesn't have to store data
467 1/1 assign reqfifo_rready = d_ack ;
Tests: T2 T9 T10
468
469 // push together with ReqFIFO, pop upon returning read
470 1/1 assign sramreqfifo_wdata = '{
Tests: T1 T2 T3
471 mask : tl_i_int.a_mask,
472 woffset : woffset
473 };
474 1/1 assign sramreqfifo_wvalid = sram_ack & ~we_o;
Tests: T1 T2 T3
475 1/1 assign sramreqfifo_rready = rspfifo_wvalid;
Tests: T1 T2 T3
476
477 1/1 assign rspfifo_wvalid = rvalid_i & reqfifo_rvalid;
Tests: T1 T2 T3
478
479 1/1 assign sramreqaddrfifo_wdata = tl_i_int.a_address[DataBitWidth+:SramBusBankAW];
Tests: T1 T2 T3
480
481 // Make sure only requested bytes are forwarded
482 logic [WidthMult-1:0][DataWidth-1:0] rdata_reshaped;
483 logic [DataWidth-1:0] rdata_tlword;
484
485 // This just changes the array format so that the correct word can be selected by indexing.
486 1/1 assign rdata_reshaped = rdata_i;
Tests: T2 T8 T26
487
488 if (EnableDataIntgPt) begin : gen_no_rmask
489 always_comb begin
490 // If the read mask is set to zero, all read data is zeroed out by the mask.
491 // We have to set the ECC bits accordingly since we are using an inverted Hsiao code.
492 rdata_tlword = prim_secded_pkg::SecdedInv3932ZeroWord;
493 // Otherwise, if at least one mask bit is nonzero, we are passing through the integrity.
494 // In that case we need to feed back the entire word since otherwise the integrity
495 // will not calculate correctly.
496 if (|sramreqfifo_rdata.mask) begin
497 // Select correct word.
498 if (DataXorAddr) begin : gen_data_xor_addr
499 // When DataXorAddr is enabled, on a read, the address is XORed with the data fetched from
500 // the memory in the underlying memory controller (e.g., flash controller). At this point,
501 // the address is again removed. If the address in the read transaction has been modified,
502 // e.g., due to a fault, rdata now contains faulty data, which is detected by the
503 // integrity mechanism.
504 rdata_tlword = {
505 rdata_reshaped[sramreqfifo_rdata.woffset][DataWidth-1:top_pkg::TL_DW],
506 rdata_reshaped[sramreqfifo_rdata.woffset][top_pkg::TL_DW-1:0] ^
507 {{(top_pkg::TL_DW-SramBusBankAW){1'b0}}, sramreqaddrfifo_rdata}
508 };
509 end else begin: gen_no_data_xor_addr
510 rdata_tlword = rdata_reshaped[sramreqfifo_rdata.woffset];
511 end
512 end
513 end
514 end else begin : gen_rmask
515 logic [DataWidth-1:0] rmask;
516 always_comb begin
517 1/1 rmask = '0;
Tests: T1 T2 T3
518 1/1 for (int i = 0 ; i < top_pkg::TL_DW/8 ; i++) begin
Tests: T1 T2 T3
519 1/1 rmask[8*i +: 8] = {8{sramreqfifo_rdata.mask[i]}};
Tests: T1 T2 T3
520 end
521 end
522 // Select correct word and mask it.
523 1/1 assign rdata_tlword = rdata_reshaped[sramreqfifo_rdata.woffset] & rmask;
Tests: T1 T2 T3
524 end
525
526 1/1 assign rspfifo_wdata = '{
Tests: T1 T2 T3
527 data : rdata_tlword[top_pkg::TL_DW-1:0],
528 data_intg : EnableDataIntgPt ? rdata_tlword[DataWidth-1 -: DataIntgWidth] : '0,
529 error : rerror_i[1] // Only care for Uncorrectable error
530 };
531 1/1 assign rspfifo_rready = (reqfifo_rdata.op == OpRead & ~reqfifo_rdata.error)
Tests: T1 T2 T3
532 ? reqfifo_rready : 1'b0 ;
533
534 // This module only cares about uncorrectable errors.
535 logic unused_rerror;
536 0/1 ==> assign unused_rerror = rerror_i[0];
537
538 // FIFO instance: REQ, RSP
539
540 // ReqFIFO is to store the Access type to match to the Response data.
541 // For instance, SRAM accepts the write request but doesn't return the
542 // acknowledge. In this case, it may be hard to determine when the D
543 // response for the write data should send out if reads/writes are
544 // interleaved. So, to make it in-order (even TL-UL allows out-of-order
545 // responses), storing the request is necessary. And if the read entry
546 // is write op, it is safe to return the response right away. If it is
547 // read reqeust, then D response is waiting until read data arrives.
548 prim_fifo_sync #(
549 .Width (ReqFifoWidth),
550 .Pass (1'b0),
551 .Depth (Outstanding),
552 .Secure (SecFifoPtr)
553 ) u_reqfifo (
554 .clk_i,
555 .rst_ni,
556 .clr_i (1'b0),
557 .wvalid_i(reqfifo_wvalid),
558 .wready_o(reqfifo_wready),
559 .wdata_i (reqfifo_wdata),
560 .rvalid_o(reqfifo_rvalid),
561 .rready_i(reqfifo_rready),
562 .rdata_o (reqfifo_rdata),
563 .full_o (),
564 .depth_o (),
565 .err_o (reqfifo_error)
566 );
567
568 // sramreqfifo:
569 // While the ReqFIFO holds the request until it is sent back via TL-UL, the
570 // sramreqfifo only needs to hold the mask and word offset until the read
571 // data returns from memory.
572 prim_fifo_sync #(
573 .Width (SramReqFifoWidth),
574 .Pass (1'b0),
575 .Depth (Outstanding),
576 .Secure (SecFifoPtr)
577 ) u_sramreqfifo (
578 .clk_i,
579 .rst_ni,
580 .clr_i (1'b0),
581 .wvalid_i(sramreqfifo_wvalid),
582 .wready_o(sramreqfifo_wready),
583 .wdata_i (sramreqfifo_wdata),
584 .rvalid_o(),
585 .rready_i(sramreqfifo_rready),
586 .rdata_o (sramreqfifo_rdata),
587 .full_o (),
588 .depth_o (),
589 .err_o (sramreqfifo_error)
590 );
591
592 // sramreqaddrfifo:
593 // This fifo holds the address used for undoing the address XOR data infection.
594 if (DataXorAddr) begin : gen_data_xor_addr_fifo
595 prim_fifo_sync #(
596 .Width (SramBusBankAW),
597 .Pass (1'b0),
598 .Depth (Outstanding),
599 .OutputZeroIfEmpty (1)
600 ) u_sramreqaddrfifo (
601 .clk_i,
602 .rst_ni,
603 .clr_i (1'b0),
604 .wvalid_i(sramreqfifo_wvalid),
605 .wready_o(sramreqaddrfifo_wready),
606 .wdata_i (sramreqaddrfifo_wdata),
607 .rvalid_o(),
608 .rready_i(sramreqfifo_rready),
609 .rdata_o (sramreqaddrfifo_rdata),
610 .full_o (),
611 .depth_o (),
612 .err_o ()
613 );
614 end else begin : gen_no_data_xor_addr_fifo
615 assign sramreqaddrfifo_wready = 1'b1;
616 assign sramreqaddrfifo_rdata = '0;
617
618 // Tie-off unused signals
619 logic unused_sramreqaddrfifo;
620 1/1 assign unused_sramreqaddrfifo = ^{sramreqaddrfifo_wdata, sramreqaddrfifo_rdata};
Tests: T1 T2 T3
Line Coverage for Module :
tlul_adapter_sram ( parameter SramAw=10,SramDw=32,Outstanding=1,SramBusBankAW=12,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=0,SecFifoPtr=0,EnableReadback=0,DataXorAddr=0,WidthMult=1,DataOutW=32,DataBitWidth=2,WoffsetWidth=1,DataWidth=32 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 73 | 69 | 94.52 |
| CONT_ASSIGN | 107 | 0 | 0 | |
| CONT_ASSIGN | 114 | 0 | 0 | |
| ALWAYS | 129 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 176 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 272 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 273 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 274 | 1 | 1 | 100.00 |
| ALWAYS | 279 | 8 | 6 | 75.00 |
| ALWAYS | 299 | 6 | 5 | 83.33 |
| CONT_ASSIGN | 313 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 317 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 336 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 341 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 347 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 359 | 1 | 1 | 100.00 |
| ALWAYS | 362 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 369 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 390 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 391 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 392 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 393 | 1 | 1 | 100.00 |
| ALWAYS | 423 | 6 | 6 | 100.00 |
| ALWAYS | 435 | 5 | 5 | 100.00 |
| CONT_ASSIGN | 450 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 451 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 452 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 456 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 457 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 459 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 460 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 467 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 470 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 474 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 475 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 477 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 479 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 486 | 1 | 1 | 100.00 |
| ALWAYS | 517 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 523 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 526 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 531 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 536 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 620 | 1 | 1 | 100.00 |
106 logic unused_sram_byte_readback_error;
107 unreachable assign unused_sram_byte_readback_error = sram_byte_readback_error;
108 assign readback_error = '0;
109 assign readback_error_q = '0;
110 end
111
112 // readback error output is permanent and should be used for alert generation
113 // or other downstream effects
114 unreachable assign readback_error_o = readback_error | readback_error_q;
115
116 // integrity check
117 if (CmdIntgCheck) begin : gen_cmd_intg_check
118 tlul_cmd_intg_chk u_cmd_intg_chk (
119 .tl_i(tl_i),
120 .err_o (intg_error)
121 );
122 end else begin : gen_no_cmd_intg_check
123 assign intg_error = '0;
124 end
125
126 // permanently latch integrity error until reset
127 logic intg_error_q;
128 always_ff @(posedge clk_i or negedge rst_ni) begin
129 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
130 1/1 intg_error_q <= '0;
Tests: T1 T2 T3
131 1/1 end else if (intg_error || rsp_fifo_error || sramreqfifo_error || reqfifo_error) begin
Tests: T1 T2 T3
132 unreachable intg_error_q <= 1'b1;
133 end
MISSING_ELSE
134 end
135
136 // integrity error output is permanent and should be used for alert generation
137 // or other downstream effects
138 1/1 assign intg_error_o = intg_error | rsp_fifo_error | sramreqfifo_error |
Tests: T1 T2 T3
139 reqfifo_error | intg_error_q;
140
141 // wr_attr_error: Check if the request size, mask are permitted.
142 // Basic check of size, mask, addr align is done in tlul_err module.
143 // Here it checks any partial write if ByteAccess isn't allowed.
144 1/1 assign wr_attr_error = (tl_i.a_opcode == PutFullData || tl_i.a_opcode == PutPartialData)
Tests: T1 T2 T3
145 ? ((ByteAccess == 0) ?
146 (tl_i.a_mask != '1 || tl_i.a_size != 2'h2) : 1'b0)
147 : 1'b0;
148
149 // An instruction type transaction is only valid if en_ifetch is enabled
150 // If the instruction type is completely invalid, also considered an instruction error
151 1/1 assign instr_error = prim_mubi_pkg::mubi4_test_invalid(tl_i.a_user.instr_type) |
Tests: T1 T2 T3
152 (prim_mubi_pkg::mubi4_test_true_strict(tl_i.a_user.instr_type) &
153 prim_mubi_pkg::mubi4_test_false_loose(en_ifetch_i));
154
155 if (ErrOnWrite == 1) begin : gen_no_writes
156 1/1 assign wr_vld_error = tl_i.a_opcode != Get;
Tests: T1 T2 T3
157 end else begin : gen_writes_allowed
158 assign wr_vld_error = 1'b0;
159 end
160
161 if (ErrOnRead == 1) begin: gen_no_reads
162 assign rd_vld_error = tl_i.a_opcode == Get;
163 end else begin : gen_reads_allowed
164 assign rd_vld_error = 1'b0;
165 end
166
167 // tlul protocol check
168 tlul_err u_err (
169 .clk_i,
170 .rst_ni,
171 .tl_i(tl_i),
172 .err_o (tlul_error)
173 );
174
175 // error return is transactional and thus does not used the "latched" intg_err signal
176 1/1 assign error_det = wr_attr_error | wr_vld_error | rd_vld_error | instr_error |
Tests: T1 T2 T3
177 tlul_error | intg_error;
178
179 // from sram_byte to adapter logic
180 tl_h2d_t tl_i_int;
181 // from adapter logic to sram_byte
182 tl_d2h_t tl_o_int;
183 // from sram_byte to rsp_gen
184 tl_d2h_t tl_out;
185
186 // not all parts of tl_i_int are used
187 logic unused_tl_i_int;
188 1/1 assign unused_tl_i_int = ^tl_i_int;
Tests: T1 T2 T3
189
190 tlul_rsp_intg_gen #(
191 .EnableRspIntgGen(EnableRspIntgGen),
192 .EnableDataIntgGen(EnableDataIntgGen)
193 ) u_rsp_gen (
194 .tl_i(tl_out),
195 .tl_o
196 );
197
198 // byte handling for integrity
199 tlul_sram_byte #(
200 .EnableIntg(ByteAccess & EnableDataIntgPt & !ErrOnWrite),
201 .Outstanding(Outstanding),
202 .EnableReadback(EnableReadback)
203 ) u_sram_byte (
204 .clk_i,
205 .rst_ni,
206 .tl_i,
207 .tl_o(tl_out),
208 .tl_sram_o(tl_i_int),
209 .tl_sram_i(tl_o_int),
210 .error_i(error_det),
211 .error_o(error_internal),
212 .alert_o(sram_byte_readback_error),
213 .compound_txn_in_progress_o,
214 .readback_en_i,
215 .wr_collision_i,
216 .write_pending_i
217 );
218
219 typedef struct packed {
220 logic [top_pkg::TL_DBW-1:0] mask ; // Byte mask within the TL-UL word
221 logic [WoffsetWidth-1:0] woffset ; // Offset of the TL-UL word within the SRAM word
222 } sram_req_t ;
223
224 typedef struct packed {
225 logic [SramBusBankAW-1:0] addr; // Address of the request going to the memory.
226 } sram_req_addr_t ;
227
228 typedef enum logic [1:0] {
229 OpWrite,
230 OpRead,
231 OpUnknown
232 } req_op_e ;
233
234 typedef struct packed {
235 req_op_e op ;
236 logic error ;
237 prim_mubi_pkg::mubi4_t instr_type;
238 logic [top_pkg::TL_SZW-1:0] size ;
239 logic [top_pkg::TL_AIW-1:0] source ;
240 } req_t ;
241
242 typedef struct packed {
243 logic [top_pkg::TL_DW-1:0] data ;
244 logic [DataIntgWidth-1:0] data_intg ;
245 logic error ;
246 } rsp_t ;
247
248 localparam int SramReqFifoWidth = $bits(sram_req_t) ;
249 localparam int ReqFifoWidth = $bits(req_t) ;
250 localparam int RspFifoWidth = $bits(rsp_t) ;
251
252 // FIFO signal in case OutStand is greater than 1
253 // If request is latched, {write, source} is pushed to req fifo.
254 // Req fifo is popped when D channel is acknowledged (v & r)
255 // D channel valid is asserted if it is write request or rsp fifo not empty if read.
256 logic reqfifo_wvalid, reqfifo_wready;
257 logic reqfifo_rvalid, reqfifo_rready;
258 req_t reqfifo_wdata, reqfifo_rdata;
259
260 logic sramreqfifo_wvalid, sramreqfifo_wready;
261 logic sramreqfifo_rready;
262 sram_req_t sramreqfifo_wdata, sramreqfifo_rdata;
263
264 logic sramreqaddrfifo_wready;
265 logic [SramBusBankAW-1:0] sramreqaddrfifo_wdata, sramreqaddrfifo_rdata;
266
267 logic rspfifo_wvalid, rspfifo_wready;
268 logic rspfifo_rvalid, rspfifo_rready;
269 rsp_t rspfifo_wdata, rspfifo_rdata;
270
271 logic a_ack, d_ack, sram_ack;
272 1/1 assign a_ack = tl_i_int.a_valid & tl_o_int.a_ready ;
Tests: T1 T2 T3
273 1/1 assign d_ack = tl_o_int.d_valid & tl_i_int.d_ready ;
Tests: T1 T2 T3
274 1/1 assign sram_ack = req_o & gnt_i ;
Tests: T1 T2 T3
275
276 // Valid handling
277 logic d_valid, d_error;
278 always_comb begin
279 1/1 d_valid = 1'b0;
Tests: T1 T2 T3
280
281 1/1 if (reqfifo_rvalid) begin
Tests: T1 T2 T3
282 1/1 if (reqfifo_rdata.error) begin
Tests: T2 T8 T26
283 // Return error response. Assume no request went out to SRAM
284 0/1 ==> d_valid = 1'b1;
285 1/1 end else if (reqfifo_rdata.op == OpRead) begin
Tests: T2 T8 T26
286 1/1 d_valid = rspfifo_rvalid;
Tests: T2 T8 T26
287 end else begin
288 // Write without error
289 0/1 ==> d_valid = 1'b1;
290 end
291 end else begin
292 1/1 d_valid = 1'b0;
Tests: T1 T2 T3
293 end
294 end
295
296
297
298 always_comb begin
299 1/1 d_error = 1'b0;
Tests: T1 T2 T3
300
301 1/1 if (reqfifo_rvalid) begin
Tests: T1 T2 T3
302 1/1 if (reqfifo_rdata.op == OpRead) begin
Tests: T2 T8 T26
303 1/1 d_error = rspfifo_rdata.error | reqfifo_rdata.error;
Tests: T2 T8 T26
304 end else begin
305 0/1 ==> d_error = reqfifo_rdata.error;
306 end
307 end else begin
308 1/1 d_error = 1'b0;
Tests: T1 T2 T3
309 end
310 end
311
312 logic vld_rd_rsp;
313 1/1 assign vld_rd_rsp = d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead);
Tests: T1 T2 T3
314 // If the response data is not valid, we set it to an illegal blanking value which is determined
315 // by whether the current transaction is an instruction fetch or a regular read operation.
316 logic [top_pkg::TL_DW-1:0] error_blanking_data;
317 1/1 assign error_blanking_data = (prim_mubi_pkg::mubi4_test_true_strict(reqfifo_rdata.instr_type)) ?
Tests: T1 T2 T3
318 DataWhenInstrError :
319 DataWhenError;
320
321 // Since DataWhenInstrError and DataWhenError can be arbitrary parameters
322 // we statically calculate the correct integrity values for these parameters here so that
323 // they do not have to be supplied externally.
324 logic [top_pkg::TL_DW-1:0] unused_instr, unused_data;
325 logic [DataIntgWidth-1:0] error_instr_integ, error_data_integ;
326 tlul_data_integ_enc u_tlul_data_integ_enc_instr (
327 .data_i(DataMaxWidth'(DataWhenInstrError)),
328 .data_intg_o({error_instr_integ, unused_instr})
329 );
330 tlul_data_integ_enc u_tlul_data_integ_enc_data (
331 .data_i(DataMaxWidth'(DataWhenError)),
332 .data_intg_o({error_data_integ, unused_data})
333 );
334
335 logic [DataIntgWidth-1:0] error_blanking_integ;
336 1/1 assign error_blanking_integ = (prim_mubi_pkg::mubi4_test_true_strict(reqfifo_rdata.instr_type)) ?
Tests: T1 T2 T3
337 error_instr_integ :
338 error_data_integ;
339
340 logic [top_pkg::TL_DW-1:0] d_data;
341 1/1 assign d_data = (vld_rd_rsp & ~d_error) ? rspfifo_rdata.data // valid read
Tests: T1 T2 T3
342 : error_blanking_data; // write or TL-UL error
343
344 // If this a write response with data fields set to 0, we have to set all ECC bits correctly
345 // since we are using an inverted Hsiao code.
346 logic [DataIntgWidth-1:0] data_intg;
347 1/1 assign data_intg = (vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : // TL-UL error
Tests: T1 T2 T3
348 (vld_rd_rsp) ? rspfifo_rdata.data_intg : // valid read
349 prim_secded_pkg::SecdedInv3932ZeroEcc; // valid write
350
351 // When an error is seen on an incoming transaction it gets an immediate response without
352 // performing an SRAM request. It may be the transaction receives a ready the first cycle it is
353 // seen, but if not we force a ready the following cycle. This avoids factoring the error
354 // calculation into the outgoing ready preventing a feedthrough path from the incoming tilelink
355 // signals to the outgoing tilelink signals.
356 logic missed_err_gnt_d, missed_err_gnt_q;
357
358 // Track whether we've seen an incoming transaction with an error that didn't get a ready
359 1/1 assign missed_err_gnt_d = error_internal & tl_i_int.a_valid & ~tl_o_int.a_ready;
Tests: T1 T2 T3
360
361 always_ff @(posedge clk_i or negedge rst_ni) begin
362 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
363 1/1 missed_err_gnt_q <= 1'b0;
Tests: T1 T2 T3
364 end else begin
365 1/1 missed_err_gnt_q <= missed_err_gnt_d;
Tests: T1 T2 T3
366 end
367 end
368
369 1/1 assign tl_o_int = '{
Tests: T1 T2 T3
370 d_valid : d_valid ,
371 d_opcode : (d_valid && reqfifo_rdata.op != OpRead) ? AccessAck : AccessAckData,
372 d_param : '0,
373 d_size : (d_valid) ? reqfifo_rdata.size : '0,
374 d_source : (d_valid) ? reqfifo_rdata.source : '0,
375 d_sink : 1'b0,
376 d_data : d_data,
377 d_user : '{default: '0, data_intg: data_intg},
378 d_error : d_valid && d_error,
379 a_ready : (gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready &
380 sramreqaddrfifo_wready
381 };
382
383 // a_ready depends on the FIFO full condition and grant from SRAM (or SRAM arbiter)
384 // assemble response, including read response, write response, and error for unsupported stuff
385
386 // Output to SRAM:
387 // Generate request only when no internal error occurs. If error occurs, the request should be
388 // dropped and returned error response to the host. So, error to be pushed to reqfifo.
389 // In this case, it is assumed the request is granted (may cause ordering issue later?)
390 1/1 assign req_o = tl_i_int.a_valid & reqfifo_wready & ~error_internal;
Tests: T1 T2 T3
391 1/1 assign req_type_o = tl_i_int.a_user.instr_type;
Tests: T1 T2 T3
392 1/1 assign we_o = tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData});
Tests: T1 T2 T3
393 1/1 assign addr_o = (tl_i_int.a_valid) ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0;
Tests: T1 T2 T3
394
395 // Support SRAMs wider than the TL-UL word width by mapping the parts of the
396 // TL-UL address which are more fine-granular than the SRAM width to the
397 // SRAM write mask.
398 logic [WoffsetWidth-1:0] woffset;
399 if (top_pkg::TL_DW != SramDw) begin : gen_wordwidthadapt
400 assign woffset = tl_i_int.a_address[DataBitWidth-1:prim_util_pkg::vbits(top_pkg::TL_DBW)];
401 end else begin : gen_no_wordwidthadapt
402 assign woffset = '0;
403 end
404
405 // The size of the data/wmask depends on whether passthrough integrity is enabled.
406 // If passthrough integrity is enabled, the data is concatenated with the integrity passed through
407 // the user bits. Otherwise, it is the data only.
408 localparam int DataWidth = EnableDataIntgPt ? top_pkg::TL_DW + DataIntgWidth : top_pkg::TL_DW;
409
410 // Final combined wmask / wdata
411 logic [WidthMult-1:0][DataWidth-1:0] wmask_combined;
412 logic [WidthMult-1:0][DataWidth-1:0] wdata_combined;
413
414 // Original tlul portion
415 logic [WidthMult-1:0][top_pkg::TL_DW-1:0] wmask_int;
416 logic [WidthMult-1:0][top_pkg::TL_DW-1:0] wdata_int;
417
418 // Integrity portion
419 logic [WidthMult-1:0][DataIntgWidth-1:0] wmask_intg;
420 logic [WidthMult-1:0][DataIntgWidth-1:0] wdata_intg;
421
422 always_comb begin
423 1/1 wmask_int = '0;
Tests: T1 T2 T3
424 1/1 wdata_int = '0;
Tests: T1 T2 T3
425
426 1/1 if (tl_i_int.a_valid) begin
Tests: T1 T2 T3
427 1/1 for (int i = 0 ; i < top_pkg::TL_DW/8 ; i++) begin
Tests: T2 T8 T26
428 1/1 wmask_int[woffset][8*i +: 8] = {8{tl_i_int.a_mask[i]}};
Tests: T2 T8 T26
429 1/1 wdata_int[woffset][8*i +: 8] = (tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[8*i+:8] : '0;
Tests: T2 T8 T26
430 end
431 end
MISSING_ELSE
432 end
433
434 always_comb begin
435 1/1 wmask_intg = '0;
Tests: T1 T2 T3
436 1/1 wdata_intg = '0;
Tests: T1 T2 T3
437
438 1/1 if (tl_i_int.a_valid) begin
Tests: T1 T2 T3
439 1/1 wmask_intg[woffset] = {DataIntgWidth{1'b1}};
Tests: T2 T8 T26
440 1/1 wdata_intg[woffset] = tl_i_int.a_user.data_intg;
Tests: T2 T8 T26
441 end
MISSING_ELSE
442 end
443
444 for (genvar i = 0; i < WidthMult; i++) begin : gen_write_output
445 if (EnableDataIntgPt) begin : gen_combined_output
446 assign wmask_combined[i] = {wmask_intg[i], wmask_int[i]};
447 assign wdata_combined[i] = {wdata_intg[i], wdata_int[i]};
448 end else begin : gen_ft_output
449 logic unused_w;
450 1/1 assign wmask_combined[i] = wmask_int[i];
Tests: T1 T2 T3
451 1/1 assign wdata_combined[i] = wdata_int[i];
Tests: T1 T2 T3
452 1/1 assign unused_w = |wmask_intg & |wdata_intg;
Tests: T1 T2 T3
453 end
454 end
455
456 1/1 assign wmask_o = wmask_combined;
Tests: T1 T2 T3
457 1/1 assign wdata_o = wdata_combined;
Tests: T1 T2 T3
458
459 1/1 assign reqfifo_wvalid = a_ack ; // Push to FIFO only when granted
Tests: T2 T8 T26
460 1/1 assign reqfifo_wdata = '{
Tests: T1 T2 T3
461 op: (tl_i_int.a_opcode != Get) ? OpWrite : OpRead, // To return AccessAck for opcode error
462 error: error_internal,
463 instr_type: tl_i_int.a_user.instr_type,
464 size: tl_i_int.a_size,
465 source: tl_i_int.a_source
466 }; // Store the request only. Doesn't have to store data
467 1/1 assign reqfifo_rready = d_ack ;
Tests: T2 T8 T26
468
469 // push together with ReqFIFO, pop upon returning read
470 1/1 assign sramreqfifo_wdata = '{
Tests: T1 T2 T3
471 mask : tl_i_int.a_mask,
472 woffset : woffset
473 };
474 1/1 assign sramreqfifo_wvalid = sram_ack & ~we_o;
Tests: T1 T2 T3
475 1/1 assign sramreqfifo_rready = rspfifo_wvalid;
Tests: T1 T2 T3
476
477 1/1 assign rspfifo_wvalid = rvalid_i & reqfifo_rvalid;
Tests: T1 T2 T3
478
479 1/1 assign sramreqaddrfifo_wdata = tl_i_int.a_address[DataBitWidth+:SramBusBankAW];
Tests: T1 T2 T3
480
481 // Make sure only requested bytes are forwarded
482 logic [WidthMult-1:0][DataWidth-1:0] rdata_reshaped;
483 logic [DataWidth-1:0] rdata_tlword;
484
485 // This just changes the array format so that the correct word can be selected by indexing.
486 1/1 assign rdata_reshaped = rdata_i;
Tests: T2 T8 T26
487
488 if (EnableDataIntgPt) begin : gen_no_rmask
489 always_comb begin
490 // If the read mask is set to zero, all read data is zeroed out by the mask.
491 // We have to set the ECC bits accordingly since we are using an inverted Hsiao code.
492 rdata_tlword = prim_secded_pkg::SecdedInv3932ZeroWord;
493 // Otherwise, if at least one mask bit is nonzero, we are passing through the integrity.
494 // In that case we need to feed back the entire word since otherwise the integrity
495 // will not calculate correctly.
496 if (|sramreqfifo_rdata.mask) begin
497 // Select correct word.
498 if (DataXorAddr) begin : gen_data_xor_addr
499 // When DataXorAddr is enabled, on a read, the address is XORed with the data fetched from
500 // the memory in the underlying memory controller (e.g., flash controller). At this point,
501 // the address is again removed. If the address in the read transaction has been modified,
502 // e.g., due to a fault, rdata now contains faulty data, which is detected by the
503 // integrity mechanism.
504 rdata_tlword = {
505 rdata_reshaped[sramreqfifo_rdata.woffset][DataWidth-1:top_pkg::TL_DW],
506 rdata_reshaped[sramreqfifo_rdata.woffset][top_pkg::TL_DW-1:0] ^
507 {{(top_pkg::TL_DW-SramBusBankAW){1'b0}}, sramreqaddrfifo_rdata}
508 };
509 end else begin: gen_no_data_xor_addr
510 rdata_tlword = rdata_reshaped[sramreqfifo_rdata.woffset];
511 end
512 end
513 end
514 end else begin : gen_rmask
515 logic [DataWidth-1:0] rmask;
516 always_comb begin
517 1/1 rmask = '0;
Tests: T1 T2 T3
518 1/1 for (int i = 0 ; i < top_pkg::TL_DW/8 ; i++) begin
Tests: T1 T2 T3
519 1/1 rmask[8*i +: 8] = {8{sramreqfifo_rdata.mask[i]}};
Tests: T1 T2 T3
520 end
521 end
522 // Select correct word and mask it.
523 1/1 assign rdata_tlword = rdata_reshaped[sramreqfifo_rdata.woffset] & rmask;
Tests: T1 T2 T3
524 end
525
526 1/1 assign rspfifo_wdata = '{
Tests: T1 T2 T3
527 data : rdata_tlword[top_pkg::TL_DW-1:0],
528 data_intg : EnableDataIntgPt ? rdata_tlword[DataWidth-1 -: DataIntgWidth] : '0,
529 error : rerror_i[1] // Only care for Uncorrectable error
530 };
531 1/1 assign rspfifo_rready = (reqfifo_rdata.op == OpRead & ~reqfifo_rdata.error)
Tests: T1 T2 T3
532 ? reqfifo_rready : 1'b0 ;
533
534 // This module only cares about uncorrectable errors.
535 logic unused_rerror;
536 0/1 ==> assign unused_rerror = rerror_i[0];
537
538 // FIFO instance: REQ, RSP
539
540 // ReqFIFO is to store the Access type to match to the Response data.
541 // For instance, SRAM accepts the write request but doesn't return the
542 // acknowledge. In this case, it may be hard to determine when the D
543 // response for the write data should send out if reads/writes are
544 // interleaved. So, to make it in-order (even TL-UL allows out-of-order
545 // responses), storing the request is necessary. And if the read entry
546 // is write op, it is safe to return the response right away. If it is
547 // read reqeust, then D response is waiting until read data arrives.
548 prim_fifo_sync #(
549 .Width (ReqFifoWidth),
550 .Pass (1'b0),
551 .Depth (Outstanding),
552 .Secure (SecFifoPtr)
553 ) u_reqfifo (
554 .clk_i,
555 .rst_ni,
556 .clr_i (1'b0),
557 .wvalid_i(reqfifo_wvalid),
558 .wready_o(reqfifo_wready),
559 .wdata_i (reqfifo_wdata),
560 .rvalid_o(reqfifo_rvalid),
561 .rready_i(reqfifo_rready),
562 .rdata_o (reqfifo_rdata),
563 .full_o (),
564 .depth_o (),
565 .err_o (reqfifo_error)
566 );
567
568 // sramreqfifo:
569 // While the ReqFIFO holds the request until it is sent back via TL-UL, the
570 // sramreqfifo only needs to hold the mask and word offset until the read
571 // data returns from memory.
572 prim_fifo_sync #(
573 .Width (SramReqFifoWidth),
574 .Pass (1'b0),
575 .Depth (Outstanding),
576 .Secure (SecFifoPtr)
577 ) u_sramreqfifo (
578 .clk_i,
579 .rst_ni,
580 .clr_i (1'b0),
581 .wvalid_i(sramreqfifo_wvalid),
582 .wready_o(sramreqfifo_wready),
583 .wdata_i (sramreqfifo_wdata),
584 .rvalid_o(),
585 .rready_i(sramreqfifo_rready),
586 .rdata_o (sramreqfifo_rdata),
587 .full_o (),
588 .depth_o (),
589 .err_o (sramreqfifo_error)
590 );
591
592 // sramreqaddrfifo:
593 // This fifo holds the address used for undoing the address XOR data infection.
594 if (DataXorAddr) begin : gen_data_xor_addr_fifo
595 prim_fifo_sync #(
596 .Width (SramBusBankAW),
597 .Pass (1'b0),
598 .Depth (Outstanding),
599 .OutputZeroIfEmpty (1)
600 ) u_sramreqaddrfifo (
601 .clk_i,
602 .rst_ni,
603 .clr_i (1'b0),
604 .wvalid_i(sramreqfifo_wvalid),
605 .wready_o(sramreqaddrfifo_wready),
606 .wdata_i (sramreqaddrfifo_wdata),
607 .rvalid_o(),
608 .rready_i(sramreqfifo_rready),
609 .rdata_o (sramreqaddrfifo_rdata),
610 .full_o (),
611 .depth_o (),
612 .err_o ()
613 );
614 end else begin : gen_no_data_xor_addr_fifo
615 assign sramreqaddrfifo_wready = 1'b1;
616 assign sramreqaddrfifo_rdata = '0;
617
618 // Tie-off unused signals
619 logic unused_sramreqaddrfifo;
620 1/1 assign unused_sramreqaddrfifo = ^{sramreqaddrfifo_wdata, sramreqaddrfifo_rdata};
Tests: T1 T2 T3
Cond Coverage for Module :
tlul_adapter_sram ( parameter SramAw=10,SramDw=32,Outstanding=1,SramBusBankAW=12,ByteAccess=0,ErrOnWrite=0,ErrOnRead=1,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=0,SecFifoPtr=0,EnableReadback=0,DataXorAddr=0,WidthMult=1,DataOutW=32,DataBitWidth=2,WoffsetWidth=1,DataWidth=32 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 121 | 73 | 60.33 |
| Logical | 121 | 73 | 60.33 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 114
EXPRESSION (readback_error | readback_error_q)
-------1------ --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Unreachable | |
LINE 131
EXPRESSION (intg_error || rsp_fifo_error || sramreqfifo_error || reqfifo_error)
-----1---- -------2------ --------3-------- ------4------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 0 | 1 | Unreachable | |
| 0 | 0 | 1 | 0 | Unreachable | |
| 0 | 1 | 0 | 0 | Unreachable | |
| 1 | 0 | 0 | 0 | Unreachable | |
LINE 138
EXPRESSION (intg_error | rsp_fifo_error | sramreqfifo_error | reqfifo_error | intg_error_q)
-----1---- -------2------ --------3-------- ------4------ ------5-----
| -1- | -2- | -3- | -4- | -5- | Status | Tests |
|---|
| 0 | 0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 0 | 0 | 1 | Not Covered | |
| 0 | 0 | 0 | 1 | 0 | Unreachable | |
| 0 | 0 | 1 | 0 | 0 | Unreachable | |
| 0 | 1 | 0 | 0 | 0 | Unreachable | |
| 1 | 0 | 0 | 0 | 0 | Unreachable | |
LINE 144
EXPRESSION
Number Term
1 ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T4,T5 |
LINE 144
SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
---------------1-------------- ----------------2----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T2,T4,T5 |
| 1 | 0 | Covered | T2,T4,T5 |
LINE 144
SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
---------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T4,T5 |
LINE 144
SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T4,T5 |
LINE 144
SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
---------1--------- ----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T2,T4,T5 |
| 0 | 1 | Covered | T4,T8,T10 |
| 1 | 0 | Covered | T4,T5,T8 |
LINE 144
SUB-EXPRESSION (tl_i.a_mask != '1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T4,T5 |
| 1 | Covered | T4,T5,T8 |
LINE 144
SUB-EXPRESSION (tl_i.a_size != 2'h2)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T4,T5 |
| 1 | Covered | T4,T5,T8 |
LINE 162
EXPRESSION (tl_i.a_opcode == Get)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 176
EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
------1------ ------2----- ------3----- -----4----- -----5---- -----6----
| -1- | -2- | -3- | -4- | -5- | -6- | Status | Tests |
|---|
| 0 | 0 | 0 | 0 | 0 | 0 | Covered | T2,T9,T10 |
| 0 | 0 | 0 | 0 | 0 | 1 | Unreachable | |
| 0 | 0 | 0 | 0 | 1 | 0 | Covered | T4,T5,T8 |
| 0 | 0 | 0 | 1 | 0 | 0 | Not Covered | |
| 0 | 0 | 1 | 0 | 0 | 0 | Not Covered | |
| 0 | 1 | 0 | 0 | 0 | 0 | Unreachable | |
| 1 | 0 | 0 | 0 | 0 | 0 | Not Covered | |
LINE 272
EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
--------1------- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T2,T9,T10 |
| 1 | 1 | Covered | T2,T9,T10 |
LINE 273
EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
--------1------- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T10,T11 |
| 1 | 1 | Covered | T2,T9,T10 |
LINE 274
EXPRESSION (req_o & gnt_i)
--1-- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T2,T9,T10 |
LINE 285
EXPRESSION (reqfifo_rdata.op == OpRead)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T9,T10 |
| 1 | Not Covered | |
LINE 302
EXPRESSION (reqfifo_rdata.op == OpRead)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T9,T10 |
| 1 | Not Covered | |
LINE 303
EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
---------1--------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
LINE 313
EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
---1--- -------2------ -------3------ --------------4-------------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Not Covered | |
| 1 | 0 | 1 | 1 | Not Covered | |
| 1 | 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | 1 | Not Covered | |
LINE 313
SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 341
EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
-------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 341
SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
-----1---- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 347
EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
-----------------1-----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 347
SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
-----1---- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 347
SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 359
EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
-------1------ --------2------- ----------3----------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T2,T9,T10 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Not Covered | |
LINE 369
EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
--------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T9,T10 |
LINE 369
SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
---1--- --------------2-------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T2,T9,T10 |
LINE 369
SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 369
EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T9,T10 |
LINE 369
EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T9,T10 |
LINE 369
EXPRESSION (d_valid && d_error)
---1--- ---2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T2,T9,T10 |
| 1 | 1 | Not Covered | |
LINE 369
EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready & sramreqaddrfifo_wready)
-------------1------------ -------2------ ---------3-------- -----------4----------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Not Covered | |
| 1 | 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | 1 | Covered | T2,T9,T10 |
LINE 369
SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
--1-- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T2,T9,T10 |
LINE 390
EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
--------1------- -------2------ ---------3---------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Not Covered | |
| 1 | 0 | 1 | Covered | T2,T9,T10 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T2,T9,T10 |
LINE 392
EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
--------1------- ----------------------------2---------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T8 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T2,T9,T10 |
LINE 393
EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
--------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T9,T10 |
LINE 429
EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Covered | T2,T9,T10 |
LINE 429
SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
---------1-------- --2-
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T2,T9,T10 |
LINE 452
EXPRESSION (((|wmask_intg)) & ((|wdata_intg)))
-------1------- -------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T2,T9,T10 |
| 1 | 1 | Covered | T2,T9,T10 |
LINE 460
EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
-------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T4,T5 |
LINE 460
SUB-EXPRESSION (tl_i_int.a_opcode != Get)
-------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T4,T5 |
LINE 474
EXPRESSION (sram_ack & ((~we_o)))
----1--- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T9,T10 |
| 1 | 1 | Not Covered | |
LINE 477
EXPRESSION (rvalid_i & reqfifo_rvalid)
----1--- -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T9,T10 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 531
EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
----------------------------1----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 531
SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
--------------1------------- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 531
SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
Cond Coverage for Module :
tlul_adapter_sram ( parameter SramAw=10,SramDw=32,Outstanding=1,SramBusBankAW=12,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=0,SecFifoPtr=0,EnableReadback=0,DataXorAddr=0,WidthMult=1,DataOutW=32,DataBitWidth=2,WoffsetWidth=1,DataWidth=32 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 121 | 87 | 71.90 |
| Logical | 121 | 87 | 71.90 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 114
EXPRESSION (readback_error | readback_error_q)
-------1------ --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Unreachable | |
LINE 131
EXPRESSION (intg_error || rsp_fifo_error || sramreqfifo_error || reqfifo_error)
-----1---- -------2------ --------3-------- ------4------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 0 | 1 | Unreachable | |
| 0 | 0 | 1 | 0 | Unreachable | |
| 0 | 1 | 0 | 0 | Unreachable | |
| 1 | 0 | 0 | 0 | Unreachable | |
LINE 138
EXPRESSION (intg_error | rsp_fifo_error | sramreqfifo_error | reqfifo_error | intg_error_q)
-----1---- -------2------ --------3-------- ------4------ ------5-----
| -1- | -2- | -3- | -4- | -5- | Status | Tests |
|---|
| 0 | 0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 0 | 0 | 1 | Not Covered | |
| 0 | 0 | 0 | 1 | 0 | Unreachable | |
| 0 | 0 | 1 | 0 | 0 | Unreachable | |
| 0 | 1 | 0 | 0 | 0 | Unreachable | |
| 1 | 0 | 0 | 0 | 0 | Unreachable | |
LINE 144
EXPRESSION
Number Term
1 ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T4,T5 |
LINE 144
SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
---------------1-------------- ----------------2----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T2,T4,T5 |
| 1 | 0 | Covered | T2,T4,T5 |
LINE 144
SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
---------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T4,T5 |
LINE 144
SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T4,T5 |
LINE 144
SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
---------1--------- ----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T2,T4,T5 |
| 0 | 1 | Covered | T4,T8,T10 |
| 1 | 0 | Covered | T4,T5,T8 |
LINE 144
SUB-EXPRESSION (tl_i.a_mask != '1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T4,T5 |
| 1 | Covered | T4,T5,T8 |
LINE 144
SUB-EXPRESSION (tl_i.a_size != 2'h2)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T4,T5 |
| 1 | Covered | T4,T5,T8 |
LINE 156
EXPRESSION (tl_i.a_opcode != Get)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T4,T5 |
LINE 176
EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
------1------ ------2----- ------3----- -----4----- -----5---- -----6----
| -1- | -2- | -3- | -4- | -5- | -6- | Status | Tests |
|---|
| 0 | 0 | 0 | 0 | 0 | 0 | Covered | T2,T8,T26 |
| 0 | 0 | 0 | 0 | 0 | 1 | Unreachable | |
| 0 | 0 | 0 | 0 | 1 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 0 | 1 | 0 | 0 | Not Covered | |
| 0 | 0 | 1 | 0 | 0 | 0 | Unreachable | |
| 0 | 1 | 0 | 0 | 0 | 0 | Not Covered | |
| 1 | 0 | 0 | 0 | 0 | 0 | Not Covered | |
LINE 272
EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
--------1------- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T2,T8,T26 |
| 1 | 1 | Covered | T2,T8,T26 |
LINE 273
EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
--------1------- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T8,T15 |
| 1 | 1 | Covered | T2,T8,T26 |
LINE 274
EXPRESSION (req_o & gnt_i)
--1-- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T2,T8,T26 |
LINE 285
EXPRESSION (reqfifo_rdata.op == OpRead)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Covered | T2,T8,T26 |
LINE 302
EXPRESSION (reqfifo_rdata.op == OpRead)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Covered | T2,T8,T26 |
LINE 303
EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
---------1--------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T8,T15,T27 |
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T2,T26,T44 |
LINE 313
EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
---1--- -------2------ -------3------ --------------4-------------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Not Covered | |
| 1 | 0 | 1 | 1 | Not Covered | |
| 1 | 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | 1 | Covered | T2,T8,T26 |
LINE 313
SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T8,T26 |
LINE 341
EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
-------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T8,T15,T27 |
LINE 341
SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
-----1---- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T26,T44 |
| 1 | 1 | Covered | T8,T15,T27 |
LINE 347
EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
-----------------1-----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 347
SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
-----1---- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T2,T8,T26 |
| 1 | 1 | Not Covered | |
LINE 347
SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T8,T26 |
LINE 359
EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
-------1------ --------2------- ----------3----------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T2,T8,T26 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Not Covered | |
LINE 369
EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
--------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 369
SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
---1--- --------------2-------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T8,T26 |
| 1 | 1 | Not Covered | |
LINE 369
SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 369
EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T8,T26 |
LINE 369
EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T8,T26 |
LINE 369
EXPRESSION (d_valid && d_error)
---1--- ---2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T8,T15,T27 |
| 1 | 1 | Covered | T2,T26,T44 |
LINE 369
EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready & sramreqaddrfifo_wready)
-------------1------------ -------2------ ---------3-------- -----------4----------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Not Covered | |
| 1 | 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | 1 | Covered | T2,T8,T26 |
LINE 369
SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
--1-- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T2,T8,T26 |
LINE 390
EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
--------1------- -------2------ ---------3---------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Not Covered | |
| 1 | 0 | 1 | Covered | T2,T8,T26 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T2,T8,T26 |
LINE 392
EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
--------1------- ----------------------------2---------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T4,T5 |
| 1 | 0 | Covered | T2,T8,T26 |
| 1 | 1 | Not Covered | |
LINE 393
EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
--------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T8,T26 |
LINE 429
EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T8,T26 |
| 1 | Not Covered | |
LINE 429
SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
---------1-------- --2-
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T2,T8,T26 |
| 1 | 1 | Not Covered | |
LINE 452
EXPRESSION (((|wmask_intg)) & ((|wdata_intg)))
-------1------- -------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T28,T30,T45 |
| 1 | 1 | Covered | T2,T8,T26 |
LINE 460
EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
-------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T4,T5 |
LINE 460
SUB-EXPRESSION (tl_i_int.a_opcode != Get)
-------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T4,T5 |
LINE 474
EXPRESSION (sram_ack & ((~we_o)))
----1--- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T2,T8,T26 |
LINE 477
EXPRESSION (rvalid_i & reqfifo_rvalid)
----1--- -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T44,T27,T29 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T2,T8,T26 |
LINE 531
EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
----------------------------1----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T8,T26 |
LINE 531
SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
--------------1------------- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T2,T8,T26 |
LINE 531
SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T8,T26 |
Branch Coverage for Module :
tlul_adapter_sram
| Line No. | Total | Covered | Percent |
| Branches |
|
26 |
24 |
92.31 |
| TERNARY |
144 |
2 |
2 |
100.00 |
| TERNARY |
341 |
2 |
2 |
100.00 |
| TERNARY |
347 |
3 |
2 |
66.67 |
| TERNARY |
393 |
2 |
2 |
100.00 |
| TERNARY |
531 |
2 |
2 |
100.00 |
| IF |
129 |
2 |
2 |
100.00 |
| IF |
281 |
4 |
3 |
75.00 |
| IF |
301 |
3 |
3 |
100.00 |
| IF |
362 |
2 |
2 |
100.00 |
| IF |
426 |
2 |
2 |
100.00 |
| IF |
438 |
2 |
2 |
100.00 |
144 assign wr_attr_error = (tl_i.a_opcode == PutFullData || tl_i.a_opcode == PutPartialData)
145 ? ((ByteAccess == 0) ?
146 (tl_i.a_mask != '1 || tl_i.a_size != 2'h2) : 1'b0)
147 : 1'b0;
ID LINE
-1- 144 ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T4,T5 |
| 0 |
Covered |
T1,T2,T3 |
341 assign d_data = (vld_rd_rsp & ~d_error) ? rspfifo_rdata.data // valid read
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T8,T15,T27 |
| 0 |
Covered |
T1,T2,T3 |
347 assign data_intg = (vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : // TL-UL error
-1-
==>
348 (vld_rd_rsp) ? rspfifo_rdata.data_intg : // valid read
-2-
==>
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Not Covered |
|
| 0 |
1 |
Covered |
T2,T8,T26 |
| 0 |
0 |
Covered |
T1,T2,T3 |
393 assign addr_o = (tl_i_int.a_valid) ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T8,T9 |
| 0 |
Covered |
T1,T2,T3 |
531 assign rspfifo_rready = (reqfifo_rdata.op == OpRead & ~reqfifo_rdata.error)
532 ? reqfifo_rready : 1'b0 ;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T8,T26 |
| 0 |
Covered |
T1,T2,T3 |
129 if (!rst_ni) begin
-1-
130 intg_error_q <= '0;
==>
131 end else if (intg_error || rsp_fifo_error || sramreqfifo_error || reqfifo_error) begin
-2-
132 intg_error_q <= 1'b1;
==> (Unreachable)
133 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Unreachable |
|
| 0 |
0 |
Covered |
T1,T2,T3 |
281 if (reqfifo_rvalid) begin
-1-
282 if (reqfifo_rdata.error) begin
-2-
283 // Return error response. Assume no request went out to SRAM
284 d_valid = 1'b1;
==>
285 end else if (reqfifo_rdata.op == OpRead) begin
-3-
286 d_valid = rspfifo_rvalid;
==>
287 end else begin
288 // Write without error
289 d_valid = 1'b1;
==>
290 end
291 end else begin
292 d_valid = 1'b0;
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
1 |
- |
Not Covered |
|
| 1 |
0 |
1 |
Covered |
T2,T8,T26 |
| 1 |
0 |
0 |
Covered |
T2,T9,T10 |
| 0 |
- |
- |
Covered |
T1,T2,T3 |
301 if (reqfifo_rvalid) begin
-1-
302 if (reqfifo_rdata.op == OpRead) begin
-2-
303 d_error = rspfifo_rdata.error | reqfifo_rdata.error;
==>
304 end else begin
305 d_error = reqfifo_rdata.error;
==>
306 end
307 end else begin
308 d_error = 1'b0;
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
1 |
Covered |
T2,T8,T26 |
| 1 |
0 |
Covered |
T2,T9,T10 |
| 0 |
- |
Covered |
T1,T2,T3 |
362 if (!rst_ni) begin
-1-
363 missed_err_gnt_q <= 1'b0;
==>
364 end else begin
365 missed_err_gnt_q <= missed_err_gnt_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
426 if (tl_i_int.a_valid) begin
-1-
427 for (int i = 0 ; i < top_pkg::TL_DW/8 ; i++) begin
==>
428 wmask_int[woffset][8*i +: 8] = {8{tl_i_int.a_mask[i]}};
429 wdata_int[woffset][8*i +: 8] = (tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[8*i+:8] : '0;
430 end
431 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T8,T9 |
| 0 |
Covered |
T1,T2,T3 |
438 if (tl_i_int.a_valid) begin
-1-
439 wmask_intg[woffset] = {DataIntgWidth{1'b1}};
==>
440 wdata_intg[woffset] = tl_i_int.a_user.data_intg;
441 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T8,T9 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
tlul_adapter_sram
Assertion Details
AddrOutKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
918843738 |
918664206 |
0 |
0 |
| T1 |
1904 |
1772 |
0 |
0 |
| T2 |
4836 |
4714 |
0 |
0 |
| T3 |
3436 |
3270 |
0 |
0 |
| T4 |
134464 |
134332 |
0 |
0 |
| T5 |
4396 |
4214 |
0 |
0 |
| T6 |
11196 |
8206 |
0 |
0 |
| T7 |
3846 |
3652 |
0 |
0 |
| T8 |
8574 |
8434 |
0 |
0 |
| T9 |
19470 |
19310 |
0 |
0 |
| T10 |
19336 |
19210 |
0 |
0 |
DataIntgOptions_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1952 |
1952 |
0 |
0 |
| T1 |
2 |
2 |
0 |
0 |
| T2 |
2 |
2 |
0 |
0 |
| T3 |
2 |
2 |
0 |
0 |
| T4 |
2 |
2 |
0 |
0 |
| T5 |
2 |
2 |
0 |
0 |
| T6 |
2 |
2 |
0 |
0 |
| T7 |
2 |
2 |
0 |
0 |
| T8 |
2 |
2 |
0 |
0 |
| T9 |
2 |
2 |
0 |
0 |
| T10 |
2 |
2 |
0 |
0 |
ReqOutKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
918843738 |
918664206 |
0 |
0 |
| T1 |
1904 |
1772 |
0 |
0 |
| T2 |
4836 |
4714 |
0 |
0 |
| T3 |
3436 |
3270 |
0 |
0 |
| T4 |
134464 |
134332 |
0 |
0 |
| T5 |
4396 |
4214 |
0 |
0 |
| T6 |
11196 |
8206 |
0 |
0 |
| T7 |
3846 |
3652 |
0 |
0 |
| T8 |
8574 |
8434 |
0 |
0 |
| T9 |
19470 |
19310 |
0 |
0 |
| T10 |
19336 |
19210 |
0 |
0 |
SramDwHasByteGranularity_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1952 |
1952 |
0 |
0 |
| T1 |
2 |
2 |
0 |
0 |
| T2 |
2 |
2 |
0 |
0 |
| T3 |
2 |
2 |
0 |
0 |
| T4 |
2 |
2 |
0 |
0 |
| T5 |
2 |
2 |
0 |
0 |
| T6 |
2 |
2 |
0 |
0 |
| T7 |
2 |
2 |
0 |
0 |
| T8 |
2 |
2 |
0 |
0 |
| T9 |
2 |
2 |
0 |
0 |
| T10 |
2 |
2 |
0 |
0 |
SramDwIsMultipleOfTlulWidth_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1952 |
1952 |
0 |
0 |
| T1 |
2 |
2 |
0 |
0 |
| T2 |
2 |
2 |
0 |
0 |
| T3 |
2 |
2 |
0 |
0 |
| T4 |
2 |
2 |
0 |
0 |
| T5 |
2 |
2 |
0 |
0 |
| T6 |
2 |
2 |
0 |
0 |
| T7 |
2 |
2 |
0 |
0 |
| T8 |
2 |
2 |
0 |
0 |
| T9 |
2 |
2 |
0 |
0 |
| T10 |
2 |
2 |
0 |
0 |
TlOutKnownIfFifoKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
918843738 |
918664206 |
0 |
0 |
| T1 |
1904 |
1772 |
0 |
0 |
| T2 |
4836 |
4714 |
0 |
0 |
| T3 |
3436 |
3270 |
0 |
0 |
| T4 |
134464 |
134332 |
0 |
0 |
| T5 |
4396 |
4214 |
0 |
0 |
| T6 |
11196 |
8206 |
0 |
0 |
| T7 |
3846 |
3652 |
0 |
0 |
| T8 |
8574 |
8434 |
0 |
0 |
| T9 |
19470 |
19310 |
0 |
0 |
| T10 |
19336 |
19210 |
0 |
0 |
TlOutValidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
918843738 |
918664206 |
0 |
0 |
| T1 |
1904 |
1772 |
0 |
0 |
| T2 |
4836 |
4714 |
0 |
0 |
| T3 |
3436 |
3270 |
0 |
0 |
| T4 |
134464 |
134332 |
0 |
0 |
| T5 |
4396 |
4214 |
0 |
0 |
| T6 |
11196 |
8206 |
0 |
0 |
| T7 |
3846 |
3652 |
0 |
0 |
| T8 |
8574 |
8434 |
0 |
0 |
| T9 |
19470 |
19310 |
0 |
0 |
| T10 |
19336 |
19210 |
0 |
0 |
WdataOutKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
918843738 |
918664206 |
0 |
0 |
| T1 |
1904 |
1772 |
0 |
0 |
| T2 |
4836 |
4714 |
0 |
0 |
| T3 |
3436 |
3270 |
0 |
0 |
| T4 |
134464 |
134332 |
0 |
0 |
| T5 |
4396 |
4214 |
0 |
0 |
| T6 |
11196 |
8206 |
0 |
0 |
| T7 |
3846 |
3652 |
0 |
0 |
| T8 |
8574 |
8434 |
0 |
0 |
| T9 |
19470 |
19310 |
0 |
0 |
| T10 |
19336 |
19210 |
0 |
0 |
WeOutKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
918843738 |
918664206 |
0 |
0 |
| T1 |
1904 |
1772 |
0 |
0 |
| T2 |
4836 |
4714 |
0 |
0 |
| T3 |
3436 |
3270 |
0 |
0 |
| T4 |
134464 |
134332 |
0 |
0 |
| T5 |
4396 |
4214 |
0 |
0 |
| T6 |
11196 |
8206 |
0 |
0 |
| T7 |
3846 |
3652 |
0 |
0 |
| T8 |
8574 |
8434 |
0 |
0 |
| T9 |
19470 |
19310 |
0 |
0 |
| T10 |
19336 |
19210 |
0 |
0 |
WmaskOutKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
918843738 |
918664206 |
0 |
0 |
| T1 |
1904 |
1772 |
0 |
0 |
| T2 |
4836 |
4714 |
0 |
0 |
| T3 |
3436 |
3270 |
0 |
0 |
| T4 |
134464 |
134332 |
0 |
0 |
| T5 |
4396 |
4214 |
0 |
0 |
| T6 |
11196 |
8206 |
0 |
0 |
| T7 |
3846 |
3652 |
0 |
0 |
| T8 |
8574 |
8434 |
0 |
0 |
| T9 |
19470 |
19310 |
0 |
0 |
| T10 |
19336 |
19210 |
0 |
0 |
adapterNoReadOrWrite
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1952 |
1952 |
0 |
0 |
| T1 |
2 |
2 |
0 |
0 |
| T2 |
2 |
2 |
0 |
0 |
| T3 |
2 |
2 |
0 |
0 |
| T4 |
2 |
2 |
0 |
0 |
| T5 |
2 |
2 |
0 |
0 |
| T6 |
2 |
2 |
0 |
0 |
| T7 |
2 |
2 |
0 |
0 |
| T8 |
2 |
2 |
0 |
0 |
| T9 |
2 |
2 |
0 |
0 |
| T10 |
2 |
2 |
0 |
0 |
rvalidHighReqFifoEmpty
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
918843738 |
178300 |
0 |
0 |
| T2 |
2418 |
100 |
0 |
0 |
| T3 |
1718 |
0 |
0 |
0 |
| T4 |
67232 |
0 |
0 |
0 |
| T5 |
2198 |
0 |
0 |
0 |
| T6 |
5598 |
0 |
0 |
0 |
| T7 |
1923 |
0 |
0 |
0 |
| T8 |
4287 |
52 |
0 |
0 |
| T9 |
9735 |
0 |
0 |
0 |
| T10 |
9668 |
0 |
0 |
0 |
| T11 |
42259 |
0 |
0 |
0 |
| T15 |
0 |
20 |
0 |
0 |
| T26 |
0 |
100 |
0 |
0 |
| T27 |
0 |
34 |
0 |
0 |
| T28 |
0 |
231 |
0 |
0 |
| T29 |
0 |
17 |
0 |
0 |
| T30 |
0 |
740 |
0 |
0 |
| T44 |
0 |
100 |
0 |
0 |
| T46 |
0 |
100 |
0 |
0 |
rvalidHighWhenRspFifoFull
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
918843738 |
178300 |
0 |
0 |
| T2 |
2418 |
100 |
0 |
0 |
| T3 |
1718 |
0 |
0 |
0 |
| T4 |
67232 |
0 |
0 |
0 |
| T5 |
2198 |
0 |
0 |
0 |
| T6 |
5598 |
0 |
0 |
0 |
| T7 |
1923 |
0 |
0 |
0 |
| T8 |
4287 |
52 |
0 |
0 |
| T9 |
9735 |
0 |
0 |
0 |
| T10 |
9668 |
0 |
0 |
0 |
| T11 |
42259 |
0 |
0 |
0 |
| T15 |
0 |
20 |
0 |
0 |
| T26 |
0 |
100 |
0 |
0 |
| T27 |
0 |
34 |
0 |
0 |
| T28 |
0 |
231 |
0 |
0 |
| T29 |
0 |
17 |
0 |
0 |
| T30 |
0 |
740 |
0 |
0 |
| T44 |
0 |
100 |
0 |
0 |
| T46 |
0 |
100 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_tlul2sram_egress
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 72 | 69 | 95.83 |
| CONT_ASSIGN | 107 | 0 | 0 | |
| CONT_ASSIGN | 114 | 0 | 0 | |
| ALWAYS | 129 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 176 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 272 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 273 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 274 | 1 | 1 | 100.00 |
| ALWAYS | 279 | 7 | 6 | 85.71 |
| ALWAYS | 299 | 6 | 5 | 83.33 |
| CONT_ASSIGN | 313 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 317 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 336 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 341 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 347 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 359 | 1 | 1 | 100.00 |
| ALWAYS | 362 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 369 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 390 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 391 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 392 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 393 | 1 | 1 | 100.00 |
| ALWAYS | 423 | 6 | 6 | 100.00 |
| ALWAYS | 435 | 5 | 5 | 100.00 |
| CONT_ASSIGN | 450 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 451 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 452 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 456 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 457 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 459 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 460 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 467 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 470 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 474 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 475 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 477 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 479 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 486 | 1 | 1 | 100.00 |
| ALWAYS | 517 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 523 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 526 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 531 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 536 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 620 | 1 | 1 | 100.00 |
106 logic unused_sram_byte_readback_error;
107 unreachable assign unused_sram_byte_readback_error = sram_byte_readback_error;
108 assign readback_error = '0;
109 assign readback_error_q = '0;
110 end
111
112 // readback error output is permanent and should be used for alert generation
113 // or other downstream effects
114 unreachable assign readback_error_o = readback_error | readback_error_q;
115
116 // integrity check
117 if (CmdIntgCheck) begin : gen_cmd_intg_check
118 tlul_cmd_intg_chk u_cmd_intg_chk (
119 .tl_i(tl_i),
120 .err_o (intg_error)
121 );
122 end else begin : gen_no_cmd_intg_check
123 assign intg_error = '0;
124 end
125
126 // permanently latch integrity error until reset
127 logic intg_error_q;
128 always_ff @(posedge clk_i or negedge rst_ni) begin
129 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
130 1/1 intg_error_q <= '0;
Tests: T1 T2 T3
131 1/1 end else if (intg_error || rsp_fifo_error || sramreqfifo_error || reqfifo_error) begin
Tests: T1 T2 T3
132 unreachable intg_error_q <= 1'b1;
133 end
MISSING_ELSE
134 end
135
136 // integrity error output is permanent and should be used for alert generation
137 // or other downstream effects
138 1/1 assign intg_error_o = intg_error | rsp_fifo_error | sramreqfifo_error |
Tests: T1 T2 T3
139 reqfifo_error | intg_error_q;
140
141 // wr_attr_error: Check if the request size, mask are permitted.
142 // Basic check of size, mask, addr align is done in tlul_err module.
143 // Here it checks any partial write if ByteAccess isn't allowed.
144 1/1 assign wr_attr_error = (tl_i.a_opcode == PutFullData || tl_i.a_opcode == PutPartialData)
Tests: T1 T2 T3
145 ? ((ByteAccess == 0) ?
146 (tl_i.a_mask != '1 || tl_i.a_size != 2'h2) : 1'b0)
147 : 1'b0;
148
149 // An instruction type transaction is only valid if en_ifetch is enabled
150 // If the instruction type is completely invalid, also considered an instruction error
151 1/1 assign instr_error = prim_mubi_pkg::mubi4_test_invalid(tl_i.a_user.instr_type) |
Tests: T1 T2 T3
152 (prim_mubi_pkg::mubi4_test_true_strict(tl_i.a_user.instr_type) &
153 prim_mubi_pkg::mubi4_test_false_loose(en_ifetch_i));
154
155 if (ErrOnWrite == 1) begin : gen_no_writes
156 assign wr_vld_error = tl_i.a_opcode != Get;
157 end else begin : gen_writes_allowed
158 assign wr_vld_error = 1'b0;
159 end
160
161 if (ErrOnRead == 1) begin: gen_no_reads
162 1/1 assign rd_vld_error = tl_i.a_opcode == Get;
Tests: T1 T2 T3
163 end else begin : gen_reads_allowed
164 assign rd_vld_error = 1'b0;
165 end
166
167 // tlul protocol check
168 tlul_err u_err (
169 .clk_i,
170 .rst_ni,
171 .tl_i(tl_i),
172 .err_o (tlul_error)
173 );
174
175 // error return is transactional and thus does not used the "latched" intg_err signal
176 1/1 assign error_det = wr_attr_error | wr_vld_error | rd_vld_error | instr_error |
Tests: T1 T2 T3
177 tlul_error | intg_error;
178
179 // from sram_byte to adapter logic
180 tl_h2d_t tl_i_int;
181 // from adapter logic to sram_byte
182 tl_d2h_t tl_o_int;
183 // from sram_byte to rsp_gen
184 tl_d2h_t tl_out;
185
186 // not all parts of tl_i_int are used
187 logic unused_tl_i_int;
188 1/1 assign unused_tl_i_int = ^tl_i_int;
Tests: T1 T2 T3
189
190 tlul_rsp_intg_gen #(
191 .EnableRspIntgGen(EnableRspIntgGen),
192 .EnableDataIntgGen(EnableDataIntgGen)
193 ) u_rsp_gen (
194 .tl_i(tl_out),
195 .tl_o
196 );
197
198 // byte handling for integrity
199 tlul_sram_byte #(
200 .EnableIntg(ByteAccess & EnableDataIntgPt & !ErrOnWrite),
201 .Outstanding(Outstanding),
202 .EnableReadback(EnableReadback)
203 ) u_sram_byte (
204 .clk_i,
205 .rst_ni,
206 .tl_i,
207 .tl_o(tl_out),
208 .tl_sram_o(tl_i_int),
209 .tl_sram_i(tl_o_int),
210 .error_i(error_det),
211 .error_o(error_internal),
212 .alert_o(sram_byte_readback_error),
213 .compound_txn_in_progress_o,
214 .readback_en_i,
215 .wr_collision_i,
216 .write_pending_i
217 );
218
219 typedef struct packed {
220 logic [top_pkg::TL_DBW-1:0] mask ; // Byte mask within the TL-UL word
221 logic [WoffsetWidth-1:0] woffset ; // Offset of the TL-UL word within the SRAM word
222 } sram_req_t ;
223
224 typedef struct packed {
225 logic [SramBusBankAW-1:0] addr; // Address of the request going to the memory.
226 } sram_req_addr_t ;
227
228 typedef enum logic [1:0] {
229 OpWrite,
230 OpRead,
231 OpUnknown
232 } req_op_e ;
233
234 typedef struct packed {
235 req_op_e op ;
236 logic error ;
237 prim_mubi_pkg::mubi4_t instr_type;
238 logic [top_pkg::TL_SZW-1:0] size ;
239 logic [top_pkg::TL_AIW-1:0] source ;
240 } req_t ;
241
242 typedef struct packed {
243 logic [top_pkg::TL_DW-1:0] data ;
244 logic [DataIntgWidth-1:0] data_intg ;
245 logic error ;
246 } rsp_t ;
247
248 localparam int SramReqFifoWidth = $bits(sram_req_t) ;
249 localparam int ReqFifoWidth = $bits(req_t) ;
250 localparam int RspFifoWidth = $bits(rsp_t) ;
251
252 // FIFO signal in case OutStand is greater than 1
253 // If request is latched, {write, source} is pushed to req fifo.
254 // Req fifo is popped when D channel is acknowledged (v & r)
255 // D channel valid is asserted if it is write request or rsp fifo not empty if read.
256 logic reqfifo_wvalid, reqfifo_wready;
257 logic reqfifo_rvalid, reqfifo_rready;
258 req_t reqfifo_wdata, reqfifo_rdata;
259
260 logic sramreqfifo_wvalid, sramreqfifo_wready;
261 logic sramreqfifo_rready;
262 sram_req_t sramreqfifo_wdata, sramreqfifo_rdata;
263
264 logic sramreqaddrfifo_wready;
265 logic [SramBusBankAW-1:0] sramreqaddrfifo_wdata, sramreqaddrfifo_rdata;
266
267 logic rspfifo_wvalid, rspfifo_wready;
268 logic rspfifo_rvalid, rspfifo_rready;
269 rsp_t rspfifo_wdata, rspfifo_rdata;
270
271 logic a_ack, d_ack, sram_ack;
272 1/1 assign a_ack = tl_i_int.a_valid & tl_o_int.a_ready ;
Tests: T1 T2 T3
273 1/1 assign d_ack = tl_o_int.d_valid & tl_i_int.d_ready ;
Tests: T1 T2 T3
274 1/1 assign sram_ack = req_o & gnt_i ;
Tests: T1 T2 T3
275
276 // Valid handling
277 logic d_valid, d_error;
278 always_comb begin
279 1/1 d_valid = 1'b0;
Tests: T1 T2 T3
280
281 1/1 if (reqfifo_rvalid) begin
Tests: T1 T2 T3
282 1/1 if (reqfifo_rdata.error) begin
Tests: T2 T9 T10
283 // Return error response. Assume no request went out to SRAM
284 0/1 ==> d_valid = 1'b1;
285 1/1 end else if (reqfifo_rdata.op == OpRead) begin
Tests: T2 T9 T10
286 excluded d_valid = rspfifo_rvalid;
Exclude Annotation: VC_COV_UNR
287 end else begin
288 // Write without error
289 1/1 d_valid = 1'b1;
Tests: T2 T9 T10
290 end
291 end else begin
292 1/1 d_valid = 1'b0;
Tests: T1 T2 T3
293 end
294 end
295
296
297
298 always_comb begin
299 1/1 d_error = 1'b0;
Tests: T1 T2 T3
300
301 1/1 if (reqfifo_rvalid) begin
Tests: T1 T2 T3
302 1/1 if (reqfifo_rdata.op == OpRead) begin
Tests: T2 T9 T10
303 0/1 ==> d_error = rspfifo_rdata.error | reqfifo_rdata.error;
304 end else begin
305 1/1 d_error = reqfifo_rdata.error;
Tests: T2 T9 T10
306 end
307 end else begin
308 1/1 d_error = 1'b0;
Tests: T1 T2 T3
309 end
310 end
311
312 logic vld_rd_rsp;
313 1/1 assign vld_rd_rsp = d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead);
Tests: T1 T2 T3
314 // If the response data is not valid, we set it to an illegal blanking value which is determined
315 // by whether the current transaction is an instruction fetch or a regular read operation.
316 logic [top_pkg::TL_DW-1:0] error_blanking_data;
317 1/1 assign error_blanking_data = (prim_mubi_pkg::mubi4_test_true_strict(reqfifo_rdata.instr_type)) ?
Tests: T1 T2 T3
318 DataWhenInstrError :
319 DataWhenError;
320
321 // Since DataWhenInstrError and DataWhenError can be arbitrary parameters
322 // we statically calculate the correct integrity values for these parameters here so that
323 // they do not have to be supplied externally.
324 logic [top_pkg::TL_DW-1:0] unused_instr, unused_data;
325 logic [DataIntgWidth-1:0] error_instr_integ, error_data_integ;
326 tlul_data_integ_enc u_tlul_data_integ_enc_instr (
327 .data_i(DataMaxWidth'(DataWhenInstrError)),
328 .data_intg_o({error_instr_integ, unused_instr})
329 );
330 tlul_data_integ_enc u_tlul_data_integ_enc_data (
331 .data_i(DataMaxWidth'(DataWhenError)),
332 .data_intg_o({error_data_integ, unused_data})
333 );
334
335 logic [DataIntgWidth-1:0] error_blanking_integ;
336 1/1 assign error_blanking_integ = (prim_mubi_pkg::mubi4_test_true_strict(reqfifo_rdata.instr_type)) ?
Tests: T1 T2 T3
337 error_instr_integ :
338 error_data_integ;
339
340 logic [top_pkg::TL_DW-1:0] d_data;
341 1/1 assign d_data = (vld_rd_rsp & ~d_error) ? rspfifo_rdata.data // valid read
Tests: T1 T2 T3
342 : error_blanking_data; // write or TL-UL error
343
344 // If this a write response with data fields set to 0, we have to set all ECC bits correctly
345 // since we are using an inverted Hsiao code.
346 logic [DataIntgWidth-1:0] data_intg;
347 1/1 assign data_intg = (vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : // TL-UL error
Tests: T1 T2 T3
348 (vld_rd_rsp) ? rspfifo_rdata.data_intg : // valid read
349 prim_secded_pkg::SecdedInv3932ZeroEcc; // valid write
350
351 // When an error is seen on an incoming transaction it gets an immediate response without
352 // performing an SRAM request. It may be the transaction receives a ready the first cycle it is
353 // seen, but if not we force a ready the following cycle. This avoids factoring the error
354 // calculation into the outgoing ready preventing a feedthrough path from the incoming tilelink
355 // signals to the outgoing tilelink signals.
356 logic missed_err_gnt_d, missed_err_gnt_q;
357
358 // Track whether we've seen an incoming transaction with an error that didn't get a ready
359 1/1 assign missed_err_gnt_d = error_internal & tl_i_int.a_valid & ~tl_o_int.a_ready;
Tests: T1 T2 T3
360
361 always_ff @(posedge clk_i or negedge rst_ni) begin
362 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
363 1/1 missed_err_gnt_q <= 1'b0;
Tests: T1 T2 T3
364 end else begin
365 1/1 missed_err_gnt_q <= missed_err_gnt_d;
Tests: T1 T2 T3
366 end
367 end
368
369 1/1 assign tl_o_int = '{
Tests: T1 T2 T3
370 d_valid : d_valid ,
371 d_opcode : (d_valid && reqfifo_rdata.op != OpRead) ? AccessAck : AccessAckData,
372 d_param : '0,
373 d_size : (d_valid) ? reqfifo_rdata.size : '0,
374 d_source : (d_valid) ? reqfifo_rdata.source : '0,
375 d_sink : 1'b0,
376 d_data : d_data,
377 d_user : '{default: '0, data_intg: data_intg},
378 d_error : d_valid && d_error,
379 a_ready : (gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready &
380 sramreqaddrfifo_wready
381 };
382
383 // a_ready depends on the FIFO full condition and grant from SRAM (or SRAM arbiter)
384 // assemble response, including read response, write response, and error for unsupported stuff
385
386 // Output to SRAM:
387 // Generate request only when no internal error occurs. If error occurs, the request should be
388 // dropped and returned error response to the host. So, error to be pushed to reqfifo.
389 // In this case, it is assumed the request is granted (may cause ordering issue later?)
390 1/1 assign req_o = tl_i_int.a_valid & reqfifo_wready & ~error_internal;
Tests: T1 T2 T3
391 1/1 assign req_type_o = tl_i_int.a_user.instr_type;
Tests: T1 T2 T3
392 1/1 assign we_o = tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData});
Tests: T1 T2 T3
393 1/1 assign addr_o = (tl_i_int.a_valid) ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0;
Tests: T1 T2 T3
394
395 // Support SRAMs wider than the TL-UL word width by mapping the parts of the
396 // TL-UL address which are more fine-granular than the SRAM width to the
397 // SRAM write mask.
398 logic [WoffsetWidth-1:0] woffset;
399 if (top_pkg::TL_DW != SramDw) begin : gen_wordwidthadapt
400 assign woffset = tl_i_int.a_address[DataBitWidth-1:prim_util_pkg::vbits(top_pkg::TL_DBW)];
401 end else begin : gen_no_wordwidthadapt
402 assign woffset = '0;
403 end
404
405 // The size of the data/wmask depends on whether passthrough integrity is enabled.
406 // If passthrough integrity is enabled, the data is concatenated with the integrity passed through
407 // the user bits. Otherwise, it is the data only.
408 localparam int DataWidth = EnableDataIntgPt ? top_pkg::TL_DW + DataIntgWidth : top_pkg::TL_DW;
409
410 // Final combined wmask / wdata
411 logic [WidthMult-1:0][DataWidth-1:0] wmask_combined;
412 logic [WidthMult-1:0][DataWidth-1:0] wdata_combined;
413
414 // Original tlul portion
415 logic [WidthMult-1:0][top_pkg::TL_DW-1:0] wmask_int;
416 logic [WidthMult-1:0][top_pkg::TL_DW-1:0] wdata_int;
417
418 // Integrity portion
419 logic [WidthMult-1:0][DataIntgWidth-1:0] wmask_intg;
420 logic [WidthMult-1:0][DataIntgWidth-1:0] wdata_intg;
421
422 always_comb begin
423 1/1 wmask_int = '0;
Tests: T1 T2 T3
424 1/1 wdata_int = '0;
Tests: T1 T2 T3
425
426 1/1 if (tl_i_int.a_valid) begin
Tests: T1 T2 T3
427 1/1 for (int i = 0 ; i < top_pkg::TL_DW/8 ; i++) begin
Tests: T2 T9 T10
428 1/1 wmask_int[woffset][8*i +: 8] = {8{tl_i_int.a_mask[i]}};
Tests: T2 T9 T10
429 1/1 wdata_int[woffset][8*i +: 8] = (tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[8*i+:8] : '0;
Tests: T2 T9 T10
430 end
431 end
MISSING_ELSE
432 end
433
434 always_comb begin
435 1/1 wmask_intg = '0;
Tests: T1 T2 T3
436 1/1 wdata_intg = '0;
Tests: T1 T2 T3
437
438 1/1 if (tl_i_int.a_valid) begin
Tests: T1 T2 T3
439 1/1 wmask_intg[woffset] = {DataIntgWidth{1'b1}};
Tests: T2 T9 T10
440 1/1 wdata_intg[woffset] = tl_i_int.a_user.data_intg;
Tests: T2 T9 T10
441 end
MISSING_ELSE
442 end
443
444 for (genvar i = 0; i < WidthMult; i++) begin : gen_write_output
445 if (EnableDataIntgPt) begin : gen_combined_output
446 assign wmask_combined[i] = {wmask_intg[i], wmask_int[i]};
447 assign wdata_combined[i] = {wdata_intg[i], wdata_int[i]};
448 end else begin : gen_ft_output
449 logic unused_w;
450 1/1 assign wmask_combined[i] = wmask_int[i];
Tests: T1 T2 T3
451 1/1 assign wdata_combined[i] = wdata_int[i];
Tests: T1 T2 T3
452 1/1 assign unused_w = |wmask_intg & |wdata_intg;
Tests: T1 T2 T3
453 end
454 end
455
456 1/1 assign wmask_o = wmask_combined;
Tests: T1 T2 T3
457 1/1 assign wdata_o = wdata_combined;
Tests: T1 T2 T3
458
459 1/1 assign reqfifo_wvalid = a_ack ; // Push to FIFO only when granted
Tests: T2 T9 T10
460 1/1 assign reqfifo_wdata = '{
Tests: T1 T2 T3
461 op: (tl_i_int.a_opcode != Get) ? OpWrite : OpRead, // To return AccessAck for opcode error
462 error: error_internal,
463 instr_type: tl_i_int.a_user.instr_type,
464 size: tl_i_int.a_size,
465 source: tl_i_int.a_source
466 }; // Store the request only. Doesn't have to store data
467 1/1 assign reqfifo_rready = d_ack ;
Tests: T2 T9 T10
468
469 // push together with ReqFIFO, pop upon returning read
470 1/1 assign sramreqfifo_wdata = '{
Tests: T1 T2 T3
471 mask : tl_i_int.a_mask,
472 woffset : woffset
473 };
474 1/1 assign sramreqfifo_wvalid = sram_ack & ~we_o;
Tests: T1 T2 T3
475 1/1 assign sramreqfifo_rready = rspfifo_wvalid;
Tests: T1 T2 T3
476
477 1/1 assign rspfifo_wvalid = rvalid_i & reqfifo_rvalid;
Tests: T1 T2 T3
478
479 1/1 assign sramreqaddrfifo_wdata = tl_i_int.a_address[DataBitWidth+:SramBusBankAW];
Tests: T1 T2 T3
480
481 // Make sure only requested bytes are forwarded
482 logic [WidthMult-1:0][DataWidth-1:0] rdata_reshaped;
483 logic [DataWidth-1:0] rdata_tlword;
484
485 // This just changes the array format so that the correct word can be selected by indexing.
486 1/1 assign rdata_reshaped = rdata_i;
Tests: T2 T8 T26
487
488 if (EnableDataIntgPt) begin : gen_no_rmask
489 always_comb begin
490 // If the read mask is set to zero, all read data is zeroed out by the mask.
491 // We have to set the ECC bits accordingly since we are using an inverted Hsiao code.
492 rdata_tlword = prim_secded_pkg::SecdedInv3932ZeroWord;
493 // Otherwise, if at least one mask bit is nonzero, we are passing through the integrity.
494 // In that case we need to feed back the entire word since otherwise the integrity
495 // will not calculate correctly.
496 if (|sramreqfifo_rdata.mask) begin
497 // Select correct word.
498 if (DataXorAddr) begin : gen_data_xor_addr
499 // When DataXorAddr is enabled, on a read, the address is XORed with the data fetched from
500 // the memory in the underlying memory controller (e.g., flash controller). At this point,
501 // the address is again removed. If the address in the read transaction has been modified,
502 // e.g., due to a fault, rdata now contains faulty data, which is detected by the
503 // integrity mechanism.
504 rdata_tlword = {
505 rdata_reshaped[sramreqfifo_rdata.woffset][DataWidth-1:top_pkg::TL_DW],
506 rdata_reshaped[sramreqfifo_rdata.woffset][top_pkg::TL_DW-1:0] ^
507 {{(top_pkg::TL_DW-SramBusBankAW){1'b0}}, sramreqaddrfifo_rdata}
508 };
509 end else begin: gen_no_data_xor_addr
510 rdata_tlword = rdata_reshaped[sramreqfifo_rdata.woffset];
511 end
512 end
513 end
514 end else begin : gen_rmask
515 logic [DataWidth-1:0] rmask;
516 always_comb begin
517 1/1 rmask = '0;
Tests: T1 T2 T3
518 1/1 for (int i = 0 ; i < top_pkg::TL_DW/8 ; i++) begin
Tests: T1 T2 T3
519 1/1 rmask[8*i +: 8] = {8{sramreqfifo_rdata.mask[i]}};
Tests: T1 T2 T3
520 end
521 end
522 // Select correct word and mask it.
523 1/1 assign rdata_tlword = rdata_reshaped[sramreqfifo_rdata.woffset] & rmask;
Tests: T1 T2 T3
524 end
525
526 1/1 assign rspfifo_wdata = '{
Tests: T1 T2 T3
527 data : rdata_tlword[top_pkg::TL_DW-1:0],
528 data_intg : EnableDataIntgPt ? rdata_tlword[DataWidth-1 -: DataIntgWidth] : '0,
529 error : rerror_i[1] // Only care for Uncorrectable error
530 };
531 1/1 assign rspfifo_rready = (reqfifo_rdata.op == OpRead & ~reqfifo_rdata.error)
Tests: T1 T2 T3
532 ? reqfifo_rready : 1'b0 ;
533
534 // This module only cares about uncorrectable errors.
535 logic unused_rerror;
536 0/1 ==> assign unused_rerror = rerror_i[0];
537
538 // FIFO instance: REQ, RSP
539
540 // ReqFIFO is to store the Access type to match to the Response data.
541 // For instance, SRAM accepts the write request but doesn't return the
542 // acknowledge. In this case, it may be hard to determine when the D
543 // response for the write data should send out if reads/writes are
544 // interleaved. So, to make it in-order (even TL-UL allows out-of-order
545 // responses), storing the request is necessary. And if the read entry
546 // is write op, it is safe to return the response right away. If it is
547 // read reqeust, then D response is waiting until read data arrives.
548 prim_fifo_sync #(
549 .Width (ReqFifoWidth),
550 .Pass (1'b0),
551 .Depth (Outstanding),
552 .Secure (SecFifoPtr)
553 ) u_reqfifo (
554 .clk_i,
555 .rst_ni,
556 .clr_i (1'b0),
557 .wvalid_i(reqfifo_wvalid),
558 .wready_o(reqfifo_wready),
559 .wdata_i (reqfifo_wdata),
560 .rvalid_o(reqfifo_rvalid),
561 .rready_i(reqfifo_rready),
562 .rdata_o (reqfifo_rdata),
563 .full_o (),
564 .depth_o (),
565 .err_o (reqfifo_error)
566 );
567
568 // sramreqfifo:
569 // While the ReqFIFO holds the request until it is sent back via TL-UL, the
570 // sramreqfifo only needs to hold the mask and word offset until the read
571 // data returns from memory.
572 prim_fifo_sync #(
573 .Width (SramReqFifoWidth),
574 .Pass (1'b0),
575 .Depth (Outstanding),
576 .Secure (SecFifoPtr)
577 ) u_sramreqfifo (
578 .clk_i,
579 .rst_ni,
580 .clr_i (1'b0),
581 .wvalid_i(sramreqfifo_wvalid),
582 .wready_o(sramreqfifo_wready),
583 .wdata_i (sramreqfifo_wdata),
584 .rvalid_o(),
585 .rready_i(sramreqfifo_rready),
586 .rdata_o (sramreqfifo_rdata),
587 .full_o (),
588 .depth_o (),
589 .err_o (sramreqfifo_error)
590 );
591
592 // sramreqaddrfifo:
593 // This fifo holds the address used for undoing the address XOR data infection.
594 if (DataXorAddr) begin : gen_data_xor_addr_fifo
595 prim_fifo_sync #(
596 .Width (SramBusBankAW),
597 .Pass (1'b0),
598 .Depth (Outstanding),
599 .OutputZeroIfEmpty (1)
600 ) u_sramreqaddrfifo (
601 .clk_i,
602 .rst_ni,
603 .clr_i (1'b0),
604 .wvalid_i(sramreqfifo_wvalid),
605 .wready_o(sramreqaddrfifo_wready),
606 .wdata_i (sramreqaddrfifo_wdata),
607 .rvalid_o(),
608 .rready_i(sramreqfifo_rready),
609 .rdata_o (sramreqaddrfifo_rdata),
610 .full_o (),
611 .depth_o (),
612 .err_o ()
613 );
614 end else begin : gen_no_data_xor_addr_fifo
615 assign sramreqaddrfifo_wready = 1'b1;
616 assign sramreqaddrfifo_rdata = '0;
617
618 // Tie-off unused signals
619 logic unused_sramreqaddrfifo;
620 1/1 assign unused_sramreqaddrfifo = ^{sramreqaddrfifo_wdata, sramreqaddrfifo_rdata};
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_tlul2sram_egress
| Total | Covered | Percent |
|---|
| Conditions | 95 | 73 | 76.84 |
| Logical | 95 | 73 | 76.84 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 114
EXPRESSION (readback_error | readback_error_q)
-------1------ --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Unreachable | |
LINE 131
EXPRESSION (intg_error || rsp_fifo_error || sramreqfifo_error || reqfifo_error)
-----1---- -------2------ --------3-------- ------4------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 0 | 1 | Unreachable | |
| 0 | 0 | 1 | 0 | Unreachable | |
| 0 | 1 | 0 | 0 | Unreachable | |
| 1 | 0 | 0 | 0 | Unreachable | |
LINE 138
EXPRESSION (intg_error | rsp_fifo_error | sramreqfifo_error | reqfifo_error | intg_error_q)
-----1---- -------2------ --------3-------- ------4------ ------5-----
| -1- | -2- | -3- | -4- | -5- | Status | Tests | Exclude Annotation |
|---|
| 0 | 0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 0 | 0 | 1 | Excluded | |
VC_COV_UNR |
| 0 | 0 | 0 | 1 | 0 | Unreachable | |
| 0 | 0 | 1 | 0 | 0 | Unreachable | |
| 0 | 1 | 0 | 0 | 0 | Unreachable | |
| 1 | 0 | 0 | 0 | 0 | Unreachable | |
LINE 144
EXPRESSION
Number Term
1 ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T4,T5 |
LINE 144
SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
---------------1-------------- ----------------2----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T2,T4,T5 |
| 1 | 0 | Covered | T2,T4,T5 |
LINE 144
SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
---------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T4,T5 |
LINE 144
SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T4,T5 |
LINE 144
SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
---------1--------- ----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T2,T4,T5 |
| 0 | 1 | Covered | T4,T8,T10 |
| 1 | 0 | Covered | T4,T5,T8 |
LINE 144
SUB-EXPRESSION (tl_i.a_mask != '1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T4,T5 |
| 1 | Covered | T4,T5,T8 |
LINE 144
SUB-EXPRESSION (tl_i.a_size != 2'h2)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T4,T5 |
| 1 | Covered | T4,T5,T8 |
LINE 162
EXPRESSION (tl_i.a_opcode == Get)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 176
EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
------1------ ------2----- ------3----- -----4----- -----5---- -----6----
| -1- | -2- | -3- | -4- | -5- | -6- | Status | Tests | Exclude Annotation |
|---|
| 0 | 0 | 0 | 0 | 0 | 0 | Covered | T2,T9,T10 |
| 0 | 0 | 0 | 0 | 0 | 1 | Unreachable | |
| 0 | 0 | 0 | 0 | 1 | 0 | Covered | T4,T5,T8 |
| 0 | 0 | 0 | 1 | 0 | 0 | Excluded | |
VC_COV_UNR |
| 0 | 0 | 1 | 0 | 0 | 0 | Not Covered | |
| 0 | 1 | 0 | 0 | 0 | 0 | Unreachable | |
| 1 | 0 | 0 | 0 | 0 | 0 | Not Covered | |
LINE 272
EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
--------1------- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T2,T9,T10 |
| 1 | 1 | Covered | T2,T9,T10 |
LINE 273
EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
--------1------- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T10,T11 |
| 1 | 1 | Covered | T2,T9,T10 |
LINE 274
EXPRESSION (req_o & gnt_i)
--1-- --2--
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T2,T9,T10 |
LINE 285
EXPRESSION (reqfifo_rdata.op == OpRead)
--------------1-------------
| -1- | Status | Tests | Exclude Annotation |
|---|
| 0 | Covered | T2,T9,T10 |
| 1 | Excluded | |
VC_COV_UNR |
LINE 302
EXPRESSION (reqfifo_rdata.op == OpRead)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T9,T10 |
| 1 | Not Covered | |
LINE 303
EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
---------1--------- ---------2---------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 0 | Excluded | |
VC_COV_UNR |
| 0 | 1 | Not Covered | |
| 1 | 0 | Excluded | |
VC_COV_UNR |
LINE 313
EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
---1--- -------2------ -------3------ --------------4-------------
| -1- | -2- | -3- | -4- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 0 | 1 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | 1 | Excluded | |
VC_COV_UNR |
LINE 313
SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 341
EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
-------------1-------------
| -1- | Status | Tests | Exclude Annotation |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Excluded | |
VC_COV_UNR |
LINE 341
SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
-----1---- ------2-----
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | Excluded | |
VC_COV_UNR |
LINE 347
EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
-----------------1-----------------
| -1- | Status | Tests | Exclude Annotation |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Excluded | |
VC_COV_UNR |
LINE 347
SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
-----1---- ---------2---------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | Excluded | |
VC_COV_UNR |
LINE 347
SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
-----1----
| -1- | Status | Tests | Exclude Annotation |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Excluded | |
VC_COV_UNR |
LINE 359
EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
-------1------ --------2------- ----------3----------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T2,T9,T10 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Not Covered | |
LINE 369
EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
--------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T9,T10 |
LINE 369
SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
---1--- --------------2-------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T2,T9,T10 |
LINE 369
SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 369
EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T9,T10 |
LINE 369
EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T9,T10 |
LINE 369
EXPRESSION (d_valid && d_error)
---1--- ---2---
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 0 | Covered | T2,T9,T10 |
| 1 | 1 | Not Covered | |
LINE 369
EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready & sramreqaddrfifo_wready)
-------------1------------ -------2------ ---------3-------- -----------4----------
| -1- | -2- | -3- | -4- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Not Covered | |
| 1 | 1 | 0 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | 1 | Covered | T2,T9,T10 |
LINE 369
SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
--1-- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T2,T9,T10 |
LINE 390
EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
--------1------- -------2------ ---------3---------
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 0 | 1 | Covered | T2,T9,T10 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T2,T9,T10 |
LINE 392
EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
--------1------- ----------------------------2---------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T8 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T2,T9,T10 |
LINE 393
EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
--------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T9,T10 |
LINE 429
EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Covered | T2,T9,T10 |
LINE 429
SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
---------1-------- --2-
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T2,T9,T10 |
LINE 452
EXPRESSION (((|wmask_intg)) & ((|wdata_intg)))
-------1------- -------2-------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Excluded | |
vcs_gen_start:i=0:vcs_gen_end:VC_COV_UNR |
| 1 | 0 | Covered | T2,T9,T10 |
| 1 | 1 | Covered | T2,T9,T10 |
LINE 460
EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
-------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T4,T5 |
LINE 460
SUB-EXPRESSION (tl_i_int.a_opcode != Get)
-------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T4,T5 |
LINE 474
EXPRESSION (sram_ack & ((~we_o)))
----1--- ----2----
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T9,T10 |
| 1 | 1 | Excluded | |
VC_COV_UNR |
LINE 477
EXPRESSION (rvalid_i & reqfifo_rvalid)
----1--- -------2------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Covered | T2,T9,T10 |
| 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | Excluded | |
VC_COV_UNR |
LINE 531
EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
----------------------------1----------------------------
| -1- | Status | Tests | Exclude Annotation |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Excluded | |
VC_COV_UNR |
LINE 531
SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
--------------1------------- ------------2-----------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Excluded | |
VC_COV_UNR |
LINE 531
SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
Branch Coverage for Instance : tb.dut.u_tlul2sram_egress
| Line No. | Total | Covered | Percent |
| Branches |
|
21 |
19 |
90.48 |
| TERNARY |
144 |
2 |
2 |
100.00 |
| TERNARY |
341 |
1 |
1 |
100.00 |
| TERNARY |
347 |
1 |
1 |
100.00 |
| TERNARY |
393 |
2 |
2 |
100.00 |
| TERNARY |
531 |
1 |
1 |
100.00 |
| IF |
129 |
2 |
2 |
100.00 |
| IF |
281 |
3 |
2 |
66.67 |
| IF |
301 |
3 |
2 |
66.67 |
| IF |
362 |
2 |
2 |
100.00 |
| IF |
426 |
2 |
2 |
100.00 |
| IF |
438 |
2 |
2 |
100.00 |
144 assign wr_attr_error = (tl_i.a_opcode == PutFullData || tl_i.a_opcode == PutPartialData)
145 ? ((ByteAccess == 0) ?
146 (tl_i.a_mask != '1 || tl_i.a_size != 2'h2) : 1'b0)
147 : 1'b0;
ID LINE
-1- 144 ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T4,T5 |
| 0 |
Covered |
T1,T2,T3 |
341 assign d_data = (vld_rd_rsp & ~d_error) ? rspfifo_rdata.data // valid read
-1-
==> (Excluded)
==>
Branches:
| -1- | Status | Tests | Exclude Annotation |
| 1 |
Excluded |
|
VC_COV_UNR |
| 0 |
Covered |
T1,T2,T3 |
|
347 assign data_intg = (vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : // TL-UL error
-1-
==> (Excluded)
348 (vld_rd_rsp) ? rspfifo_rdata.data_intg : // valid read
-2-
==> (Excluded)
==>
Branches:
| -1- | -2- | Status | Tests | Exclude Annotation |
| 1 |
- |
Excluded |
|
VC_COV_UNR |
| 0 |
1 |
Excluded |
|
VC_COV_UNR |
| 0 |
0 |
Covered |
T1,T2,T3 |
|
393 assign addr_o = (tl_i_int.a_valid) ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T9,T10 |
| 0 |
Covered |
T1,T2,T3 |
531 assign rspfifo_rready = (reqfifo_rdata.op == OpRead & ~reqfifo_rdata.error)
532 ? reqfifo_rready : 1'b0 ;
-1-
==> (Excluded)
==>
Branches:
| -1- | Status | Tests | Exclude Annotation |
| 1 |
Excluded |
|
VC_COV_UNR |
| 0 |
Covered |
T1,T2,T3 |
|
129 if (!rst_ni) begin
-1-
130 intg_error_q <= '0;
==>
131 end else if (intg_error || rsp_fifo_error || sramreqfifo_error || reqfifo_error) begin
-2-
132 intg_error_q <= 1'b1;
==> (Unreachable)
133 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Unreachable |
|
| 0 |
0 |
Covered |
T1,T2,T3 |
281 if (reqfifo_rvalid) begin
-1-
282 if (reqfifo_rdata.error) begin
-2-
283 // Return error response. Assume no request went out to SRAM
284 d_valid = 1'b1;
==>
285 end else if (reqfifo_rdata.op == OpRead) begin
-3-
286 d_valid = rspfifo_rvalid;
==> (Excluded)
Exclude Annotation: VC_COV_UNR
287 end else begin
288 // Write without error
289 d_valid = 1'b1;
==>
290 end
291 end else begin
292 d_valid = 1'b0;
==>
Branches:
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
| 1 |
1 |
- |
Not Covered |
|
|
| 1 |
0 |
1 |
Excluded |
|
VC_COV_UNR |
| 1 |
0 |
0 |
Covered |
T2,T9,T10 |
|
| 0 |
- |
- |
Covered |
T1,T2,T3 |
|
301 if (reqfifo_rvalid) begin
-1-
302 if (reqfifo_rdata.op == OpRead) begin
-2-
303 d_error = rspfifo_rdata.error | reqfifo_rdata.error;
==>
304 end else begin
305 d_error = reqfifo_rdata.error;
==>
306 end
307 end else begin
308 d_error = 1'b0;
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
1 |
Not Covered |
|
| 1 |
0 |
Covered |
T2,T9,T10 |
| 0 |
- |
Covered |
T1,T2,T3 |
362 if (!rst_ni) begin
-1-
363 missed_err_gnt_q <= 1'b0;
==>
364 end else begin
365 missed_err_gnt_q <= missed_err_gnt_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
426 if (tl_i_int.a_valid) begin
-1-
427 for (int i = 0 ; i < top_pkg::TL_DW/8 ; i++) begin
==>
428 wmask_int[woffset][8*i +: 8] = {8{tl_i_int.a_mask[i]}};
429 wdata_int[woffset][8*i +: 8] = (tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[8*i+:8] : '0;
430 end
431 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T9,T10 |
| 0 |
Covered |
T1,T2,T3 |
438 if (tl_i_int.a_valid) begin
-1-
439 wmask_intg[woffset] = {DataIntgWidth{1'b1}};
==>
440 wdata_intg[woffset] = tl_i_int.a_user.data_intg;
441 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T9,T10 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_tlul2sram_egress
Assertion Details
AddrOutKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
459421869 |
459332103 |
0 |
0 |
| T1 |
952 |
886 |
0 |
0 |
| T2 |
2418 |
2357 |
0 |
0 |
| T3 |
1718 |
1635 |
0 |
0 |
| T4 |
67232 |
67166 |
0 |
0 |
| T5 |
2198 |
2107 |
0 |
0 |
| T6 |
5598 |
4103 |
0 |
0 |
| T7 |
1923 |
1826 |
0 |
0 |
| T8 |
4287 |
4217 |
0 |
0 |
| T9 |
9735 |
9655 |
0 |
0 |
| T10 |
9668 |
9605 |
0 |
0 |
DataIntgOptions_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
976 |
976 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
ReqOutKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
459421869 |
459332103 |
0 |
0 |
| T1 |
952 |
886 |
0 |
0 |
| T2 |
2418 |
2357 |
0 |
0 |
| T3 |
1718 |
1635 |
0 |
0 |
| T4 |
67232 |
67166 |
0 |
0 |
| T5 |
2198 |
2107 |
0 |
0 |
| T6 |
5598 |
4103 |
0 |
0 |
| T7 |
1923 |
1826 |
0 |
0 |
| T8 |
4287 |
4217 |
0 |
0 |
| T9 |
9735 |
9655 |
0 |
0 |
| T10 |
9668 |
9605 |
0 |
0 |
SramDwHasByteGranularity_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
976 |
976 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
SramDwIsMultipleOfTlulWidth_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
976 |
976 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
TlOutKnownIfFifoKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
459421869 |
459332103 |
0 |
0 |
| T1 |
952 |
886 |
0 |
0 |
| T2 |
2418 |
2357 |
0 |
0 |
| T3 |
1718 |
1635 |
0 |
0 |
| T4 |
67232 |
67166 |
0 |
0 |
| T5 |
2198 |
2107 |
0 |
0 |
| T6 |
5598 |
4103 |
0 |
0 |
| T7 |
1923 |
1826 |
0 |
0 |
| T8 |
4287 |
4217 |
0 |
0 |
| T9 |
9735 |
9655 |
0 |
0 |
| T10 |
9668 |
9605 |
0 |
0 |
TlOutValidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
459421869 |
459332103 |
0 |
0 |
| T1 |
952 |
886 |
0 |
0 |
| T2 |
2418 |
2357 |
0 |
0 |
| T3 |
1718 |
1635 |
0 |
0 |
| T4 |
67232 |
67166 |
0 |
0 |
| T5 |
2198 |
2107 |
0 |
0 |
| T6 |
5598 |
4103 |
0 |
0 |
| T7 |
1923 |
1826 |
0 |
0 |
| T8 |
4287 |
4217 |
0 |
0 |
| T9 |
9735 |
9655 |
0 |
0 |
| T10 |
9668 |
9605 |
0 |
0 |
WdataOutKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
459421869 |
459332103 |
0 |
0 |
| T1 |
952 |
886 |
0 |
0 |
| T2 |
2418 |
2357 |
0 |
0 |
| T3 |
1718 |
1635 |
0 |
0 |
| T4 |
67232 |
67166 |
0 |
0 |
| T5 |
2198 |
2107 |
0 |
0 |
| T6 |
5598 |
4103 |
0 |
0 |
| T7 |
1923 |
1826 |
0 |
0 |
| T8 |
4287 |
4217 |
0 |
0 |
| T9 |
9735 |
9655 |
0 |
0 |
| T10 |
9668 |
9605 |
0 |
0 |
WeOutKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
459421869 |
459332103 |
0 |
0 |
| T1 |
952 |
886 |
0 |
0 |
| T2 |
2418 |
2357 |
0 |
0 |
| T3 |
1718 |
1635 |
0 |
0 |
| T4 |
67232 |
67166 |
0 |
0 |
| T5 |
2198 |
2107 |
0 |
0 |
| T6 |
5598 |
4103 |
0 |
0 |
| T7 |
1923 |
1826 |
0 |
0 |
| T8 |
4287 |
4217 |
0 |
0 |
| T9 |
9735 |
9655 |
0 |
0 |
| T10 |
9668 |
9605 |
0 |
0 |
WmaskOutKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
459421869 |
459332103 |
0 |
0 |
| T1 |
952 |
886 |
0 |
0 |
| T2 |
2418 |
2357 |
0 |
0 |
| T3 |
1718 |
1635 |
0 |
0 |
| T4 |
67232 |
67166 |
0 |
0 |
| T5 |
2198 |
2107 |
0 |
0 |
| T6 |
5598 |
4103 |
0 |
0 |
| T7 |
1923 |
1826 |
0 |
0 |
| T8 |
4287 |
4217 |
0 |
0 |
| T9 |
9735 |
9655 |
0 |
0 |
| T10 |
9668 |
9605 |
0 |
0 |
adapterNoReadOrWrite
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
976 |
976 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
rvalidHighReqFifoEmpty
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
459421869 |
0 |
0 |
0 |
rvalidHighWhenRspFifoFull
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
459421869 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_tlul2sram_ingress
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 72 | 69 | 95.83 |
| CONT_ASSIGN | 107 | 0 | 0 | |
| CONT_ASSIGN | 114 | 0 | 0 | |
| ALWAYS | 129 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 176 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 272 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 273 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 274 | 1 | 1 | 100.00 |
| ALWAYS | 279 | 7 | 6 | 85.71 |
| ALWAYS | 299 | 6 | 5 | 83.33 |
| CONT_ASSIGN | 313 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 317 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 336 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 341 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 347 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 359 | 1 | 1 | 100.00 |
| ALWAYS | 362 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 369 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 390 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 391 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 392 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 393 | 1 | 1 | 100.00 |
| ALWAYS | 423 | 6 | 6 | 100.00 |
| ALWAYS | 435 | 5 | 5 | 100.00 |
| CONT_ASSIGN | 450 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 451 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 452 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 456 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 457 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 459 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 460 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 467 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 470 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 474 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 475 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 477 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 479 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 486 | 1 | 1 | 100.00 |
| ALWAYS | 517 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 523 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 526 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 531 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 536 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 620 | 1 | 1 | 100.00 |
106 logic unused_sram_byte_readback_error;
107 unreachable assign unused_sram_byte_readback_error = sram_byte_readback_error;
108 assign readback_error = '0;
109 assign readback_error_q = '0;
110 end
111
112 // readback error output is permanent and should be used for alert generation
113 // or other downstream effects
114 unreachable assign readback_error_o = readback_error | readback_error_q;
115
116 // integrity check
117 if (CmdIntgCheck) begin : gen_cmd_intg_check
118 tlul_cmd_intg_chk u_cmd_intg_chk (
119 .tl_i(tl_i),
120 .err_o (intg_error)
121 );
122 end else begin : gen_no_cmd_intg_check
123 assign intg_error = '0;
124 end
125
126 // permanently latch integrity error until reset
127 logic intg_error_q;
128 always_ff @(posedge clk_i or negedge rst_ni) begin
129 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
130 1/1 intg_error_q <= '0;
Tests: T1 T2 T3
131 1/1 end else if (intg_error || rsp_fifo_error || sramreqfifo_error || reqfifo_error) begin
Tests: T1 T2 T3
132 unreachable intg_error_q <= 1'b1;
133 end
MISSING_ELSE
134 end
135
136 // integrity error output is permanent and should be used for alert generation
137 // or other downstream effects
138 1/1 assign intg_error_o = intg_error | rsp_fifo_error | sramreqfifo_error |
Tests: T1 T2 T3
139 reqfifo_error | intg_error_q;
140
141 // wr_attr_error: Check if the request size, mask are permitted.
142 // Basic check of size, mask, addr align is done in tlul_err module.
143 // Here it checks any partial write if ByteAccess isn't allowed.
144 1/1 assign wr_attr_error = (tl_i.a_opcode == PutFullData || tl_i.a_opcode == PutPartialData)
Tests: T1 T2 T3
145 ? ((ByteAccess == 0) ?
146 (tl_i.a_mask != '1 || tl_i.a_size != 2'h2) : 1'b0)
147 : 1'b0;
148
149 // An instruction type transaction is only valid if en_ifetch is enabled
150 // If the instruction type is completely invalid, also considered an instruction error
151 1/1 assign instr_error = prim_mubi_pkg::mubi4_test_invalid(tl_i.a_user.instr_type) |
Tests: T1 T2 T3
152 (prim_mubi_pkg::mubi4_test_true_strict(tl_i.a_user.instr_type) &
153 prim_mubi_pkg::mubi4_test_false_loose(en_ifetch_i));
154
155 if (ErrOnWrite == 1) begin : gen_no_writes
156 1/1 assign wr_vld_error = tl_i.a_opcode != Get;
Tests: T1 T2 T3
157 end else begin : gen_writes_allowed
158 assign wr_vld_error = 1'b0;
159 end
160
161 if (ErrOnRead == 1) begin: gen_no_reads
162 assign rd_vld_error = tl_i.a_opcode == Get;
163 end else begin : gen_reads_allowed
164 assign rd_vld_error = 1'b0;
165 end
166
167 // tlul protocol check
168 tlul_err u_err (
169 .clk_i,
170 .rst_ni,
171 .tl_i(tl_i),
172 .err_o (tlul_error)
173 );
174
175 // error return is transactional and thus does not used the "latched" intg_err signal
176 1/1 assign error_det = wr_attr_error | wr_vld_error | rd_vld_error | instr_error |
Tests: T1 T2 T3
177 tlul_error | intg_error;
178
179 // from sram_byte to adapter logic
180 tl_h2d_t tl_i_int;
181 // from adapter logic to sram_byte
182 tl_d2h_t tl_o_int;
183 // from sram_byte to rsp_gen
184 tl_d2h_t tl_out;
185
186 // not all parts of tl_i_int are used
187 logic unused_tl_i_int;
188 1/1 assign unused_tl_i_int = ^tl_i_int;
Tests: T1 T2 T3
189
190 tlul_rsp_intg_gen #(
191 .EnableRspIntgGen(EnableRspIntgGen),
192 .EnableDataIntgGen(EnableDataIntgGen)
193 ) u_rsp_gen (
194 .tl_i(tl_out),
195 .tl_o
196 );
197
198 // byte handling for integrity
199 tlul_sram_byte #(
200 .EnableIntg(ByteAccess & EnableDataIntgPt & !ErrOnWrite),
201 .Outstanding(Outstanding),
202 .EnableReadback(EnableReadback)
203 ) u_sram_byte (
204 .clk_i,
205 .rst_ni,
206 .tl_i,
207 .tl_o(tl_out),
208 .tl_sram_o(tl_i_int),
209 .tl_sram_i(tl_o_int),
210 .error_i(error_det),
211 .error_o(error_internal),
212 .alert_o(sram_byte_readback_error),
213 .compound_txn_in_progress_o,
214 .readback_en_i,
215 .wr_collision_i,
216 .write_pending_i
217 );
218
219 typedef struct packed {
220 logic [top_pkg::TL_DBW-1:0] mask ; // Byte mask within the TL-UL word
221 logic [WoffsetWidth-1:0] woffset ; // Offset of the TL-UL word within the SRAM word
222 } sram_req_t ;
223
224 typedef struct packed {
225 logic [SramBusBankAW-1:0] addr; // Address of the request going to the memory.
226 } sram_req_addr_t ;
227
228 typedef enum logic [1:0] {
229 OpWrite,
230 OpRead,
231 OpUnknown
232 } req_op_e ;
233
234 typedef struct packed {
235 req_op_e op ;
236 logic error ;
237 prim_mubi_pkg::mubi4_t instr_type;
238 logic [top_pkg::TL_SZW-1:0] size ;
239 logic [top_pkg::TL_AIW-1:0] source ;
240 } req_t ;
241
242 typedef struct packed {
243 logic [top_pkg::TL_DW-1:0] data ;
244 logic [DataIntgWidth-1:0] data_intg ;
245 logic error ;
246 } rsp_t ;
247
248 localparam int SramReqFifoWidth = $bits(sram_req_t) ;
249 localparam int ReqFifoWidth = $bits(req_t) ;
250 localparam int RspFifoWidth = $bits(rsp_t) ;
251
252 // FIFO signal in case OutStand is greater than 1
253 // If request is latched, {write, source} is pushed to req fifo.
254 // Req fifo is popped when D channel is acknowledged (v & r)
255 // D channel valid is asserted if it is write request or rsp fifo not empty if read.
256 logic reqfifo_wvalid, reqfifo_wready;
257 logic reqfifo_rvalid, reqfifo_rready;
258 req_t reqfifo_wdata, reqfifo_rdata;
259
260 logic sramreqfifo_wvalid, sramreqfifo_wready;
261 logic sramreqfifo_rready;
262 sram_req_t sramreqfifo_wdata, sramreqfifo_rdata;
263
264 logic sramreqaddrfifo_wready;
265 logic [SramBusBankAW-1:0] sramreqaddrfifo_wdata, sramreqaddrfifo_rdata;
266
267 logic rspfifo_wvalid, rspfifo_wready;
268 logic rspfifo_rvalid, rspfifo_rready;
269 rsp_t rspfifo_wdata, rspfifo_rdata;
270
271 logic a_ack, d_ack, sram_ack;
272 1/1 assign a_ack = tl_i_int.a_valid & tl_o_int.a_ready ;
Tests: T1 T2 T3
273 1/1 assign d_ack = tl_o_int.d_valid & tl_i_int.d_ready ;
Tests: T1 T2 T3
274 1/1 assign sram_ack = req_o & gnt_i ;
Tests: T1 T2 T3
275
276 // Valid handling
277 logic d_valid, d_error;
278 always_comb begin
279 1/1 d_valid = 1'b0;
Tests: T1 T2 T3
280
281 1/1 if (reqfifo_rvalid) begin
Tests: T1 T2 T3
282 1/1 if (reqfifo_rdata.error) begin
Tests: T2 T8 T26
283 // Return error response. Assume no request went out to SRAM
284 0/1 ==> d_valid = 1'b1;
285 1/1 end else if (reqfifo_rdata.op == OpRead) begin
Tests: T2 T8 T26
286 1/1 d_valid = rspfifo_rvalid;
Tests: T2 T8 T26
287 end else begin
288 // Write without error
289 excluded d_valid = 1'b1;
Exclude Annotation: VC_COV_UNR
290 end
291 end else begin
292 1/1 d_valid = 1'b0;
Tests: T1 T2 T3
293 end
294 end
295
296
297
298 always_comb begin
299 1/1 d_error = 1'b0;
Tests: T1 T2 T3
300
301 1/1 if (reqfifo_rvalid) begin
Tests: T1 T2 T3
302 1/1 if (reqfifo_rdata.op == OpRead) begin
Tests: T2 T8 T26
303 1/1 d_error = rspfifo_rdata.error | reqfifo_rdata.error;
Tests: T2 T8 T26
304 end else begin
305 0/1 ==> d_error = reqfifo_rdata.error;
306 end
307 end else begin
308 1/1 d_error = 1'b0;
Tests: T1 T2 T3
309 end
310 end
311
312 logic vld_rd_rsp;
313 1/1 assign vld_rd_rsp = d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead);
Tests: T1 T2 T3
314 // If the response data is not valid, we set it to an illegal blanking value which is determined
315 // by whether the current transaction is an instruction fetch or a regular read operation.
316 logic [top_pkg::TL_DW-1:0] error_blanking_data;
317 1/1 assign error_blanking_data = (prim_mubi_pkg::mubi4_test_true_strict(reqfifo_rdata.instr_type)) ?
Tests: T1 T2 T3
318 DataWhenInstrError :
319 DataWhenError;
320
321 // Since DataWhenInstrError and DataWhenError can be arbitrary parameters
322 // we statically calculate the correct integrity values for these parameters here so that
323 // they do not have to be supplied externally.
324 logic [top_pkg::TL_DW-1:0] unused_instr, unused_data;
325 logic [DataIntgWidth-1:0] error_instr_integ, error_data_integ;
326 tlul_data_integ_enc u_tlul_data_integ_enc_instr (
327 .data_i(DataMaxWidth'(DataWhenInstrError)),
328 .data_intg_o({error_instr_integ, unused_instr})
329 );
330 tlul_data_integ_enc u_tlul_data_integ_enc_data (
331 .data_i(DataMaxWidth'(DataWhenError)),
332 .data_intg_o({error_data_integ, unused_data})
333 );
334
335 logic [DataIntgWidth-1:0] error_blanking_integ;
336 1/1 assign error_blanking_integ = (prim_mubi_pkg::mubi4_test_true_strict(reqfifo_rdata.instr_type)) ?
Tests: T1 T2 T3
337 error_instr_integ :
338 error_data_integ;
339
340 logic [top_pkg::TL_DW-1:0] d_data;
341 1/1 assign d_data = (vld_rd_rsp & ~d_error) ? rspfifo_rdata.data // valid read
Tests: T1 T2 T3
342 : error_blanking_data; // write or TL-UL error
343
344 // If this a write response with data fields set to 0, we have to set all ECC bits correctly
345 // since we are using an inverted Hsiao code.
346 logic [DataIntgWidth-1:0] data_intg;
347 1/1 assign data_intg = (vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : // TL-UL error
Tests: T1 T2 T3
348 (vld_rd_rsp) ? rspfifo_rdata.data_intg : // valid read
349 prim_secded_pkg::SecdedInv3932ZeroEcc; // valid write
350
351 // When an error is seen on an incoming transaction it gets an immediate response without
352 // performing an SRAM request. It may be the transaction receives a ready the first cycle it is
353 // seen, but if not we force a ready the following cycle. This avoids factoring the error
354 // calculation into the outgoing ready preventing a feedthrough path from the incoming tilelink
355 // signals to the outgoing tilelink signals.
356 logic missed_err_gnt_d, missed_err_gnt_q;
357
358 // Track whether we've seen an incoming transaction with an error that didn't get a ready
359 1/1 assign missed_err_gnt_d = error_internal & tl_i_int.a_valid & ~tl_o_int.a_ready;
Tests: T1 T2 T3
360
361 always_ff @(posedge clk_i or negedge rst_ni) begin
362 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
363 1/1 missed_err_gnt_q <= 1'b0;
Tests: T1 T2 T3
364 end else begin
365 1/1 missed_err_gnt_q <= missed_err_gnt_d;
Tests: T1 T2 T3
366 end
367 end
368
369 1/1 assign tl_o_int = '{
Tests: T1 T2 T3
370 d_valid : d_valid ,
371 d_opcode : (d_valid && reqfifo_rdata.op != OpRead) ? AccessAck : AccessAckData,
372 d_param : '0,
373 d_size : (d_valid) ? reqfifo_rdata.size : '0,
374 d_source : (d_valid) ? reqfifo_rdata.source : '0,
375 d_sink : 1'b0,
376 d_data : d_data,
377 d_user : '{default: '0, data_intg: data_intg},
378 d_error : d_valid && d_error,
379 a_ready : (gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready &
380 sramreqaddrfifo_wready
381 };
382
383 // a_ready depends on the FIFO full condition and grant from SRAM (or SRAM arbiter)
384 // assemble response, including read response, write response, and error for unsupported stuff
385
386 // Output to SRAM:
387 // Generate request only when no internal error occurs. If error occurs, the request should be
388 // dropped and returned error response to the host. So, error to be pushed to reqfifo.
389 // In this case, it is assumed the request is granted (may cause ordering issue later?)
390 1/1 assign req_o = tl_i_int.a_valid & reqfifo_wready & ~error_internal;
Tests: T1 T2 T3
391 1/1 assign req_type_o = tl_i_int.a_user.instr_type;
Tests: T1 T2 T3
392 1/1 assign we_o = tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData});
Tests: T1 T2 T3
393 1/1 assign addr_o = (tl_i_int.a_valid) ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0;
Tests: T1 T2 T3
394
395 // Support SRAMs wider than the TL-UL word width by mapping the parts of the
396 // TL-UL address which are more fine-granular than the SRAM width to the
397 // SRAM write mask.
398 logic [WoffsetWidth-1:0] woffset;
399 if (top_pkg::TL_DW != SramDw) begin : gen_wordwidthadapt
400 assign woffset = tl_i_int.a_address[DataBitWidth-1:prim_util_pkg::vbits(top_pkg::TL_DBW)];
401 end else begin : gen_no_wordwidthadapt
402 assign woffset = '0;
403 end
404
405 // The size of the data/wmask depends on whether passthrough integrity is enabled.
406 // If passthrough integrity is enabled, the data is concatenated with the integrity passed through
407 // the user bits. Otherwise, it is the data only.
408 localparam int DataWidth = EnableDataIntgPt ? top_pkg::TL_DW + DataIntgWidth : top_pkg::TL_DW;
409
410 // Final combined wmask / wdata
411 logic [WidthMult-1:0][DataWidth-1:0] wmask_combined;
412 logic [WidthMult-1:0][DataWidth-1:0] wdata_combined;
413
414 // Original tlul portion
415 logic [WidthMult-1:0][top_pkg::TL_DW-1:0] wmask_int;
416 logic [WidthMult-1:0][top_pkg::TL_DW-1:0] wdata_int;
417
418 // Integrity portion
419 logic [WidthMult-1:0][DataIntgWidth-1:0] wmask_intg;
420 logic [WidthMult-1:0][DataIntgWidth-1:0] wdata_intg;
421
422 always_comb begin
423 1/1 wmask_int = '0;
Tests: T1 T2 T3
424 1/1 wdata_int = '0;
Tests: T1 T2 T3
425
426 1/1 if (tl_i_int.a_valid) begin
Tests: T1 T2 T3
427 1/1 for (int i = 0 ; i < top_pkg::TL_DW/8 ; i++) begin
Tests: T2 T8 T26
428 1/1 wmask_int[woffset][8*i +: 8] = {8{tl_i_int.a_mask[i]}};
Tests: T2 T8 T26
429 1/1 wdata_int[woffset][8*i +: 8] = (tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[8*i+:8] : '0;
Tests: T2 T8 T26
430 end
431 end
MISSING_ELSE
432 end
433
434 always_comb begin
435 1/1 wmask_intg = '0;
Tests: T1 T2 T3
436 1/1 wdata_intg = '0;
Tests: T1 T2 T3
437
438 1/1 if (tl_i_int.a_valid) begin
Tests: T1 T2 T3
439 1/1 wmask_intg[woffset] = {DataIntgWidth{1'b1}};
Tests: T2 T8 T26
440 1/1 wdata_intg[woffset] = tl_i_int.a_user.data_intg;
Tests: T2 T8 T26
441 end
MISSING_ELSE
442 end
443
444 for (genvar i = 0; i < WidthMult; i++) begin : gen_write_output
445 if (EnableDataIntgPt) begin : gen_combined_output
446 assign wmask_combined[i] = {wmask_intg[i], wmask_int[i]};
447 assign wdata_combined[i] = {wdata_intg[i], wdata_int[i]};
448 end else begin : gen_ft_output
449 logic unused_w;
450 1/1 assign wmask_combined[i] = wmask_int[i];
Tests: T1 T2 T3
451 1/1 assign wdata_combined[i] = wdata_int[i];
Tests: T1 T2 T3
452 1/1 assign unused_w = |wmask_intg & |wdata_intg;
Tests: T1 T2 T3
453 end
454 end
455
456 1/1 assign wmask_o = wmask_combined;
Tests: T1 T2 T3
457 1/1 assign wdata_o = wdata_combined;
Tests: T1 T2 T3
458
459 1/1 assign reqfifo_wvalid = a_ack ; // Push to FIFO only when granted
Tests: T2 T8 T26
460 1/1 assign reqfifo_wdata = '{
Tests: T1 T2 T3
461 op: (tl_i_int.a_opcode != Get) ? OpWrite : OpRead, // To return AccessAck for opcode error
462 error: error_internal,
463 instr_type: tl_i_int.a_user.instr_type,
464 size: tl_i_int.a_size,
465 source: tl_i_int.a_source
466 }; // Store the request only. Doesn't have to store data
467 1/1 assign reqfifo_rready = d_ack ;
Tests: T2 T8 T26
468
469 // push together with ReqFIFO, pop upon returning read
470 1/1 assign sramreqfifo_wdata = '{
Tests: T1 T2 T3
471 mask : tl_i_int.a_mask,
472 woffset : woffset
473 };
474 1/1 assign sramreqfifo_wvalid = sram_ack & ~we_o;
Tests: T1 T2 T3
475 1/1 assign sramreqfifo_rready = rspfifo_wvalid;
Tests: T1 T2 T3
476
477 1/1 assign rspfifo_wvalid = rvalid_i & reqfifo_rvalid;
Tests: T1 T2 T3
478
479 1/1 assign sramreqaddrfifo_wdata = tl_i_int.a_address[DataBitWidth+:SramBusBankAW];
Tests: T1 T2 T3
480
481 // Make sure only requested bytes are forwarded
482 logic [WidthMult-1:0][DataWidth-1:0] rdata_reshaped;
483 logic [DataWidth-1:0] rdata_tlword;
484
485 // This just changes the array format so that the correct word can be selected by indexing.
486 1/1 assign rdata_reshaped = rdata_i;
Tests: T2 T8 T26
487
488 if (EnableDataIntgPt) begin : gen_no_rmask
489 always_comb begin
490 // If the read mask is set to zero, all read data is zeroed out by the mask.
491 // We have to set the ECC bits accordingly since we are using an inverted Hsiao code.
492 rdata_tlword = prim_secded_pkg::SecdedInv3932ZeroWord;
493 // Otherwise, if at least one mask bit is nonzero, we are passing through the integrity.
494 // In that case we need to feed back the entire word since otherwise the integrity
495 // will not calculate correctly.
496 if (|sramreqfifo_rdata.mask) begin
497 // Select correct word.
498 if (DataXorAddr) begin : gen_data_xor_addr
499 // When DataXorAddr is enabled, on a read, the address is XORed with the data fetched from
500 // the memory in the underlying memory controller (e.g., flash controller). At this point,
501 // the address is again removed. If the address in the read transaction has been modified,
502 // e.g., due to a fault, rdata now contains faulty data, which is detected by the
503 // integrity mechanism.
504 rdata_tlword = {
505 rdata_reshaped[sramreqfifo_rdata.woffset][DataWidth-1:top_pkg::TL_DW],
506 rdata_reshaped[sramreqfifo_rdata.woffset][top_pkg::TL_DW-1:0] ^
507 {{(top_pkg::TL_DW-SramBusBankAW){1'b0}}, sramreqaddrfifo_rdata}
508 };
509 end else begin: gen_no_data_xor_addr
510 rdata_tlword = rdata_reshaped[sramreqfifo_rdata.woffset];
511 end
512 end
513 end
514 end else begin : gen_rmask
515 logic [DataWidth-1:0] rmask;
516 always_comb begin
517 1/1 rmask = '0;
Tests: T1 T2 T3
518 1/1 for (int i = 0 ; i < top_pkg::TL_DW/8 ; i++) begin
Tests: T1 T2 T3
519 1/1 rmask[8*i +: 8] = {8{sramreqfifo_rdata.mask[i]}};
Tests: T1 T2 T3
520 end
521 end
522 // Select correct word and mask it.
523 1/1 assign rdata_tlword = rdata_reshaped[sramreqfifo_rdata.woffset] & rmask;
Tests: T1 T2 T3
524 end
525
526 1/1 assign rspfifo_wdata = '{
Tests: T1 T2 T3
527 data : rdata_tlword[top_pkg::TL_DW-1:0],
528 data_intg : EnableDataIntgPt ? rdata_tlword[DataWidth-1 -: DataIntgWidth] : '0,
529 error : rerror_i[1] // Only care for Uncorrectable error
530 };
531 1/1 assign rspfifo_rready = (reqfifo_rdata.op == OpRead & ~reqfifo_rdata.error)
Tests: T1 T2 T3
532 ? reqfifo_rready : 1'b0 ;
533
534 // This module only cares about uncorrectable errors.
535 logic unused_rerror;
536 0/1 ==> assign unused_rerror = rerror_i[0];
537
538 // FIFO instance: REQ, RSP
539
540 // ReqFIFO is to store the Access type to match to the Response data.
541 // For instance, SRAM accepts the write request but doesn't return the
542 // acknowledge. In this case, it may be hard to determine when the D
543 // response for the write data should send out if reads/writes are
544 // interleaved. So, to make it in-order (even TL-UL allows out-of-order
545 // responses), storing the request is necessary. And if the read entry
546 // is write op, it is safe to return the response right away. If it is
547 // read reqeust, then D response is waiting until read data arrives.
548 prim_fifo_sync #(
549 .Width (ReqFifoWidth),
550 .Pass (1'b0),
551 .Depth (Outstanding),
552 .Secure (SecFifoPtr)
553 ) u_reqfifo (
554 .clk_i,
555 .rst_ni,
556 .clr_i (1'b0),
557 .wvalid_i(reqfifo_wvalid),
558 .wready_o(reqfifo_wready),
559 .wdata_i (reqfifo_wdata),
560 .rvalid_o(reqfifo_rvalid),
561 .rready_i(reqfifo_rready),
562 .rdata_o (reqfifo_rdata),
563 .full_o (),
564 .depth_o (),
565 .err_o (reqfifo_error)
566 );
567
568 // sramreqfifo:
569 // While the ReqFIFO holds the request until it is sent back via TL-UL, the
570 // sramreqfifo only needs to hold the mask and word offset until the read
571 // data returns from memory.
572 prim_fifo_sync #(
573 .Width (SramReqFifoWidth),
574 .Pass (1'b0),
575 .Depth (Outstanding),
576 .Secure (SecFifoPtr)
577 ) u_sramreqfifo (
578 .clk_i,
579 .rst_ni,
580 .clr_i (1'b0),
581 .wvalid_i(sramreqfifo_wvalid),
582 .wready_o(sramreqfifo_wready),
583 .wdata_i (sramreqfifo_wdata),
584 .rvalid_o(),
585 .rready_i(sramreqfifo_rready),
586 .rdata_o (sramreqfifo_rdata),
587 .full_o (),
588 .depth_o (),
589 .err_o (sramreqfifo_error)
590 );
591
592 // sramreqaddrfifo:
593 // This fifo holds the address used for undoing the address XOR data infection.
594 if (DataXorAddr) begin : gen_data_xor_addr_fifo
595 prim_fifo_sync #(
596 .Width (SramBusBankAW),
597 .Pass (1'b0),
598 .Depth (Outstanding),
599 .OutputZeroIfEmpty (1)
600 ) u_sramreqaddrfifo (
601 .clk_i,
602 .rst_ni,
603 .clr_i (1'b0),
604 .wvalid_i(sramreqfifo_wvalid),
605 .wready_o(sramreqaddrfifo_wready),
606 .wdata_i (sramreqaddrfifo_wdata),
607 .rvalid_o(),
608 .rready_i(sramreqfifo_rready),
609 .rdata_o (sramreqaddrfifo_rdata),
610 .full_o (),
611 .depth_o (),
612 .err_o ()
613 );
614 end else begin : gen_no_data_xor_addr_fifo
615 assign sramreqaddrfifo_wready = 1'b1;
616 assign sramreqaddrfifo_rdata = '0;
617
618 // Tie-off unused signals
619 logic unused_sramreqaddrfifo;
620 1/1 assign unused_sramreqaddrfifo = ^{sramreqaddrfifo_wdata, sramreqaddrfifo_rdata};
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_tlul2sram_ingress
| Total | Covered | Percent |
|---|
| Conditions | 106 | 87 | 82.08 |
| Logical | 106 | 87 | 82.08 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 114
EXPRESSION (readback_error | readback_error_q)
-------1------ --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Unreachable | |
LINE 131
EXPRESSION (intg_error || rsp_fifo_error || sramreqfifo_error || reqfifo_error)
-----1---- -------2------ --------3-------- ------4------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 0 | 1 | Unreachable | |
| 0 | 0 | 1 | 0 | Unreachable | |
| 0 | 1 | 0 | 0 | Unreachable | |
| 1 | 0 | 0 | 0 | Unreachable | |
LINE 138
EXPRESSION (intg_error | rsp_fifo_error | sramreqfifo_error | reqfifo_error | intg_error_q)
-----1---- -------2------ --------3-------- ------4------ ------5-----
| -1- | -2- | -3- | -4- | -5- | Status | Tests | Exclude Annotation |
|---|
| 0 | 0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 0 | 0 | 1 | Excluded | |
VC_COV_UNR |
| 0 | 0 | 0 | 1 | 0 | Unreachable | |
| 0 | 0 | 1 | 0 | 0 | Unreachable | |
| 0 | 1 | 0 | 0 | 0 | Unreachable | |
| 1 | 0 | 0 | 0 | 0 | Unreachable | |
LINE 144
EXPRESSION
Number Term
1 ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T4,T5 |
LINE 144
SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
---------------1-------------- ----------------2----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T2,T4,T5 |
| 1 | 0 | Covered | T2,T4,T5 |
LINE 144
SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
---------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T4,T5 |
LINE 144
SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T4,T5 |
LINE 144
SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
---------1--------- ----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T2,T4,T5 |
| 0 | 1 | Covered | T4,T8,T10 |
| 1 | 0 | Covered | T4,T5,T8 |
LINE 144
SUB-EXPRESSION (tl_i.a_mask != '1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T4,T5 |
| 1 | Covered | T4,T5,T8 |
LINE 144
SUB-EXPRESSION (tl_i.a_size != 2'h2)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T4,T5 |
| 1 | Covered | T4,T5,T8 |
LINE 156
EXPRESSION (tl_i.a_opcode != Get)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T4,T5 |
LINE 176
EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
------1------ ------2----- ------3----- -----4----- -----5---- -----6----
| -1- | -2- | -3- | -4- | -5- | -6- | Status | Tests | Exclude Annotation |
|---|
| 0 | 0 | 0 | 0 | 0 | 0 | Covered | T2,T8,T26 |
| 0 | 0 | 0 | 0 | 0 | 1 | Unreachable | |
| 0 | 0 | 0 | 0 | 1 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 0 | 1 | 0 | 0 | Not Covered | |
| 0 | 0 | 1 | 0 | 0 | 0 | Unreachable | |
| 0 | 1 | 0 | 0 | 0 | 0 | Not Covered | |
| 1 | 0 | 0 | 0 | 0 | 0 | Excluded | |
VC_COV_UNR |
LINE 272
EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
--------1------- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T2,T8,T26 |
| 1 | 1 | Covered | T2,T8,T26 |
LINE 273
EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
--------1------- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T8,T15 |
| 1 | 1 | Covered | T2,T8,T26 |
LINE 274
EXPRESSION (req_o & gnt_i)
--1-- --2--
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T2,T8,T26 |
LINE 285
EXPRESSION (reqfifo_rdata.op == OpRead)
--------------1-------------
| -1- | Status | Tests | Exclude Annotation |
|---|
| 0 | Excluded | |
VC_COV_UNR |
| 1 | Covered | T2,T8,T26 |
LINE 302
EXPRESSION (reqfifo_rdata.op == OpRead)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Covered | T2,T8,T26 |
LINE 303
EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
---------1--------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T8,T15,T27 |
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T2,T26,T44 |
LINE 313
EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
---1--- -------2------ -------3------ --------------4-------------
| -1- | -2- | -3- | -4- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 0 | 1 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | 1 | Covered | T2,T8,T26 |
LINE 313
SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T8,T26 |
LINE 341
EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
-------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T8,T15,T27 |
LINE 341
SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
-----1---- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T26,T44 |
| 1 | 1 | Covered | T8,T15,T27 |
LINE 347
EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
-----------------1-----------------
| -1- | Status | Tests | Exclude Annotation |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Excluded | |
VC_COV_UNR |
LINE 347
SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
-----1---- ---------2---------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T2,T8,T26 |
| 1 | 1 | Excluded | |
VC_COV_UNR |
LINE 347
SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T8,T26 |
LINE 359
EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
-------1------ --------2------- ----------3----------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T2,T8,T26 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Not Covered | |
LINE 369
EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
--------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 369
SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
---1--- --------------2-------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T8,T26 |
| 1 | 1 | Not Covered | |
LINE 369
SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 369
EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T8,T26 |
LINE 369
EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T8,T26 |
LINE 369
EXPRESSION (d_valid && d_error)
---1--- ---2---
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 0 | Covered | T8,T15,T27 |
| 1 | 1 | Covered | T2,T26,T44 |
LINE 369
EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready & sramreqaddrfifo_wready)
-------------1------------ -------2------ ---------3-------- -----------4----------
| -1- | -2- | -3- | -4- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Not Covered | |
| 1 | 1 | 0 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | 1 | Covered | T2,T8,T26 |
LINE 369
SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
--1-- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T2,T8,T26 |
LINE 390
EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
--------1------- -------2------ ---------3---------
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 0 | 1 | Covered | T2,T8,T26 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T2,T8,T26 |
LINE 392
EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
--------1------- ----------------------------2---------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T4,T5 |
| 1 | 0 | Covered | T2,T8,T26 |
| 1 | 1 | Not Covered | |
LINE 393
EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
--------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T8,T26 |
LINE 429
EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T8,T26 |
| 1 | Not Covered | |
LINE 429
SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
---------1-------- --2-
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T2,T8,T26 |
| 1 | 1 | Not Covered | |
LINE 452
EXPRESSION (((|wmask_intg)) & ((|wdata_intg)))
-------1------- -------2-------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Excluded | |
vcs_gen_start:i=0:vcs_gen_end:VC_COV_UNR |
| 1 | 0 | Covered | T28,T30,T45 |
| 1 | 1 | Covered | T2,T8,T26 |
LINE 460
EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
-------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T4,T5 |
LINE 460
SUB-EXPRESSION (tl_i_int.a_opcode != Get)
-------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T4,T5 |
LINE 474
EXPRESSION (sram_ack & ((~we_o)))
----1--- ----2----
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | Covered | T2,T8,T26 |
LINE 477
EXPRESSION (rvalid_i & reqfifo_rvalid)
----1--- -------2------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Covered | T44,T27,T29 |
| 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | Covered | T2,T8,T26 |
LINE 531
EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
----------------------------1----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T8,T26 |
LINE 531
SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
--------------1------------- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T2,T8,T26 |
LINE 531
SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T8,T26 |
Branch Coverage for Instance : tb.dut.u_tlul2sram_ingress
| Line No. | Total | Covered | Percent |
| Branches |
|
24 |
22 |
91.67 |
| TERNARY |
144 |
2 |
2 |
100.00 |
| TERNARY |
341 |
2 |
2 |
100.00 |
| TERNARY |
347 |
2 |
2 |
100.00 |
| TERNARY |
393 |
2 |
2 |
100.00 |
| TERNARY |
531 |
2 |
2 |
100.00 |
| IF |
129 |
2 |
2 |
100.00 |
| IF |
281 |
3 |
2 |
66.67 |
| IF |
301 |
3 |
2 |
66.67 |
| IF |
362 |
2 |
2 |
100.00 |
| IF |
426 |
2 |
2 |
100.00 |
| IF |
438 |
2 |
2 |
100.00 |
144 assign wr_attr_error = (tl_i.a_opcode == PutFullData || tl_i.a_opcode == PutPartialData)
145 ? ((ByteAccess == 0) ?
146 (tl_i.a_mask != '1 || tl_i.a_size != 2'h2) : 1'b0)
147 : 1'b0;
ID LINE
-1- 144 ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T4,T5 |
| 0 |
Covered |
T1,T2,T3 |
341 assign d_data = (vld_rd_rsp & ~d_error) ? rspfifo_rdata.data // valid read
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T8,T15,T27 |
| 0 |
Covered |
T1,T2,T3 |
347 assign data_intg = (vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : // TL-UL error
-1-
==> (Excluded)
348 (vld_rd_rsp) ? rspfifo_rdata.data_intg : // valid read
-2-
==>
==>
Branches:
| -1- | -2- | Status | Tests | Exclude Annotation |
| 1 |
- |
Excluded |
|
VC_COV_UNR |
| 0 |
1 |
Covered |
T2,T8,T26 |
|
| 0 |
0 |
Covered |
T1,T2,T3 |
|
393 assign addr_o = (tl_i_int.a_valid) ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T8,T26 |
| 0 |
Covered |
T1,T2,T3 |
531 assign rspfifo_rready = (reqfifo_rdata.op == OpRead & ~reqfifo_rdata.error)
532 ? reqfifo_rready : 1'b0 ;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T8,T26 |
| 0 |
Covered |
T1,T2,T3 |
129 if (!rst_ni) begin
-1-
130 intg_error_q <= '0;
==>
131 end else if (intg_error || rsp_fifo_error || sramreqfifo_error || reqfifo_error) begin
-2-
132 intg_error_q <= 1'b1;
==> (Unreachable)
133 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Unreachable |
|
| 0 |
0 |
Covered |
T1,T2,T3 |
281 if (reqfifo_rvalid) begin
-1-
282 if (reqfifo_rdata.error) begin
-2-
283 // Return error response. Assume no request went out to SRAM
284 d_valid = 1'b1;
==>
285 end else if (reqfifo_rdata.op == OpRead) begin
-3-
286 d_valid = rspfifo_rvalid;
==>
287 end else begin
288 // Write without error
289 d_valid = 1'b1;
==> (Excluded)
Exclude Annotation: VC_COV_UNR
290 end
291 end else begin
292 d_valid = 1'b0;
==>
Branches:
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
| 1 |
1 |
- |
Not Covered |
|
|
| 1 |
0 |
1 |
Covered |
T2,T8,T26 |
|
| 1 |
0 |
0 |
Excluded |
|
VC_COV_UNR |
| 0 |
- |
- |
Covered |
T1,T2,T3 |
|
301 if (reqfifo_rvalid) begin
-1-
302 if (reqfifo_rdata.op == OpRead) begin
-2-
303 d_error = rspfifo_rdata.error | reqfifo_rdata.error;
==>
304 end else begin
305 d_error = reqfifo_rdata.error;
==>
306 end
307 end else begin
308 d_error = 1'b0;
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
1 |
Covered |
T2,T8,T26 |
| 1 |
0 |
Not Covered |
|
| 0 |
- |
Covered |
T1,T2,T3 |
362 if (!rst_ni) begin
-1-
363 missed_err_gnt_q <= 1'b0;
==>
364 end else begin
365 missed_err_gnt_q <= missed_err_gnt_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
426 if (tl_i_int.a_valid) begin
-1-
427 for (int i = 0 ; i < top_pkg::TL_DW/8 ; i++) begin
==>
428 wmask_int[woffset][8*i +: 8] = {8{tl_i_int.a_mask[i]}};
429 wdata_int[woffset][8*i +: 8] = (tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[8*i+:8] : '0;
430 end
431 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T8,T26 |
| 0 |
Covered |
T1,T2,T3 |
438 if (tl_i_int.a_valid) begin
-1-
439 wmask_intg[woffset] = {DataIntgWidth{1'b1}};
==>
440 wdata_intg[woffset] = tl_i_int.a_user.data_intg;
441 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T8,T26 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_tlul2sram_ingress
Assertion Details
AddrOutKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
459421869 |
459332103 |
0 |
0 |
| T1 |
952 |
886 |
0 |
0 |
| T2 |
2418 |
2357 |
0 |
0 |
| T3 |
1718 |
1635 |
0 |
0 |
| T4 |
67232 |
67166 |
0 |
0 |
| T5 |
2198 |
2107 |
0 |
0 |
| T6 |
5598 |
4103 |
0 |
0 |
| T7 |
1923 |
1826 |
0 |
0 |
| T8 |
4287 |
4217 |
0 |
0 |
| T9 |
9735 |
9655 |
0 |
0 |
| T10 |
9668 |
9605 |
0 |
0 |
DataIntgOptions_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
976 |
976 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
ReqOutKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
459421869 |
459332103 |
0 |
0 |
| T1 |
952 |
886 |
0 |
0 |
| T2 |
2418 |
2357 |
0 |
0 |
| T3 |
1718 |
1635 |
0 |
0 |
| T4 |
67232 |
67166 |
0 |
0 |
| T5 |
2198 |
2107 |
0 |
0 |
| T6 |
5598 |
4103 |
0 |
0 |
| T7 |
1923 |
1826 |
0 |
0 |
| T8 |
4287 |
4217 |
0 |
0 |
| T9 |
9735 |
9655 |
0 |
0 |
| T10 |
9668 |
9605 |
0 |
0 |
SramDwHasByteGranularity_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
976 |
976 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
SramDwIsMultipleOfTlulWidth_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
976 |
976 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
TlOutKnownIfFifoKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
459421869 |
459332103 |
0 |
0 |
| T1 |
952 |
886 |
0 |
0 |
| T2 |
2418 |
2357 |
0 |
0 |
| T3 |
1718 |
1635 |
0 |
0 |
| T4 |
67232 |
67166 |
0 |
0 |
| T5 |
2198 |
2107 |
0 |
0 |
| T6 |
5598 |
4103 |
0 |
0 |
| T7 |
1923 |
1826 |
0 |
0 |
| T8 |
4287 |
4217 |
0 |
0 |
| T9 |
9735 |
9655 |
0 |
0 |
| T10 |
9668 |
9605 |
0 |
0 |
TlOutValidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
459421869 |
459332103 |
0 |
0 |
| T1 |
952 |
886 |
0 |
0 |
| T2 |
2418 |
2357 |
0 |
0 |
| T3 |
1718 |
1635 |
0 |
0 |
| T4 |
67232 |
67166 |
0 |
0 |
| T5 |
2198 |
2107 |
0 |
0 |
| T6 |
5598 |
4103 |
0 |
0 |
| T7 |
1923 |
1826 |
0 |
0 |
| T8 |
4287 |
4217 |
0 |
0 |
| T9 |
9735 |
9655 |
0 |
0 |
| T10 |
9668 |
9605 |
0 |
0 |
WdataOutKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
459421869 |
459332103 |
0 |
0 |
| T1 |
952 |
886 |
0 |
0 |
| T2 |
2418 |
2357 |
0 |
0 |
| T3 |
1718 |
1635 |
0 |
0 |
| T4 |
67232 |
67166 |
0 |
0 |
| T5 |
2198 |
2107 |
0 |
0 |
| T6 |
5598 |
4103 |
0 |
0 |
| T7 |
1923 |
1826 |
0 |
0 |
| T8 |
4287 |
4217 |
0 |
0 |
| T9 |
9735 |
9655 |
0 |
0 |
| T10 |
9668 |
9605 |
0 |
0 |
WeOutKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
459421869 |
459332103 |
0 |
0 |
| T1 |
952 |
886 |
0 |
0 |
| T2 |
2418 |
2357 |
0 |
0 |
| T3 |
1718 |
1635 |
0 |
0 |
| T4 |
67232 |
67166 |
0 |
0 |
| T5 |
2198 |
2107 |
0 |
0 |
| T6 |
5598 |
4103 |
0 |
0 |
| T7 |
1923 |
1826 |
0 |
0 |
| T8 |
4287 |
4217 |
0 |
0 |
| T9 |
9735 |
9655 |
0 |
0 |
| T10 |
9668 |
9605 |
0 |
0 |
WmaskOutKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
459421869 |
459332103 |
0 |
0 |
| T1 |
952 |
886 |
0 |
0 |
| T2 |
2418 |
2357 |
0 |
0 |
| T3 |
1718 |
1635 |
0 |
0 |
| T4 |
67232 |
67166 |
0 |
0 |
| T5 |
2198 |
2107 |
0 |
0 |
| T6 |
5598 |
4103 |
0 |
0 |
| T7 |
1923 |
1826 |
0 |
0 |
| T8 |
4287 |
4217 |
0 |
0 |
| T9 |
9735 |
9655 |
0 |
0 |
| T10 |
9668 |
9605 |
0 |
0 |
adapterNoReadOrWrite
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
976 |
976 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
rvalidHighReqFifoEmpty
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
459421869 |
178300 |
0 |
0 |
| T2 |
2418 |
100 |
0 |
0 |
| T3 |
1718 |
0 |
0 |
0 |
| T4 |
67232 |
0 |
0 |
0 |
| T5 |
2198 |
0 |
0 |
0 |
| T6 |
5598 |
0 |
0 |
0 |
| T7 |
1923 |
0 |
0 |
0 |
| T8 |
4287 |
52 |
0 |
0 |
| T9 |
9735 |
0 |
0 |
0 |
| T10 |
9668 |
0 |
0 |
0 |
| T11 |
42259 |
0 |
0 |
0 |
| T15 |
0 |
20 |
0 |
0 |
| T26 |
0 |
100 |
0 |
0 |
| T27 |
0 |
34 |
0 |
0 |
| T28 |
0 |
231 |
0 |
0 |
| T29 |
0 |
17 |
0 |
0 |
| T30 |
0 |
740 |
0 |
0 |
| T44 |
0 |
100 |
0 |
0 |
| T46 |
0 |
100 |
0 |
0 |
rvalidHighWhenRspFifoFull
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
459421869 |
178300 |
0 |
0 |
| T2 |
2418 |
100 |
0 |
0 |
| T3 |
1718 |
0 |
0 |
0 |
| T4 |
67232 |
0 |
0 |
0 |
| T5 |
2198 |
0 |
0 |
0 |
| T6 |
5598 |
0 |
0 |
0 |
| T7 |
1923 |
0 |
0 |
0 |
| T8 |
4287 |
52 |
0 |
0 |
| T9 |
9735 |
0 |
0 |
0 |
| T10 |
9668 |
0 |
0 |
0 |
| T11 |
42259 |
0 |
0 |
0 |
| T15 |
0 |
20 |
0 |
0 |
| T26 |
0 |
100 |
0 |
0 |
| T27 |
0 |
34 |
0 |
0 |
| T28 |
0 |
231 |
0 |
0 |
| T29 |
0 |
17 |
0 |
0 |
| T30 |
0 |
740 |
0 |
0 |
| T44 |
0 |
100 |
0 |
0 |
| T46 |
0 |
100 |
0 |
0 |