Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3594771	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4285803

1

T2

1

T3

34

T4

107

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4377436	1			T1	73		T2	1		T3	1
values[0x0]	1751791	1			T3	28		T4	55		T5	38
values[0x1]	1751347	1			T3	15		T4	45		T5	39

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2555792	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5324782

1

T1

34

T2

1

T3

36

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	30503	1			T6	3		T9	11		T10	5
valid_sources[0x01]	27810	1			T6	4		T9	4		T10	1
valid_sources[0x02]	27091	1			T6	1		T9	1		T10	1
valid_sources[0x03]	38461	1			T6	7		T9	5		T10	5
valid_sources[0x04]	26624	1			T6	2		T9	2		T10	4
valid_sources[0x05]	28323	1			T6	3		T9	4		T10	2
valid_sources[0x06]	29352	1			T12	1		T16	17		T17	4
valid_sources[0x07]	27599	1			T6	3		T9	5		T25	1
valid_sources[0x08]	28162	1			T4	3		T6	4		T9	2
valid_sources[0x09]	29954	1			T3	1		T6	4		T9	2
valid_sources[0x0a]	30573	1			T4	10		T6	2		T9	1
valid_sources[0x0b]	30118	1			T6	6		T9	4		T10	3
valid_sources[0x0c]	28639	1			T6	4		T9	5		T10	1
valid_sources[0x0d]	28448	1			T3	1		T6	6		T9	12
valid_sources[0x0e]	28583	1			T6	3		T9	3		T10	11
valid_sources[0x0f]	29808	1			T4	2		T6	2		T9	1
valid_sources[0x10]	29810	1			T4	4		T6	2		T25	2
valid_sources[0x11]	29069	1			T4	1		T6	3		T9	2
valid_sources[0x12]	29388	1			T6	1		T9	10		T10	2
valid_sources[0x13]	32861	1			T6	6		T9	8		T10	4
valid_sources[0x14]	30228	1			T6	3		T9	1		T12	6
valid_sources[0x15]	34265	1			T9	8		T25	5		T12	3
valid_sources[0x16]	32082	1			T6	1		T9	6		T10	8
valid_sources[0x17]	29225	1			T6	8		T9	4		T10	4
valid_sources[0x18]	29305	1			T6	3		T9	1		T10	3
valid_sources[0x19]	32192	1			T6	4		T9	3		T10	5
valid_sources[0x1a]	28668	1			T6	3		T9	11		T10	6
valid_sources[0x1b]	28680	1			T6	5		T10	6		T25	2
valid_sources[0x1c]	30263	1			T6	5		T9	16		T10	2
valid_sources[0x1d]	28150	1			T6	4		T9	11		T12	8
valid_sources[0x1e]	29573	1			T6	3		T9	2		T10	3
valid_sources[0x1f]	31034	1			T6	2		T9	3		T10	3
valid_sources[0x20]	29354	1			T6	4		T9	5		T10	1
valid_sources[0x21]	30291	1			T4	1		T6	1		T9	7
valid_sources[0x22]	30477	1			T6	5		T9	2		T10	6
valid_sources[0x23]	31445	1			T6	8		T9	10		T10	7
valid_sources[0x24]	32298	1			T6	7		T9	7		T10	7
valid_sources[0x25]	30184	1			T6	2		T9	15		T10	3
valid_sources[0x26]	28961	1			T4	1		T6	3		T9	4
valid_sources[0x27]	30074	1			T6	7		T9	3		T10	6
valid_sources[0x28]	32413	1			T6	4		T10	2		T25	6
valid_sources[0x29]	29740	1			T6	4		T9	2		T10	12
valid_sources[0x2a]	28006	1			T3	3		T6	6		T9	1
valid_sources[0x2b]	33920	1			T6	8		T9	1		T10	7
valid_sources[0x2c]	31560	1			T3	1		T9	7		T10	2
valid_sources[0x2d]	31058	1			T3	1		T6	1		T9	9
valid_sources[0x2e]	31539	1			T4	1		T6	3		T9	7
valid_sources[0x2f]	28748	1			T6	2		T9	7		T10	4
valid_sources[0x30]	28841	1			T4	2		T6	1		T9	2
valid_sources[0x31]	30948	1			T6	5		T9	2		T12	5
valid_sources[0x32]	35004	1			T4	1		T6	2		T9	6
valid_sources[0x33]	27641	1			T4	1		T6	9		T9	5
valid_sources[0x34]	26827	1			T6	5		T10	1		T12	4
valid_sources[0x35]	29686	1			T10	3		T25	2		T12	2
valid_sources[0x36]	30000	1			T6	5		T9	1		T10	4
valid_sources[0x37]	33359	1			T4	2		T5	293		T6	3
valid_sources[0x38]	29158	1			T4	7		T6	6		T9	3
valid_sources[0x39]	31120	1			T4	1		T6	6		T9	6
valid_sources[0x3a]	27367	1			T9	4		T10	1		T12	2
valid_sources[0x3b]	29363	1			T6	2		T9	9		T10	5
valid_sources[0x3c]	31194	1			T6	6		T9	5		T10	1
valid_sources[0x3d]	43271	1			T6	7		T9	9		T10	11
valid_sources[0x3e]	29892	1			T6	2		T9	9		T10	9
valid_sources[0x3f]	27789	1			T6	3		T12	3		T16	14
valid_sources[0x40]	24832	1			T4	1		T6	1		T9	5
valid_sources[0x41]	26642	1			T4	4		T6	3		T9	16
valid_sources[0x42]	27704	1			T6	9		T9	8		T10	13
valid_sources[0x43]	27590	1			T6	3		T9	10		T10	2
valid_sources[0x44]	30696	1			T4	9		T9	12		T16	20
valid_sources[0x45]	35857	1			T6	2		T9	13		T10	8
valid_sources[0x46]	31692	1			T4	4		T6	3		T9	7
valid_sources[0x47]	30522	1			T4	4		T6	4		T9	7
valid_sources[0x48]	29167	1			T6	2		T9	2		T10	6
valid_sources[0x49]	32419	1			T6	4		T9	8		T10	4
valid_sources[0x4a]	31893	1			T6	2		T9	5		T10	2
valid_sources[0x4b]	28924	1			T6	1		T10	3		T12	5
valid_sources[0x4c]	28442	1			T6	3		T9	4		T12	3
valid_sources[0x4d]	28244	1			T4	1		T6	2		T10	2
valid_sources[0x4e]	34518	1			T6	1		T9	6		T10	5
valid_sources[0x4f]	32183	1			T6	2		T9	3		T10	7
valid_sources[0x50]	28293	1			T6	3		T9	5		T10	6
valid_sources[0x51]	30403	1			T4	4		T6	5		T9	9
valid_sources[0x52]	28073	1			T6	4		T9	3		T10	4
valid_sources[0x53]	30074	1			T6	4		T12	2		T16	19
valid_sources[0x54]	33471	1			T6	7		T12	3		T16	19
valid_sources[0x55]	29235	1			T6	3		T9	16		T12	4
valid_sources[0x56]	26260	1			T3	4		T6	3		T9	7
valid_sources[0x57]	31543	1			T6	11		T9	2		T10	8
valid_sources[0x58]	45041	1			T6	4		T9	11		T10	7
valid_sources[0x59]	30720	1			T6	6		T9	2		T10	1
valid_sources[0x5a]	37506	1			T6	2		T9	1		T12	2
valid_sources[0x5b]	32484	1			T4	2		T10	4		T12	2
valid_sources[0x5c]	35274	1			T3	2		T6	3		T9	2
valid_sources[0x5d]	28871	1			T6	4		T9	2		T10	6
valid_sources[0x5e]	29127	1			T6	5		T9	4		T10	3
valid_sources[0x5f]	32065	1			T3	1		T6	3		T9	1
valid_sources[0x60]	38422	1			T6	4		T9	15		T12	1
valid_sources[0x61]	30728	1			T6	6		T9	7		T25	9
valid_sources[0x62]	31106	1			T6	3		T9	5		T10	2
valid_sources[0x63]	29750	1			T6	5		T9	9		T10	5
valid_sources[0x64]	32863	1			T6	1		T10	1		T25	2
valid_sources[0x65]	35380	1			T6	4		T9	7		T12	6
valid_sources[0x66]	30369	1			T9	12		T10	1		T12	3
valid_sources[0x67]	27498	1			T6	7		T9	17		T10	3
valid_sources[0x68]	27822	1			T6	1		T9	24		T25	3
valid_sources[0x69]	31948	1			T6	2		T9	9		T10	1
valid_sources[0x6a]	28080	1			T6	2		T9	4		T10	4
valid_sources[0x6b]	29410	1			T6	3		T9	3		T10	2
valid_sources[0x6c]	30655	1			T6	4		T9	2		T10	5
valid_sources[0x6d]	29543	1			T6	3		T10	3		T25	2
valid_sources[0x6e]	28132	1			T4	6		T6	4		T9	6
valid_sources[0x6f]	26840	1			T6	4		T9	1		T10	5
valid_sources[0x70]	29822	1			T4	2		T6	5		T9	5
valid_sources[0x71]	30219	1			T6	1		T9	20		T10	4
valid_sources[0x72]	32465	1			T3	3		T6	1		T9	1
valid_sources[0x73]	32984	1			T4	3		T6	3		T9	16
valid_sources[0x74]	29492	1			T4	2		T6	2		T9	7
valid_sources[0x75]	26221	1			T10	2		T12	3		T16	8
valid_sources[0x76]	31692	1			T6	7		T9	4		T12	6
valid_sources[0x77]	28747	1			T3	1		T6	1		T9	8
valid_sources[0x78]	34799	1			T6	4		T9	12		T10	5
valid_sources[0x79]	29000	1			T4	3		T6	4		T10	3
valid_sources[0x7a]	30267	1			T6	3		T9	6		T10	6
valid_sources[0x7b]	30471	1			T6	2		T9	11		T12	2
valid_sources[0x7c]	27693	1			T6	5		T9	3		T25	2
valid_sources[0x7d]	32094	1			T4	1		T6	4		T9	8
valid_sources[0x7e]	27374	1			T6	9		T9	5		T10	1
valid_sources[0x7f]	39880	1			T3	2		T6	3		T9	5
valid_sources[0x80]	28233	1			T6	2		T9	3		T10	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1099984

1

T2

1

T4

7

T5

36

values[0x0]

all_enables

biggest_size

1604622

1

T3

24

T4

55

T5

25

values[0x1]

all_enables

biggest_size

1581197

1

T3

10

T4

45

T5

23