Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3244577	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3967935

1

T1

1

T2

1

T3

111

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3886808	1			T1	63		T2	1		T3	101
values[0x0]	1661650	1			T3	54		T4	21		T5	26
values[0x1]	1664054	1			T3	46		T4	22		T5	29

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2301620	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4910892

1

T1

23

T2

1

T3

170

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27934	1			T3	1		T6	4		T11	2
valid_sources[0x01]	26508	1			T3	1		T5	1		T15	1
valid_sources[0x02]	28565	1			T1	1		T3	1		T11	1
valid_sources[0x03]	26704	1			T5	1		T7	1		T15	1
valid_sources[0x04]	28246	1			T3	1		T11	2		T15	5
valid_sources[0x05]	25783	1			T3	2		T7	1		T8	1
valid_sources[0x06]	27614	1			T5	3		T8	1		T11	1
valid_sources[0x07]	27261	1			T1	1		T3	1		T8	1
valid_sources[0x08]	28393	1			T1	5		T8	2		T15	1
valid_sources[0x09]	27208	1			T3	1		T5	1		T11	5
valid_sources[0x0a]	26695	1			T1	1		T3	3		T7	1
valid_sources[0x0b]	29037	1			T1	1		T8	1		T11	2
valid_sources[0x0c]	29531	1			T8	1		T11	4		T15	1
valid_sources[0x0d]	35818	1			T1	1		T5	2		T8	1
valid_sources[0x0e]	33778	1			T3	1		T11	1		T15	3
valid_sources[0x0f]	24752	1			T7	1		T11	7		T15	3
valid_sources[0x10]	24979	1			T1	1		T3	2		T11	2
valid_sources[0x11]	31602	1			T3	3		T11	1		T15	11
valid_sources[0x12]	26158	1			T3	2		T11	6		T15	8
valid_sources[0x13]	24755	1			T3	2		T5	1		T11	6
valid_sources[0x14]	28716	1			T5	3		T7	1		T8	1
valid_sources[0x15]	28858	1			T3	2		T5	1		T11	8
valid_sources[0x16]	27315	1			T1	1		T5	1		T8	1
valid_sources[0x17]	31499	1			T3	1		T8	1		T11	11
valid_sources[0x18]	26617	1			T3	1		T5	2		T11	4
valid_sources[0x19]	26479	1			T3	1		T8	2		T11	2
valid_sources[0x1a]	26419	1			T5	1		T8	1		T11	3
valid_sources[0x1b]	29195	1			T3	3		T8	1		T11	3
valid_sources[0x1c]	28231	1			T3	1		T11	3		T15	3
valid_sources[0x1d]	31556	1			T3	1		T5	1		T7	1
valid_sources[0x1e]	29957	1			T3	1		T8	3		T11	5
valid_sources[0x1f]	28088	1			T3	2		T11	5		T15	9
valid_sources[0x20]	33558	1			T3	1		T7	1		T8	2
valid_sources[0x21]	31204	1			T8	4		T11	2		T15	1
valid_sources[0x22]	27062	1			T8	2		T11	3		T15	1
valid_sources[0x23]	26405	1			T3	3		T7	1		T11	3
valid_sources[0x24]	28058	1			T8	1		T11	2		T16	7
valid_sources[0x25]	28398	1			T1	5		T3	2		T5	1
valid_sources[0x26]	34427	1			T11	8		T15	7		T17	3
valid_sources[0x27]	25092	1			T11	8		T15	2		T16	4
valid_sources[0x28]	27016	1			T1	3		T3	1		T7	1
valid_sources[0x29]	29857	1			T5	2		T11	1		T15	5
valid_sources[0x2a]	26740	1			T5	2		T11	4		T15	15
valid_sources[0x2b]	24320	1			T3	1		T8	1		T11	5
valid_sources[0x2c]	26059	1			T7	2		T8	5		T11	5
valid_sources[0x2d]	29044	1			T1	1		T7	2		T11	2
valid_sources[0x2e]	26962	1			T3	2		T5	1		T8	2
valid_sources[0x2f]	29804	1			T5	5		T8	1		T11	6
valid_sources[0x30]	29692	1			T3	1		T8	2		T11	7
valid_sources[0x31]	26308	1			T5	2		T8	3		T11	8
valid_sources[0x32]	26075	1			T8	1		T11	4		T15	12
valid_sources[0x33]	25846	1			T11	8		T15	12		T16	9
valid_sources[0x34]	30749	1			T3	3		T5	1		T11	2
valid_sources[0x35]	31226	1			T3	1		T11	1		T15	9
valid_sources[0x36]	29482	1			T1	1		T3	1		T11	8
valid_sources[0x37]	25361	1			T3	1		T5	2		T8	1
valid_sources[0x38]	32961	1			T11	2		T15	5		T17	4
valid_sources[0x39]	25263	1			T1	1		T3	1		T8	3
valid_sources[0x3a]	30161	1			T3	2		T11	7		T15	9
valid_sources[0x3b]	27522	1			T3	1		T11	3		T15	3
valid_sources[0x3c]	26923	1			T7	1		T11	3		T15	3
valid_sources[0x3d]	25735	1			T5	2		T8	1		T11	1
valid_sources[0x3e]	27835	1			T8	1		T11	1		T15	6
valid_sources[0x3f]	26732	1			T3	1		T8	1		T15	2
valid_sources[0x40]	26111	1			T3	1		T8	1		T15	5
valid_sources[0x41]	29120	1			T5	1		T8	1		T11	4
valid_sources[0x42]	27533	1			T3	2		T8	1		T11	5
valid_sources[0x43]	28480	1			T7	1		T8	2		T15	2
valid_sources[0x44]	34699	1			T1	2		T3	1		T5	4
valid_sources[0x45]	26424	1			T3	1		T5	8		T8	1
valid_sources[0x46]	26238	1			T3	1		T6	2		T7	1
valid_sources[0x47]	28880	1			T5	1		T8	1		T11	3
valid_sources[0x48]	26152	1			T5	2		T8	2		T11	3
valid_sources[0x49]	28460	1			T1	1		T5	1		T7	1
valid_sources[0x4a]	28351	1			T8	3		T15	2		T16	5
valid_sources[0x4b]	26484	1			T3	1		T11	3		T15	4
valid_sources[0x4c]	26761	1			T1	1		T3	2		T4	4
valid_sources[0x4d]	25715	1			T3	2		T8	2		T11	2
valid_sources[0x4e]	49593	1			T7	1		T11	1		T15	2
valid_sources[0x4f]	25923	1			T8	2		T11	2		T15	12
valid_sources[0x50]	29885	1			T11	3		T15	2		T16	3
valid_sources[0x51]	30042	1			T15	4		T16	10		T17	2
valid_sources[0x52]	27593	1			T5	2		T7	1		T8	3
valid_sources[0x53]	25633	1			T7	1		T8	1		T11	6
valid_sources[0x54]	25743	1			T5	2		T7	1		T11	5
valid_sources[0x55]	26458	1			T11	3		T15	4		T17	4
valid_sources[0x56]	27324	1			T4	14		T15	3		T17	1
valid_sources[0x57]	27784	1			T1	1		T11	4		T15	9
valid_sources[0x58]	27382	1			T3	1		T11	3		T15	9
valid_sources[0x59]	26302	1			T4	2		T11	2		T15	3
valid_sources[0x5a]	29299	1			T5	2		T11	3		T15	10
valid_sources[0x5b]	27516	1			T1	2		T5	1		T11	4
valid_sources[0x5c]	26105	1			T7	1		T8	1		T11	6
valid_sources[0x5d]	27415	1			T8	1		T11	4		T15	9
valid_sources[0x5e]	27580	1			T3	2		T8	2		T11	8
valid_sources[0x5f]	26032	1			T3	3		T5	2		T15	6
valid_sources[0x60]	28592	1			T8	1		T11	2		T16	9
valid_sources[0x61]	32299	1			T3	1		T11	3		T15	4
valid_sources[0x62]	26380	1			T3	1		T8	1		T11	2
valid_sources[0x63]	30967	1			T11	3		T16	4		T17	3
valid_sources[0x64]	26262	1			T1	1		T11	5		T15	9
valid_sources[0x65]	24860	1			T5	1		T7	1		T11	9
valid_sources[0x66]	25771	1			T3	1		T5	1		T8	1
valid_sources[0x67]	26113	1			T11	3		T15	11		T16	14
valid_sources[0x68]	29754	1			T5	2		T11	2		T15	8
valid_sources[0x69]	27861	1			T5	2		T8	1		T11	5
valid_sources[0x6a]	33466	1			T15	9		T16	1		T17	11
valid_sources[0x6b]	25155	1			T3	1		T5	2		T8	2
valid_sources[0x6c]	27261	1			T3	2		T5	3		T8	1
valid_sources[0x6d]	27314	1			T3	1		T7	1		T15	5
valid_sources[0x6e]	27075	1			T3	1		T5	9		T8	2
valid_sources[0x6f]	25652	1			T1	1		T3	2		T5	2
valid_sources[0x70]	26152	1			T1	3		T3	1		T11	2
valid_sources[0x71]	26373	1			T2	1		T3	2		T11	7
valid_sources[0x72]	27404	1			T3	1		T8	2		T11	11
valid_sources[0x73]	28391	1			T3	1		T8	1		T11	1
valid_sources[0x74]	29767	1			T7	1		T8	1		T15	2
valid_sources[0x75]	28348	1			T3	1		T5	1		T11	5
valid_sources[0x76]	30092	1			T11	2		T15	2		T16	3
valid_sources[0x77]	25987	1			T1	1		T3	2		T7	1
valid_sources[0x78]	25164	1			T1	1		T3	2		T5	1
valid_sources[0x79]	28937	1			T1	1		T3	2		T11	2
valid_sources[0x7a]	27770	1			T1	1		T3	1		T5	5
valid_sources[0x7b]	25189	1			T3	4		T8	1		T11	4
valid_sources[0x7c]	28053	1			T3	1		T5	1		T8	1
valid_sources[0x7d]	28944	1			T3	2		T5	3		T7	1
valid_sources[0x7e]	26805	1			T3	1		T8	1		T15	3
valid_sources[0x7f]	24909	1			T5	5		T11	3		T15	4
valid_sources[0x80]	28652	1			T3	1		T7	1		T8	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

946259

1

T1

1

T2

1

T3

11

values[0x0]

all_enables

biggest_size

1521413

1

T3

54

T4

17

T5

7

values[0x1]

all_enables

biggest_size

1500263

1

T3

46

T4

19

T5

6