Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3266020

1

T1

62

T4

7

T5

129

full_word

3967030

1

T1

1

T2

1

T4

37

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7232560	1			T1	63		T2	1		T4	44
auto[TlIntgErrCmd]	151	1			T122	3		T123	11		T124	8
auto[TlIntgErrData]	162	1			T122	13		T123	7		T124	9
auto[TlIntgErrBoth]	177	1			T122	4		T123	12		T124	13

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3890175

1

T1

63

T2

1

T4

1

auto[1]

3342875

1

T4

43

T5

55

T6

16

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	2943511	1			T1	62		T5	87		T7	63
auto[TlIntgErrNone]	partial	auto[1]	322067	1			T4	7		T5	42		T6	15
auto[TlIntgErrNone]	full_word	auto[0]	946443	1			T1	1		T2	1		T4	1
auto[TlIntgErrNone]	full_word	auto[1]	3020539	1			T4	36		T5	13		T6	1
auto[TlIntgErrCmd]	partial	auto[0]	66	1			T122	2		T123	6		T124	7
auto[TlIntgErrCmd]	partial	auto[1]	76	1			T122	1		T123	4		T124	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T123	1		T180	1		T218	2
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T180	1		T217	1		T219	1
auto[TlIntgErrData]	partial	auto[0]	73	1			T122	5		T123	4		T124	5
auto[TlIntgErrData]	partial	auto[1]	66	1			T122	7		T123	2		T124	3
auto[TlIntgErrData]	full_word	auto[0]	8	1			T122	1		T123	1		T220	1
auto[TlIntgErrData]	full_word	auto[1]	15	1			T124	1		T180	2		T220	2
auto[TlIntgErrBoth]	partial	auto[0]	62	1			T122	2		T123	5		T124	3
auto[TlIntgErrBoth]	partial	auto[1]	99	1			T122	2		T123	7		T124	8
auto[TlIntgErrBoth]	full_word	auto[0]	8	1			T124	2		T220	1		T221	2
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T180	1		T216	2		T222	1