Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3609973

1

T1

73

T3

10

T5

209

full_word

4284644

1

T2

1

T3

34

T5

84

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7894307	1			T1	73		T2	1		T3	44
auto[TlIntgErrCmd]	117	1			T117	4		T118	3		T119	9
auto[TlIntgErrData]	94	1			T117	1		T118	3		T119	9
auto[TlIntgErrBoth]	99	1			T117	5		T118	4		T119	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4378650

1

T1

73

T2

1

T3

1

auto[1]

3515967

1

T3

43

T5

77

T6

885

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3278474	1			T1	73		T3	1		T5	180
auto[TlIntgErrNone]	partial	auto[1]	331219	1			T3	9		T5	29		T6	2
auto[TlIntgErrNone]	full_word	auto[0]	1100046	1			T2	1		T5	36		T6	7
auto[TlIntgErrNone]	full_word	auto[1]	3184568	1			T3	34		T5	48		T6	883
auto[TlIntgErrCmd]	partial	auto[0]	44	1			T117	2		T118	1		T119	3
auto[TlIntgErrCmd]	partial	auto[1]	64	1			T117	1		T118	1		T119	6
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T117	1		T284	1		T281	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T118	1		T281	1		T288	1
auto[TlIntgErrData]	partial	auto[0]	40	1			T118	1		T119	7		T284	4
auto[TlIntgErrData]	partial	auto[1]	44	1			T117	1		T118	1		T119	1
auto[TlIntgErrData]	full_word	auto[0]	3	1			T118	1		T119	1		T289	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T287	1		T286	2		T290	1
auto[TlIntgErrBoth]	partial	auto[0]	34	1			T117	2		T118	1		T119	2
auto[TlIntgErrBoth]	partial	auto[1]	54	1			T117	3		T118	3		T284	3
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T285	2		T281	1		T282	2
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T284	1		T291	1		T292	1