Line Coverage for Module :
prim_ram_2p_async_adv
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 51 | 51 | 100.00 |
| ALWAYS | 136 | 3 | 3 | 100.00 |
| ALWAYS | 143 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 152 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 153 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 154 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
| ALWAYS | 233 | 15 | 15 | 100.00 |
| CONT_ASSIGN | 267 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 268 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 307 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 308 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 309 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 310 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 311 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 313 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 314 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 315 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 316 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 317 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 347 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 348 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 350 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 352 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 353 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 355 | 1 | 1 | 100.00 |
135 always_ff @(posedge clk_a_i or negedge rst_a_ni) begin
136 1/1 if (!rst_a_ni) begin
Tests: T1 T2 T3
137 1/1 a_rvalid_sram_q <= 1'b0;
Tests: T1 T2 T3
138 end else begin
139 1/1 a_rvalid_sram_q <= a_req_q & ~a_write_q;
Tests: T1 T2 T3
140 end
141 end
142 always_ff @(posedge clk_b_i or negedge rst_b_ni) begin
143 1/1 if (!rst_b_ni) begin
Tests: T1 T2 T3
144 1/1 b_rvalid_sram_q <= 1'b0;
Tests: T1 T2 T3
145 end else begin
146 1/1 b_rvalid_sram_q <= b_req_q & ~b_write_q;
Tests: T3 T5 T6
147 end
148 end
149
150 1/1 assign a_req_d = a_req_i;
Tests: T1 T2 T3
151 1/1 assign a_write_d = a_write_i;
Tests: T1 T2 T3
152 1/1 assign a_addr_d = a_addr_i;
Tests: T1 T2 T3
153 1/1 assign a_rvalid_o = a_rvalid_q;
Tests: T1 T2 T3
154 1/1 assign a_rdata_o = a_rdata_q;
Tests: T4 T5 T25
155 1/1 assign a_rerror_o = a_rerror_q;
Tests: T1 T2 T3
156
157 1/1 assign b_req_d = b_req_i;
Tests: T1 T2 T3
158 1/1 assign b_write_d = b_write_i;
Tests: T1 T2 T3
159 1/1 assign b_addr_d = b_addr_i;
Tests: T1 T2 T3
160 1/1 assign b_rvalid_o = b_rvalid_q;
Tests: T1 T2 T3
161 1/1 assign b_rdata_o = b_rdata_q;
Tests: T5 T12 T14
162 1/1 assign b_rerror_o = b_rerror_q;
Tests: T1 T2 T3
163
164 /////////////////////////////
165 // ECC / Parity Generation //
166 /////////////////////////////
167
168 if (EnableParity == 0 && EnableECC) begin : gen_secded
169
170 // check supported widths
171 `ASSERT_INIT(SecDecWidth_A, Width inside {32})
172
173 // the wmask is constantly set to 1 in this case
174 `ASSERT(OnlyWordWritePossibleWithEccPortA_A, a_req_i |->
175 a_wmask_i == {Width{1'b1}}, clk_a_i, rst_a_ni)
176 `ASSERT(OnlyWordWritePossibleWithEccPortB_A, b_req_i |->
177 b_wmask_i == {Width{1'b1}}, clk_b_i, rst_b_ni)
178
179 assign a_wmask_d = {TotalWidth{1'b1}};
180 assign b_wmask_d = {TotalWidth{1'b1}};
181
182 if (Width == 32) begin : gen_secded_39_32
183 if (HammingECC) begin : gen_hamming
184 prim_secded_inv_hamming_39_32_enc u_enc_a (
185 .data_i(a_wdata_i),
186 .data_o(a_wdata_d)
187 );
188 prim_secded_inv_hamming_39_32_dec u_dec_a (
189 .data_i (a_rdata_sram),
190 .data_o (a_rdata_d[0+:Width]),
191 .syndrome_o ( ),
192 .err_o (a_rerror_d)
193 );
194 prim_secded_inv_hamming_39_32_enc u_enc_b (
195 .data_i(b_wdata_i),
196 .data_o(b_wdata_d)
197 );
198 prim_secded_inv_hamming_39_32_dec u_dec_b (
199 .data_i (b_rdata_sram),
200 .data_o (b_rdata_d[0+:Width]),
201 .syndrome_o ( ),
202 .err_o (b_rerror_d)
203 );
204 end else begin : gen_hsiao
205 prim_secded_inv_39_32_enc u_enc_a (
206 .data_i(a_wdata_i),
207 .data_o(a_wdata_d)
208 );
209 prim_secded_inv_39_32_dec u_dec_a (
210 .data_i (a_rdata_sram),
211 .data_o (a_rdata_d[0+:Width]),
212 .syndrome_o ( ),
213 .err_o (a_rerror_d)
214 );
215 prim_secded_inv_39_32_enc u_enc_b (
216 .data_i(b_wdata_i),
217 .data_o(b_wdata_d)
218 );
219 prim_secded_inv_39_32_dec u_dec_b (
220 .data_i (b_rdata_sram),
221 .data_o (b_rdata_d[0+:Width]),
222 .syndrome_o ( ),
223 .err_o (b_rerror_d)
224 );
225 end
226 end
227 end else if (EnableParity) begin : gen_byte_parity
228
229 `ASSERT_INIT(ParityNeedsByteWriteMask_A, DataBitsPerMask == 8)
230 `ASSERT_INIT(WidthNeedsToBeByteAligned_A, Width % 8 == 0)
231
232 always_comb begin : p_parity
233 1/1 a_rerror_d = '0;
Tests: T1 T2 T3
234 1/1 b_rerror_d = '0;
Tests: T1 T2 T3
235 1/1 for (int i = 0; i < Width/8; i ++) begin
Tests: T1 T2 T3
236 // Data mapping. We have to make 8+1 = 9 bit groups
237 // that have the same write enable such that FPGA tools
238 // can map this correctly to BRAM resources.
239 1/1 a_wmask_d[i*9 +: 8] = a_wmask_i[i*8 +: 8];
Tests: T1 T2 T3
240 1/1 a_wdata_d[i*9 +: 8] = a_wdata_i[i*8 +: 8];
Tests: T1 T2 T3
241 1/1 a_rdata_d[i*8 +: 8] = a_rdata_sram[i*9 +: 8];
Tests: T1 T2 T3
242 1/1 b_wmask_d[i*9 +: 8] = b_wmask_i[i*8 +: 8];
Tests: T1 T2 T3
243 1/1 b_wdata_d[i*9 +: 8] = b_wdata_i[i*8 +: 8];
Tests: T1 T2 T3
244 1/1 b_rdata_d[i*8 +: 8] = b_rdata_sram[i*9 +: 8];
Tests: T1 T2 T3
245
246 // parity generation (odd parity)
247 1/1 a_wdata_d[i*9 + 8] = ~(^a_wdata_i[i*8 +: 8]);
Tests: T1 T2 T3
248 1/1 a_wmask_d[i*9 + 8] = &a_wmask_i[i*8 +: 8];
Tests: T1 T2 T3
249 1/1 b_wdata_d[i*9 + 8] = ~(^b_wdata_i[i*8 +: 8]);
Tests: T1 T2 T3
250 1/1 b_wmask_d[i*9 + 8] = &b_wmask_i[i*8 +: 8];
Tests: T1 T2 T3
251 // parity decoding (errors are always uncorrectable)
252 1/1 a_rerror_d[1] |= ~(^{a_rdata_sram[i*9 +: 8], a_rdata_sram[i*9 + 8]});
Tests: T1 T2 T3
253 1/1 b_rerror_d[1] |= ~(^{b_rdata_sram[i*9 +: 8], b_rdata_sram[i*9 + 8]});
Tests: T1 T2 T3
254 end
255 end
256 end else begin : gen_nosecded_noparity
257 assign a_wmask_d = a_wmask_i;
258 assign b_wmask_d = b_wmask_i;
259 assign a_wdata_d = a_wdata_i;
260 assign b_wdata_d = b_wdata_i;
261 assign a_rdata_d = a_rdata_sram[0+:Width];
262 assign b_rdata_d = b_rdata_sram[0+:Width];
263 assign a_rerror_d = '0;
264 assign b_rerror_d = '0;
265 end
266
267 1/1 assign a_rvalid_d = a_rvalid_sram_q;
Tests: T1 T2 T3
268 1/1 assign b_rvalid_d = b_rvalid_sram_q;
Tests: T1 T2 T3
269
270 /////////////////////////////////////
271 // Input/Output Pipeline Registers //
272 /////////////////////////////////////
273
274 if (EnableInputPipeline) begin : gen_regslice_input
275 // Put the register slices between ECC encoding to SRAM port
276 always_ff @(posedge clk_a_i or negedge rst_a_ni) begin
277 if (!rst_a_ni) begin
278 a_req_q <= '0;
279 a_write_q <= '0;
280 a_addr_q <= '0;
281 a_wdata_q <= '0;
282 a_wmask_q <= '0;
283 end else begin
284 a_req_q <= a_req_d;
285 a_write_q <= a_write_d;
286 a_addr_q <= a_addr_d;
287 a_wdata_q <= a_wdata_d;
288 a_wmask_q <= a_wmask_d;
289 end
290 end
291 always_ff @(posedge clk_b_i or negedge rst_b_ni) begin
292 if (!rst_b_ni) begin
293 b_req_q <= '0;
294 b_write_q <= '0;
295 b_addr_q <= '0;
296 b_wdata_q <= '0;
297 b_wmask_q <= '0;
298 end else begin
299 b_req_q <= b_req_d;
300 b_write_q <= b_write_d;
301 b_addr_q <= b_addr_d;
302 b_wdata_q <= b_wdata_d;
303 b_wmask_q <= b_wmask_d;
304 end
305 end
306 end else begin : gen_dirconnect_input
307 1/1 assign a_req_q = a_req_d;
Tests: T1 T2 T3
308 1/1 assign a_write_q = a_write_d;
Tests: T1 T2 T3
309 1/1 assign a_addr_q = a_addr_d;
Tests: T1 T2 T3
310 1/1 assign a_wdata_q = a_wdata_d;
Tests: T1 T2 T3
311 1/1 assign a_wmask_q = a_wmask_d;
Tests: T1 T2 T3
312
313 1/1 assign b_req_q = b_req_d;
Tests: T1 T2 T3
314 1/1 assign b_write_q = b_write_d;
Tests: T1 T2 T3
315 1/1 assign b_addr_q = b_addr_d;
Tests: T1 T2 T3
316 1/1 assign b_wdata_q = b_wdata_d;
Tests: T1 T2 T3
317 1/1 assign b_wmask_q = b_wmask_d;
Tests: T1 T2 T3
318 end
319
320 if (EnableOutputPipeline) begin : gen_regslice_output
321 // Put the register slices between ECC decoding to output
322 always_ff @(posedge clk_a_i or negedge rst_a_ni) begin
323 if (!rst_a_ni) begin
324 a_rvalid_q <= '0;
325 a_rdata_q <= '0;
326 a_rerror_q <= '0;
327 end else begin
328 a_rvalid_q <= a_rvalid_d;
329 a_rdata_q <= a_rdata_d;
330 // tie to zero if the read data is not valid
331 a_rerror_q <= a_rerror_d & {2{a_rvalid_d}};
332 end
333 end
334 always_ff @(posedge clk_b_i or negedge rst_b_ni) begin
335 if (!rst_b_ni) begin
336 b_rvalid_q <= '0;
337 b_rdata_q <= '0;
338 b_rerror_q <= '0;
339 end else begin
340 b_rvalid_q <= b_rvalid_d;
341 b_rdata_q <= b_rdata_d;
342 // tie to zero if the read data is not valid
343 b_rerror_q <= b_rerror_d & {2{b_rvalid_d}};
344 end
345 end
346 end else begin : gen_dirconnect_output
347 1/1 assign a_rvalid_q = a_rvalid_d;
Tests: T1 T2 T3
348 1/1 assign a_rdata_q = a_rdata_d;
Tests: T4 T5 T25
349 // tie to zero if the read data is not valid
350 1/1 assign a_rerror_q = a_rerror_d & {2{a_rvalid_d}};
Tests: T1 T2 T3
351
352 1/1 assign b_rvalid_q = b_rvalid_d;
Tests: T1 T2 T3
353 1/1 assign b_rdata_q = b_rdata_d;
Tests: T5 T12 T14
354 // tie to zero if the read data is not valid
355 1/1 assign b_rerror_q = b_rerror_d & {2{b_rvalid_d}};
Tests: T1 T2 T3
Cond Coverage for Module :
prim_ram_2p_async_adv
| Total | Covered | Percent |
|---|
| Conditions | 6 | 6 | 100.00 |
| Logical | 6 | 6 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 139
EXPRESSION (a_req_q & ((~a_write_q)))
---1--- -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T5,T6 |
| 1 | 1 | Covered | T4,T5,T25 |
LINE 146
EXPRESSION (b_req_q & ((~b_write_q)))
---1--- -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T3,T5,T6 |
| 1 | 0 | Covered | T5,T20,T29 |
| 1 | 1 | Covered | T5,T12,T14 |
Branch Coverage for Module :
prim_ram_2p_async_adv
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
136 |
2 |
2 |
100.00 |
| IF |
143 |
2 |
2 |
100.00 |
136 if (!rst_a_ni) begin
-1-
137 a_rvalid_sram_q <= 1'b0;
==>
138 end else begin
139 a_rvalid_sram_q <= a_req_q & ~a_write_q;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
143 if (!rst_b_ni) begin
-1-
144 b_rvalid_sram_q <= 1'b0;
==>
145 end else begin
146 b_rvalid_sram_q <= b_req_q & ~b_write_q;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T3,T5,T6 |
Assert Coverage for Module :
prim_ram_2p_async_adv
Assertion Details
CannotHaveEccAndParity_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
976 |
976 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
gen_byte_parity.ParityNeedsByteWriteMask_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
976 |
976 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
gen_byte_parity.WidthNeedsToBeByteAligned_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
976 |
976 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
