Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	421735679	2799879	0	0
DepthKnown_A	421735679	421597267	0	0
RvalidKnown_A	421735679	421597267	0	0
WreadyKnown_A	421735679	421597267	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421735679	2799879	0	0
T3	2704	100	0	0
T4	12731	0	0	0
T5	3176	0	0	0
T6	1218	0	0	0
T7	1561	0	0	0
T8	1033	100	0	0
T9	6001	0	0	0
T10	706	0	0	0
T11	97922	1668	0	0
T12	15980	832	0	0
T14	0	832	0	0
T15	0	1663	0	0
T16	0	832	0	0
T17	0	832	0	0
T18	0	1668	0	0
T21	0	1668	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421735679	421597267	0	0
T1	1375	1284	0	0
T2	951	889	0	0
T3	2704	2634	0	0
T4	12731	12634	0	0
T5	3176	3094	0	0
T6	1218	1129	0	0
T7	1561	1484	0	0
T8	1033	937	0	0
T9	6001	4498	0	0
T10	706	644	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421735679	421597267	0	0
T1	1375	1284	0	0
T2	951	889	0	0
T3	2704	2634	0	0
T4	12731	12634	0	0
T5	3176	3094	0	0
T6	1218	1129	0	0
T7	1561	1484	0	0
T8	1033	937	0	0
T9	6001	4498	0	0
T10	706	644	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421735679	421597267	0	0
T1	1375	1284	0	0
T2	951	889	0	0
T3	2704	2634	0	0
T4	12731	12634	0	0
T5	3176	3094	0	0
T6	1218	1129	0	0
T7	1561	1484	0	0
T8	1033	937	0	0
T9	6001	4498	0	0
T10	706	644	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	421735679	3185241	0	0
DepthKnown_A	421735679	421597267	0	0
RvalidKnown_A	421735679	421597267	0	0
WreadyKnown_A	421735679	421597267	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421735679	3185241	0	0
T3	2704	345	0	0
T4	12731	0	0	0
T5	3176	0	0	0
T6	1218	0	0	0
T7	1561	0	0	0
T8	1033	100	0	0
T9	6001	0	0	0
T10	706	0	0	0
T11	97922	837	0	0
T12	15980	832	0	0
T14	0	832	0	0
T15	0	832	0	0
T16	0	832	0	0
T17	0	832	0	0
T18	0	839	0	0
T21	0	837	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421735679	421597267	0	0
T1	1375	1284	0	0
T2	951	889	0	0
T3	2704	2634	0	0
T4	12731	12634	0	0
T5	3176	3094	0	0
T6	1218	1129	0	0
T7	1561	1484	0	0
T8	1033	937	0	0
T9	6001	4498	0	0
T10	706	644	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421735679	421597267	0	0
T1	1375	1284	0	0
T2	951	889	0	0
T3	2704	2634	0	0
T4	12731	12634	0	0
T5	3176	3094	0	0
T6	1218	1129	0	0
T7	1561	1484	0	0
T8	1033	937	0	0
T9	6001	4498	0	0
T10	706	644	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421735679	421597267	0	0
T1	1375	1284	0	0
T2	951	889	0	0
T3	2704	2634	0	0
T4	12731	12634	0	0
T5	3176	3094	0	0
T6	1218	1129	0	0
T7	1561	1484	0	0
T8	1033	937	0	0
T9	6001	4498	0	0
T10	706	644	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	421735679	188944	0	0
DepthKnown_A	421735679	421597267	0	0
RvalidKnown_A	421735679	421597267	0	0
WreadyKnown_A	421735679	421597267	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421735679	188944	0	0
T3	2704	100	0	0
T4	12731	0	0	0
T5	3176	40	0	0
T6	1218	0	0	0
T7	1561	0	0	0
T8	1033	100	0	0
T9	6001	0	0	0
T10	706	0	0	0
T11	97922	0	0	0
T12	15980	0	0	0
T13	0	5	0	0
T30	0	318	0	0
T31	0	1	0	0
T34	0	96	0	0
T45	0	100	0	0
T47	0	100	0	0
T48	0	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421735679	421597267	0	0
T1	1375	1284	0	0
T2	951	889	0	0
T3	2704	2634	0	0
T4	12731	12634	0	0
T5	3176	3094	0	0
T6	1218	1129	0	0
T7	1561	1484	0	0
T8	1033	937	0	0
T9	6001	4498	0	0
T10	706	644	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421735679	421597267	0	0
T1	1375	1284	0	0
T2	951	889	0	0
T3	2704	2634	0	0
T4	12731	12634	0	0
T5	3176	3094	0	0
T6	1218	1129	0	0
T7	1561	1484	0	0
T8	1033	937	0	0
T9	6001	4498	0	0
T10	706	644	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421735679	421597267	0	0
T1	1375	1284	0	0
T2	951	889	0	0
T3	2704	2634	0	0
T4	12731	12634	0	0
T5	3176	3094	0	0
T6	1218	1129	0	0
T7	1561	1484	0	0
T8	1033	937	0	0
T9	6001	4498	0	0
T10	706	644	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	421735679	460196	0	0
DepthKnown_A	421735679	421597267	0	0
RvalidKnown_A	421735679	421597267	0	0
WreadyKnown_A	421735679	421597267	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421735679	460196	0	0
T3	2704	299	0	0
T4	12731	0	0	0
T5	3176	176	0	0
T6	1218	0	0	0
T7	1561	0	0	0
T8	1033	100	0	0
T9	6001	0	0	0
T10	706	0	0	0
T11	97922	0	0	0
T12	15980	0	0	0
T13	0	18	0	0
T30	0	1393	0	0
T31	0	1	0	0
T34	0	307	0	0
T45	0	100	0	0
T47	0	100	0	0
T48	0	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421735679	421597267	0	0
T1	1375	1284	0	0
T2	951	889	0	0
T3	2704	2634	0	0
T4	12731	12634	0	0
T5	3176	3094	0	0
T6	1218	1129	0	0
T7	1561	1484	0	0
T8	1033	937	0	0
T9	6001	4498	0	0
T10	706	644	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421735679	421597267	0	0
T1	1375	1284	0	0
T2	951	889	0	0
T3	2704	2634	0	0
T4	12731	12634	0	0
T5	3176	3094	0	0
T6	1218	1129	0	0
T7	1561	1484	0	0
T8	1033	937	0	0
T9	6001	4498	0	0
T10	706	644	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421735679	421597267	0	0
T1	1375	1284	0	0
T2	951	889	0	0
T3	2704	2634	0	0
T4	12731	12634	0	0
T5	3176	3094	0	0
T6	1218	1129	0	0
T7	1561	1484	0	0
T8	1033	937	0	0
T9	6001	4498	0	0
T10	706	644	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	421735679	5694474	0	0
DepthKnown_A	421735679	421597267	0	0
RvalidKnown_A	421735679	421597267	0	0
WreadyKnown_A	421735679	421597267	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421735679	5694474	0	0
T1	1375	63	0	0
T2	951	1	0	0
T3	2704	1	0	0
T4	12731	44	0	0
T5	3176	148	0	0
T6	1218	17	0	0
T7	1561	63	0	0
T8	1033	1	0	0
T9	6001	1	0	0
T10	706	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421735679	421597267	0	0
T1	1375	1284	0	0
T2	951	889	0	0
T3	2704	2634	0	0
T4	12731	12634	0	0
T5	3176	3094	0	0
T6	1218	1129	0	0
T7	1561	1484	0	0
T8	1033	937	0	0
T9	6001	4498	0	0
T10	706	644	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421735679	421597267	0	0
T1	1375	1284	0	0
T2	951	889	0	0
T3	2704	2634	0	0
T4	12731	12634	0	0
T5	3176	3094	0	0
T6	1218	1129	0	0
T7	1561	1484	0	0
T8	1033	937	0	0
T9	6001	4498	0	0
T10	706	644	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421735679	421597267	0	0
T1	1375	1284	0	0
T2	951	889	0	0
T3	2704	2634	0	0
T4	12731	12634	0	0
T5	3176	3094	0	0
T6	1218	1129	0	0
T7	1561	1484	0	0
T8	1033	937	0	0
T9	6001	4498	0	0
T10	706	644	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	421735679	13761929	0	0
DepthKnown_A	421735679	421597267	0	0
RvalidKnown_A	421735679	421597267	0	0
WreadyKnown_A	421735679	421597267	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421735679	13761929	0	0
T1	1375	63	0	0
T2	951	1	0	0
T3	2704	1	0	0
T4	12731	212	0	0
T5	3176	627	0	0
T6	1218	17	0	0
T7	1561	63	0	0
T8	1033	1	0	0
T9	6001	1	0	0
T10	706	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421735679	421597267	0	0
T1	1375	1284	0	0
T2	951	889	0	0
T3	2704	2634	0	0
T4	12731	12634	0	0
T5	3176	3094	0	0
T6	1218	1129	0	0
T7	1561	1484	0	0
T8	1033	937	0	0
T9	6001	4498	0	0
T10	706	644	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421735679	421597267	0	0
T1	1375	1284	0	0
T2	951	889	0	0
T3	2704	2634	0	0
T4	12731	12634	0	0
T5	3176	3094	0	0
T6	1218	1129	0	0
T7	1561	1484	0	0
T8	1033	937	0	0
T9	6001	4498	0	0
T10	706	644	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421735679	421597267	0	0
T1	1375	1284	0	0
T2	951	889	0	0
T3	2704	2634	0	0
T4	12731	12634	0	0
T5	3176	3094	0	0
T6	1218	1129	0	0
T7	1561	1484	0	0
T8	1033	937	0	0
T9	6001	4498	0	0
T10	706	644	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0