Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	486771839	2904224	0	0
DataKnown_AKnownEnable	486771839	486648921	0	0
DepthKnown_A	486771839	486648921	0	0
RvalidKnown_A	486771839	486648921	0	0
WreadyKnown_A	486771839	486648921	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486771839	2904224	0	0
T4	2657	100	0	0
T5	2146	0	0	0
T6	4458	832	0	0
T7	1068	0	0	0
T8	3951	0	0	0
T9	11311	832	0	0
T10	43139	832	0	0
T11	1792	0	0	0
T12	22096	832	0	0
T15	0	832	0	0
T16	0	832	0	0
T17	0	1666	0	0
T25	2418	100	0	0
T72	0	832	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	486771839	486648921	0	0
T1	1172	1109	0	0
T2	1515	1420	0	0
T3	8161	8093	0	0
T4	2657	2557	0	0
T5	2146	2078	0	0
T6	4458	4384	0	0
T7	1068	968	0	0
T8	3951	3226	0	0
T9	11311	11219	0	0
T10	43139	43045	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486771839	486648921	0	0
T1	1172	1109	0	0
T2	1515	1420	0	0
T3	8161	8093	0	0
T4	2657	2557	0	0
T5	2146	2078	0	0
T6	4458	4384	0	0
T7	1068	968	0	0
T8	3951	3226	0	0
T9	11311	11219	0	0
T10	43139	43045	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486771839	486648921	0	0
T1	1172	1109	0	0
T2	1515	1420	0	0
T3	8161	8093	0	0
T4	2657	2557	0	0
T5	2146	2078	0	0
T6	4458	4384	0	0
T7	1068	968	0	0
T8	3951	3226	0	0
T9	11311	11219	0	0
T10	43139	43045	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486771839	486648921	0	0
T1	1172	1109	0	0
T2	1515	1420	0	0
T3	8161	8093	0	0
T4	2657	2557	0	0
T5	2146	2078	0	0
T6	4458	4384	0	0
T7	1068	968	0	0
T8	3951	3226	0	0
T9	11311	11219	0	0
T10	43139	43045	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	486771839	3176273	0	0
DataKnown_AKnownEnable	486771839	486648921	0	0
DepthKnown_A	486771839	486648921	0	0
RvalidKnown_A	486771839	486648921	0	0
WreadyKnown_A	486771839	486648921	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486771839	3176273	0	0
T4	2657	100	0	0
T5	2146	0	0	0
T6	4458	832	0	0
T7	1068	0	0	0
T8	3951	0	0	0
T9	11311	832	0	0
T10	43139	3632	0	0
T11	1792	0	0	0
T12	22096	2541	0	0
T15	0	832	0	0
T16	0	832	0	0
T17	0	835	0	0
T25	2418	100	0	0
T72	0	3743	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	486771839	486648921	0	0
T1	1172	1109	0	0
T2	1515	1420	0	0
T3	8161	8093	0	0
T4	2657	2557	0	0
T5	2146	2078	0	0
T6	4458	4384	0	0
T7	1068	968	0	0
T8	3951	3226	0	0
T9	11311	11219	0	0
T10	43139	43045	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486771839	486648921	0	0
T1	1172	1109	0	0
T2	1515	1420	0	0
T3	8161	8093	0	0
T4	2657	2557	0	0
T5	2146	2078	0	0
T6	4458	4384	0	0
T7	1068	968	0	0
T8	3951	3226	0	0
T9	11311	11219	0	0
T10	43139	43045	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486771839	486648921	0	0
T1	1172	1109	0	0
T2	1515	1420	0	0
T3	8161	8093	0	0
T4	2657	2557	0	0
T5	2146	2078	0	0
T6	4458	4384	0	0
T7	1068	968	0	0
T8	3951	3226	0	0
T9	11311	11219	0	0
T10	43139	43045	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486771839	486648921	0	0
T1	1172	1109	0	0
T2	1515	1420	0	0
T3	8161	8093	0	0
T4	2657	2557	0	0
T5	2146	2078	0	0
T6	4458	4384	0	0
T7	1068	968	0	0
T8	3951	3226	0	0
T9	11311	11219	0	0
T10	43139	43045	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	486771839	171918	0	0
DataKnown_AKnownEnable	486771839	486648921	0	0
DepthKnown_A	486771839	486648921	0	0
RvalidKnown_A	486771839	486648921	0	0
WreadyKnown_A	486771839	486648921	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486771839	171918	0	0
T4	2657	100	0	0
T5	2146	30	0	0
T6	4458	0	0	0
T7	1068	0	0	0
T8	3951	0	0	0
T9	11311	0	0	0
T10	43139	0	0	0
T11	1792	0	0	0
T12	22096	0	0	0
T20	0	256	0	0
T22	0	397	0	0
T25	2418	100	0	0
T29	0	9	0	0
T30	0	142	0	0
T32	0	767	0	0
T44	0	100	0	0
T45	0	799	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	486771839	486648921	0	0
T1	1172	1109	0	0
T2	1515	1420	0	0
T3	8161	8093	0	0
T4	2657	2557	0	0
T5	2146	2078	0	0
T6	4458	4384	0	0
T7	1068	968	0	0
T8	3951	3226	0	0
T9	11311	11219	0	0
T10	43139	43045	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486771839	486648921	0	0
T1	1172	1109	0	0
T2	1515	1420	0	0
T3	8161	8093	0	0
T4	2657	2557	0	0
T5	2146	2078	0	0
T6	4458	4384	0	0
T7	1068	968	0	0
T8	3951	3226	0	0
T9	11311	11219	0	0
T10	43139	43045	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486771839	486648921	0	0
T1	1172	1109	0	0
T2	1515	1420	0	0
T3	8161	8093	0	0
T4	2657	2557	0	0
T5	2146	2078	0	0
T6	4458	4384	0	0
T7	1068	968	0	0
T8	3951	3226	0	0
T9	11311	11219	0	0
T10	43139	43045	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486771839	486648921	0	0
T1	1172	1109	0	0
T2	1515	1420	0	0
T3	8161	8093	0	0
T4	2657	2557	0	0
T5	2146	2078	0	0
T6	4458	4384	0	0
T7	1068	968	0	0
T8	3951	3226	0	0
T9	11311	11219	0	0
T10	43139	43045	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	486771839	392525	0	0
DataKnown_AKnownEnable	486771839	486648921	0	0
DepthKnown_A	486771839	486648921	0	0
RvalidKnown_A	486771839	486648921	0	0
WreadyKnown_A	486771839	486648921	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486771839	392525	0	0
T4	2657	100	0	0
T5	2146	30	0	0
T6	4458	0	0	0
T7	1068	0	0	0
T8	3951	0	0	0
T9	11311	0	0	0
T10	43139	0	0	0
T11	1792	0	0	0
T12	22096	0	0	0
T20	0	256	0	0
T22	0	1240	0	0
T25	2418	100	0	0
T29	0	20	0	0
T30	0	142	0	0
T32	0	2246	0	0
T44	0	463	0	0
T45	0	799	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	486771839	486648921	0	0
T1	1172	1109	0	0
T2	1515	1420	0	0
T3	8161	8093	0	0
T4	2657	2557	0	0
T5	2146	2078	0	0
T6	4458	4384	0	0
T7	1068	968	0	0
T8	3951	3226	0	0
T9	11311	11219	0	0
T10	43139	43045	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486771839	486648921	0	0
T1	1172	1109	0	0
T2	1515	1420	0	0
T3	8161	8093	0	0
T4	2657	2557	0	0
T5	2146	2078	0	0
T6	4458	4384	0	0
T7	1068	968	0	0
T8	3951	3226	0	0
T9	11311	11219	0	0
T10	43139	43045	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486771839	486648921	0	0
T1	1172	1109	0	0
T2	1515	1420	0	0
T3	8161	8093	0	0
T4	2657	2557	0	0
T5	2146	2078	0	0
T6	4458	4384	0	0
T7	1068	968	0	0
T8	3951	3226	0	0
T9	11311	11219	0	0
T10	43139	43045	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486771839	486648921	0	0
T1	1172	1109	0	0
T2	1515	1420	0	0
T3	8161	8093	0	0
T4	2657	2557	0	0
T5	2146	2078	0	0
T6	4458	4384	0	0
T7	1068	968	0	0
T8	3951	3226	0	0
T9	11311	11219	0	0
T10	43139	43045	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	486771839	6148926	0	0
DataKnown_AKnownEnable	486771839	486648921	0	0
DepthKnown_A	486771839	486648921	0	0
RvalidKnown_A	486771839	486648921	0	0
WreadyKnown_A	486771839	486648921	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486771839	6148926	0	0
T1	1172	73	0	0
T2	1515	1	0	0
T3	8161	44	0	0
T4	2657	1	0	0
T5	2146	263	0	0
T6	4458	72	0	0
T7	1068	20	0	0
T8	3951	1	0	0
T9	11311	624	0	0
T10	43139	46	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	486771839	486648921	0	0
T1	1172	1109	0	0
T2	1515	1420	0	0
T3	8161	8093	0	0
T4	2657	2557	0	0
T5	2146	2078	0	0
T6	4458	4384	0	0
T7	1068	968	0	0
T8	3951	3226	0	0
T9	11311	11219	0	0
T10	43139	43045	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486771839	486648921	0	0
T1	1172	1109	0	0
T2	1515	1420	0	0
T3	8161	8093	0	0
T4	2657	2557	0	0
T5	2146	2078	0	0
T6	4458	4384	0	0
T7	1068	968	0	0
T8	3951	3226	0	0
T9	11311	11219	0	0
T10	43139	43045	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486771839	486648921	0	0
T1	1172	1109	0	0
T2	1515	1420	0	0
T3	8161	8093	0	0
T4	2657	2557	0	0
T5	2146	2078	0	0
T6	4458	4384	0	0
T7	1068	968	0	0
T8	3951	3226	0	0
T9	11311	11219	0	0
T10	43139	43045	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486771839	486648921	0	0
T1	1172	1109	0	0
T2	1515	1420	0	0
T3	8161	8093	0	0
T4	2657	2557	0	0
T5	2146	2078	0	0
T6	4458	4384	0	0
T7	1068	968	0	0
T8	3951	3226	0	0
T9	11311	11219	0	0
T10	43139	43045	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	486771839	12401218	0	0
DataKnown_AKnownEnable	486771839	486648921	0	0
DepthKnown_A	486771839	486648921	0	0
RvalidKnown_A	486771839	486648921	0	0
WreadyKnown_A	486771839	486648921	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486771839	12401218	0	0
T1	1172	73	0	0
T2	1515	1	0	0
T3	8161	44	0	0
T4	2657	1	0	0
T5	2146	263	0	0
T6	4458	72	0	0
T7	1068	20	0	0
T8	3951	1	0	0
T9	11311	624	0	0
T10	43139	213	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	486771839	486648921	0	0
T1	1172	1109	0	0
T2	1515	1420	0	0
T3	8161	8093	0	0
T4	2657	2557	0	0
T5	2146	2078	0	0
T6	4458	4384	0	0
T7	1068	968	0	0
T8	3951	3226	0	0
T9	11311	11219	0	0
T10	43139	43045	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486771839	486648921	0	0
T1	1172	1109	0	0
T2	1515	1420	0	0
T3	8161	8093	0	0
T4	2657	2557	0	0
T5	2146	2078	0	0
T6	4458	4384	0	0
T7	1068	968	0	0
T8	3951	3226	0	0
T9	11311	11219	0	0
T10	43139	43045	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486771839	486648921	0	0
T1	1172	1109	0	0
T2	1515	1420	0	0
T3	8161	8093	0	0
T4	2657	2557	0	0
T5	2146	2078	0	0
T6	4458	4384	0	0
T7	1068	968	0	0
T8	3951	3226	0	0
T9	11311	11219	0	0
T10	43139	43045	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486771839	486648921	0	0
T1	1172	1109	0	0
T2	1515	1420	0	0
T3	8161	8093	0	0
T4	2657	2557	0	0
T5	2146	2078	0	0
T6	4458	4384	0	0
T7	1068	968	0	0
T8	3951	3226	0	0
T9	11311	11219	0	0
T10	43139	43045	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0