Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421735679 |
3523 |
0 |
0 |
T118 |
8956 |
70 |
0 |
0 |
T119 |
6856 |
177 |
0 |
0 |
T120 |
5188 |
12 |
0 |
0 |
T121 |
6449 |
272 |
0 |
0 |
T122 |
51066 |
1 |
0 |
0 |
T123 |
28855 |
3 |
0 |
0 |
T126 |
6541 |
262 |
0 |
0 |
T129 |
5540 |
216 |
0 |
0 |
T134 |
8914 |
3 |
0 |
0 |
T136 |
8824 |
8 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421735679 |
1901 |
0 |
0 |
T106 |
2087 |
5 |
0 |
0 |
T118 |
8956 |
8 |
0 |
0 |
T124 |
91760 |
41 |
0 |
0 |
T147 |
75534 |
392 |
0 |
0 |
T175 |
13420 |
41 |
0 |
0 |
T176 |
13209 |
36 |
0 |
0 |
T177 |
14093 |
19 |
0 |
0 |
T178 |
4746 |
2 |
0 |
0 |
T179 |
11946 |
33 |
0 |
0 |
T180 |
101562 |
116 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421735679 |
1876 |
0 |
0 |
T124 |
91760 |
48 |
0 |
0 |
T147 |
75534 |
473 |
0 |
0 |
T175 |
13420 |
105 |
0 |
0 |
T176 |
13209 |
35 |
0 |
0 |
T177 |
14093 |
11 |
0 |
0 |
T178 |
4746 |
7 |
0 |
0 |
T179 |
11946 |
31 |
0 |
0 |
T180 |
101562 |
74 |
0 |
0 |
T181 |
6965 |
13 |
0 |
0 |
T182 |
155853 |
224 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421735679 |
2768 |
0 |
0 |
T106 |
2087 |
7 |
0 |
0 |
T124 |
91760 |
110 |
0 |
0 |
T147 |
75534 |
461 |
0 |
0 |
T175 |
13420 |
53 |
0 |
0 |
T176 |
13209 |
76 |
0 |
0 |
T177 |
14093 |
27 |
0 |
0 |
T178 |
4746 |
10 |
0 |
0 |
T179 |
11946 |
34 |
0 |
0 |
T180 |
101562 |
228 |
0 |
0 |
T181 |
6965 |
2 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421735679 |
16968 |
0 |
0 |
T106 |
2087 |
2 |
0 |
0 |
T124 |
91760 |
1109 |
0 |
0 |
T147 |
75534 |
513 |
0 |
0 |
T175 |
13420 |
18 |
0 |
0 |
T176 |
13209 |
36 |
0 |
0 |
T177 |
14093 |
96 |
0 |
0 |
T178 |
4746 |
6 |
0 |
0 |
T179 |
11946 |
17 |
0 |
0 |
T180 |
101562 |
2381 |
0 |
0 |
T181 |
6965 |
33 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421735679 |
15939 |
0 |
0 |
T106 |
2087 |
6 |
0 |
0 |
T124 |
91760 |
760 |
0 |
0 |
T147 |
75534 |
525 |
0 |
0 |
T175 |
13420 |
34 |
0 |
0 |
T176 |
13209 |
8 |
0 |
0 |
T177 |
14093 |
78 |
0 |
0 |
T178 |
4746 |
6 |
0 |
0 |
T179 |
11946 |
53 |
0 |
0 |
T180 |
101562 |
2014 |
0 |
0 |
T181 |
6965 |
27 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421735679 |
14728 |
0 |
0 |
T106 |
2087 |
6 |
0 |
0 |
T124 |
91760 |
916 |
0 |
0 |
T147 |
75534 |
461 |
0 |
0 |
T175 |
13420 |
24 |
0 |
0 |
T176 |
13209 |
33 |
0 |
0 |
T177 |
14093 |
108 |
0 |
0 |
T178 |
4746 |
3 |
0 |
0 |
T179 |
11946 |
17 |
0 |
0 |
T180 |
101562 |
2119 |
0 |
0 |
T181 |
6965 |
13 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421735679 |
14556 |
0 |
0 |
T106 |
2087 |
3 |
0 |
0 |
T124 |
91760 |
743 |
0 |
0 |
T147 |
75534 |
469 |
0 |
0 |
T175 |
13420 |
67 |
0 |
0 |
T176 |
13209 |
66 |
0 |
0 |
T177 |
14093 |
187 |
0 |
0 |
T178 |
4746 |
7 |
0 |
0 |
T179 |
11946 |
22 |
0 |
0 |
T180 |
101562 |
1114 |
0 |
0 |
T181 |
6965 |
47 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421735679 |
15066 |
0 |
0 |
T106 |
2087 |
4 |
0 |
0 |
T124 |
91760 |
755 |
0 |
0 |
T147 |
75534 |
482 |
0 |
0 |
T175 |
13420 |
16 |
0 |
0 |
T176 |
13209 |
27 |
0 |
0 |
T177 |
14093 |
92 |
0 |
0 |
T178 |
4746 |
4 |
0 |
0 |
T179 |
11946 |
26 |
0 |
0 |
T180 |
101562 |
1894 |
0 |
0 |
T181 |
6965 |
32 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421735679 |
14954 |
0 |
0 |
T106 |
2087 |
4 |
0 |
0 |
T124 |
91760 |
671 |
0 |
0 |
T132 |
8196 |
9 |
0 |
0 |
T175 |
13420 |
26 |
0 |
0 |
T176 |
13209 |
47 |
0 |
0 |
T177 |
14093 |
63 |
0 |
0 |
T178 |
4746 |
143 |
0 |
0 |
T179 |
11946 |
6 |
0 |
0 |
T180 |
101562 |
1892 |
0 |
0 |
T181 |
6965 |
57 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421735679 |
14374 |
0 |
0 |
T106 |
2087 |
2 |
0 |
0 |
T118 |
8956 |
6 |
0 |
0 |
T124 |
91760 |
1159 |
0 |
0 |
T175 |
13420 |
26 |
0 |
0 |
T176 |
13209 |
46 |
0 |
0 |
T177 |
14093 |
13 |
0 |
0 |
T178 |
4746 |
3 |
0 |
0 |
T179 |
11946 |
14 |
0 |
0 |
T180 |
101562 |
1784 |
0 |
0 |
T181 |
6965 |
35 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421735679 |
15850 |
0 |
0 |
T106 |
2087 |
2 |
0 |
0 |
T124 |
91760 |
1127 |
0 |
0 |
T147 |
75534 |
461 |
0 |
0 |
T175 |
13420 |
27 |
0 |
0 |
T176 |
13209 |
29 |
0 |
0 |
T177 |
14093 |
130 |
0 |
0 |
T178 |
4746 |
6 |
0 |
0 |
T179 |
11946 |
65 |
0 |
0 |
T180 |
101562 |
2282 |
0 |
0 |
T181 |
6965 |
29 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421735679 |
7505 |
0 |
0 |
T106 |
2087 |
9 |
0 |
0 |
T124 |
91760 |
587 |
0 |
0 |
T147 |
75534 |
483 |
0 |
0 |
T175 |
13420 |
55 |
0 |
0 |
T176 |
13209 |
37 |
0 |
0 |
T177 |
14093 |
63 |
0 |
0 |
T178 |
4746 |
49 |
0 |
0 |
T179 |
11946 |
25 |
0 |
0 |
T180 |
101562 |
910 |
0 |
0 |
T181 |
6965 |
13 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421735679 |
7495 |
0 |
0 |
T106 |
2087 |
5 |
0 |
0 |
T124 |
91760 |
428 |
0 |
0 |
T147 |
75534 |
439 |
0 |
0 |
T175 |
13420 |
26 |
0 |
0 |
T176 |
13209 |
25 |
0 |
0 |
T177 |
14093 |
28 |
0 |
0 |
T178 |
4746 |
6 |
0 |
0 |
T179 |
11946 |
28 |
0 |
0 |
T180 |
101562 |
908 |
0 |
0 |
T181 |
6965 |
33 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421735679 |
7365 |
0 |
0 |
T106 |
2087 |
6 |
0 |
0 |
T124 |
91760 |
389 |
0 |
0 |
T147 |
75534 |
446 |
0 |
0 |
T175 |
13420 |
78 |
0 |
0 |
T176 |
13209 |
27 |
0 |
0 |
T177 |
14093 |
11 |
0 |
0 |
T178 |
4746 |
11 |
0 |
0 |
T179 |
11946 |
25 |
0 |
0 |
T180 |
101562 |
792 |
0 |
0 |
T181 |
6965 |
34 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421735679 |
7088 |
0 |
0 |
T106 |
2087 |
1 |
0 |
0 |
T124 |
91760 |
415 |
0 |
0 |
T147 |
75534 |
436 |
0 |
0 |
T175 |
13420 |
75 |
0 |
0 |
T176 |
13209 |
59 |
0 |
0 |
T177 |
14093 |
70 |
0 |
0 |
T178 |
4746 |
51 |
0 |
0 |
T179 |
11946 |
21 |
0 |
0 |
T180 |
101562 |
986 |
0 |
0 |
T181 |
6965 |
12 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421735679 |
6718 |
0 |
0 |
T106 |
2087 |
8 |
0 |
0 |
T124 |
91760 |
433 |
0 |
0 |
T147 |
75534 |
411 |
0 |
0 |
T175 |
13420 |
19 |
0 |
0 |
T176 |
13209 |
42 |
0 |
0 |
T177 |
14093 |
59 |
0 |
0 |
T178 |
4746 |
35 |
0 |
0 |
T179 |
11946 |
19 |
0 |
0 |
T180 |
101562 |
791 |
0 |
0 |
T181 |
6965 |
7 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421735679 |
7498 |
0 |
0 |
T124 |
91760 |
438 |
0 |
0 |
T147 |
75534 |
507 |
0 |
0 |
T149 |
6820 |
59 |
0 |
0 |
T175 |
13420 |
29 |
0 |
0 |
T176 |
13209 |
74 |
0 |
0 |
T177 |
14093 |
125 |
0 |
0 |
T178 |
4746 |
11 |
0 |
0 |
T180 |
101562 |
840 |
0 |
0 |
T181 |
6965 |
26 |
0 |
0 |
T182 |
155853 |
240 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421735679 |
7548 |
0 |
0 |
T124 |
91760 |
337 |
0 |
0 |
T147 |
75534 |
477 |
0 |
0 |
T175 |
13420 |
25 |
0 |
0 |
T176 |
13209 |
38 |
0 |
0 |
T177 |
14093 |
133 |
0 |
0 |
T178 |
4746 |
67 |
0 |
0 |
T179 |
11946 |
9 |
0 |
0 |
T180 |
101562 |
922 |
0 |
0 |
T181 |
6965 |
41 |
0 |
0 |
T182 |
155853 |
315 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421735679 |
7566 |
0 |
0 |
T106 |
2087 |
4 |
0 |
0 |
T124 |
91760 |
341 |
0 |
0 |
T147 |
75534 |
457 |
0 |
0 |
T175 |
13420 |
44 |
0 |
0 |
T176 |
13209 |
26 |
0 |
0 |
T177 |
14093 |
84 |
0 |
0 |
T178 |
4746 |
55 |
0 |
0 |
T179 |
11946 |
10 |
0 |
0 |
T180 |
101562 |
592 |
0 |
0 |
T181 |
6965 |
15 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421735679 |
7435 |
0 |
0 |
T106 |
2087 |
7 |
0 |
0 |
T124 |
91760 |
436 |
0 |
0 |
T147 |
75534 |
558 |
0 |
0 |
T175 |
13420 |
33 |
0 |
0 |
T176 |
13209 |
56 |
0 |
0 |
T177 |
14093 |
85 |
0 |
0 |
T178 |
4746 |
46 |
0 |
0 |
T179 |
11946 |
12 |
0 |
0 |
T180 |
101562 |
1014 |
0 |
0 |
T181 |
6965 |
36 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421735679 |
6643 |
0 |
0 |
T106 |
2087 |
8 |
0 |
0 |
T124 |
91760 |
394 |
0 |
0 |
T132 |
8196 |
6 |
0 |
0 |
T175 |
13420 |
32 |
0 |
0 |
T176 |
13209 |
38 |
0 |
0 |
T177 |
14093 |
31 |
0 |
0 |
T178 |
4746 |
3 |
0 |
0 |
T179 |
11946 |
9 |
0 |
0 |
T180 |
101562 |
707 |
0 |
0 |
T181 |
6965 |
17 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421735679 |
7121 |
0 |
0 |
T106 |
2087 |
7 |
0 |
0 |
T124 |
91760 |
370 |
0 |
0 |
T147 |
75534 |
487 |
0 |
0 |
T175 |
13420 |
49 |
0 |
0 |
T176 |
13209 |
53 |
0 |
0 |
T177 |
14093 |
67 |
0 |
0 |
T178 |
4746 |
7 |
0 |
0 |
T179 |
11946 |
17 |
0 |
0 |
T180 |
101562 |
724 |
0 |
0 |
T181 |
6965 |
44 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421735679 |
7469 |
0 |
0 |
T106 |
2087 |
1 |
0 |
0 |
T124 |
91760 |
407 |
0 |
0 |
T147 |
75534 |
420 |
0 |
0 |
T175 |
13420 |
57 |
0 |
0 |
T176 |
13209 |
60 |
0 |
0 |
T177 |
14093 |
41 |
0 |
0 |
T178 |
4746 |
44 |
0 |
0 |
T179 |
11946 |
13 |
0 |
0 |
T180 |
101562 |
737 |
0 |
0 |
T181 |
6965 |
43 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421735679 |
8142 |
0 |
0 |
T106 |
2087 |
4 |
0 |
0 |
T124 |
91760 |
469 |
0 |
0 |
T147 |
75534 |
455 |
0 |
0 |
T175 |
13420 |
52 |
0 |
0 |
T176 |
13209 |
40 |
0 |
0 |
T177 |
14093 |
47 |
0 |
0 |
T178 |
4746 |
11 |
0 |
0 |
T179 |
11946 |
37 |
0 |
0 |
T180 |
101562 |
1197 |
0 |
0 |
T181 |
6965 |
31 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421735679 |
7142 |
0 |
0 |
T106 |
2087 |
4 |
0 |
0 |
T124 |
91760 |
380 |
0 |
0 |
T147 |
75534 |
497 |
0 |
0 |
T175 |
13420 |
72 |
0 |
0 |
T176 |
13209 |
41 |
0 |
0 |
T177 |
14093 |
63 |
0 |
0 |
T178 |
4746 |
13 |
0 |
0 |
T179 |
11946 |
1 |
0 |
0 |
T180 |
101562 |
963 |
0 |
0 |
T181 |
6965 |
6 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421735679 |
7299 |
0 |
0 |
T106 |
2087 |
6 |
0 |
0 |
T124 |
91760 |
506 |
0 |
0 |
T147 |
75534 |
453 |
0 |
0 |
T175 |
13420 |
16 |
0 |
0 |
T176 |
13209 |
45 |
0 |
0 |
T177 |
14093 |
59 |
0 |
0 |
T178 |
4746 |
33 |
0 |
0 |
T179 |
11946 |
31 |
0 |
0 |
T180 |
101562 |
765 |
0 |
0 |
T181 |
6965 |
15 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421735679 |
6975 |
0 |
0 |
T106 |
2087 |
3 |
0 |
0 |
T124 |
91760 |
417 |
0 |
0 |
T147 |
75534 |
453 |
0 |
0 |
T175 |
13420 |
28 |
0 |
0 |
T176 |
13209 |
68 |
0 |
0 |
T177 |
14093 |
66 |
0 |
0 |
T178 |
4746 |
66 |
0 |
0 |
T179 |
11946 |
29 |
0 |
0 |
T180 |
101562 |
831 |
0 |
0 |
T181 |
6965 |
14 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421735679 |
7768 |
0 |
0 |
T106 |
2087 |
6 |
0 |
0 |
T124 |
91760 |
465 |
0 |
0 |
T147 |
75534 |
461 |
0 |
0 |
T175 |
13420 |
64 |
0 |
0 |
T176 |
13209 |
62 |
0 |
0 |
T177 |
14093 |
85 |
0 |
0 |
T178 |
4746 |
50 |
0 |
0 |
T179 |
11946 |
11 |
0 |
0 |
T180 |
101562 |
975 |
0 |
0 |
T181 |
6965 |
13 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421735679 |
6949 |
0 |
0 |
T106 |
2087 |
8 |
0 |
0 |
T124 |
91760 |
448 |
0 |
0 |
T147 |
75534 |
474 |
0 |
0 |
T175 |
13420 |
49 |
0 |
0 |
T176 |
13209 |
72 |
0 |
0 |
T177 |
14093 |
34 |
0 |
0 |
T178 |
4746 |
60 |
0 |
0 |
T179 |
11946 |
8 |
0 |
0 |
T180 |
101562 |
751 |
0 |
0 |
T181 |
6965 |
35 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421735679 |
7594 |
0 |
0 |
T106 |
2087 |
3 |
0 |
0 |
T124 |
91760 |
441 |
0 |
0 |
T147 |
75534 |
457 |
0 |
0 |
T175 |
13420 |
77 |
0 |
0 |
T176 |
13209 |
14 |
0 |
0 |
T177 |
14093 |
68 |
0 |
0 |
T178 |
4746 |
31 |
0 |
0 |
T179 |
11946 |
22 |
0 |
0 |
T180 |
101562 |
907 |
0 |
0 |
T181 |
6965 |
9 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421735679 |
6991 |
0 |
0 |
T124 |
91760 |
353 |
0 |
0 |
T147 |
75534 |
461 |
0 |
0 |
T175 |
13420 |
67 |
0 |
0 |
T176 |
13209 |
27 |
0 |
0 |
T177 |
14093 |
31 |
0 |
0 |
T178 |
4746 |
7 |
0 |
0 |
T179 |
11946 |
26 |
0 |
0 |
T180 |
101562 |
644 |
0 |
0 |
T181 |
6965 |
18 |
0 |
0 |
T182 |
155853 |
283 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421735679 |
6714 |
0 |
0 |
T106 |
2087 |
2 |
0 |
0 |
T124 |
91760 |
221 |
0 |
0 |
T147 |
75534 |
491 |
0 |
0 |
T175 |
13420 |
43 |
0 |
0 |
T176 |
13209 |
69 |
0 |
0 |
T177 |
14093 |
37 |
0 |
0 |
T178 |
4746 |
56 |
0 |
0 |
T179 |
11946 |
25 |
0 |
0 |
T180 |
101562 |
784 |
0 |
0 |
T181 |
6965 |
14 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421735679 |
6815 |
0 |
0 |
T124 |
91760 |
352 |
0 |
0 |
T147 |
75534 |
459 |
0 |
0 |
T175 |
13420 |
50 |
0 |
0 |
T176 |
13209 |
28 |
0 |
0 |
T177 |
14093 |
44 |
0 |
0 |
T178 |
4746 |
41 |
0 |
0 |
T179 |
11946 |
18 |
0 |
0 |
T180 |
101562 |
772 |
0 |
0 |
T181 |
6965 |
43 |
0 |
0 |
T182 |
155853 |
261 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421735679 |
7310 |
0 |
0 |
T106 |
2087 |
1 |
0 |
0 |
T124 |
91760 |
366 |
0 |
0 |
T147 |
75534 |
504 |
0 |
0 |
T175 |
13420 |
76 |
0 |
0 |
T176 |
13209 |
56 |
0 |
0 |
T177 |
14093 |
57 |
0 |
0 |
T178 |
4746 |
3 |
0 |
0 |
T179 |
11946 |
10 |
0 |
0 |
T180 |
101562 |
634 |
0 |
0 |
T181 |
6965 |
19 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421735679 |
7165 |
0 |
0 |
T106 |
2087 |
2 |
0 |
0 |
T118 |
8956 |
5 |
0 |
0 |
T124 |
91760 |
379 |
0 |
0 |
T175 |
13420 |
49 |
0 |
0 |
T176 |
13209 |
59 |
0 |
0 |
T177 |
14093 |
39 |
0 |
0 |
T178 |
4746 |
3 |
0 |
0 |
T179 |
11946 |
18 |
0 |
0 |
T180 |
101562 |
929 |
0 |
0 |
T181 |
6965 |
25 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421735679 |
2528 |
0 |
0 |
T106 |
2087 |
8 |
0 |
0 |
T124 |
91760 |
72 |
0 |
0 |
T147 |
75534 |
494 |
0 |
0 |
T175 |
13420 |
51 |
0 |
0 |
T176 |
13209 |
60 |
0 |
0 |
T177 |
14093 |
17 |
0 |
0 |
T178 |
4746 |
15 |
0 |
0 |
T179 |
11946 |
16 |
0 |
0 |
T180 |
101562 |
176 |
0 |
0 |
T181 |
6965 |
43 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421735679 |
2179 |
0 |
0 |
T124 |
91760 |
67 |
0 |
0 |
T147 |
75534 |
437 |
0 |
0 |
T175 |
13420 |
14 |
0 |
0 |
T176 |
13209 |
46 |
0 |
0 |
T177 |
14093 |
8 |
0 |
0 |
T178 |
4746 |
4 |
0 |
0 |
T179 |
11946 |
8 |
0 |
0 |
T180 |
101562 |
183 |
0 |
0 |
T181 |
6965 |
19 |
0 |
0 |
T182 |
155853 |
280 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421735679 |
2369 |
0 |
0 |
T106 |
2087 |
3 |
0 |
0 |
T124 |
91760 |
104 |
0 |
0 |
T147 |
75534 |
467 |
0 |
0 |
T175 |
13420 |
38 |
0 |
0 |
T176 |
13209 |
54 |
0 |
0 |
T177 |
14093 |
11 |
0 |
0 |
T178 |
4746 |
16 |
0 |
0 |
T179 |
11946 |
31 |
0 |
0 |
T180 |
101562 |
148 |
0 |
0 |
T181 |
6965 |
13 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421735679 |
2534 |
0 |
0 |
T106 |
2087 |
5 |
0 |
0 |
T124 |
91760 |
107 |
0 |
0 |
T147 |
75534 |
464 |
0 |
0 |
T175 |
13420 |
64 |
0 |
0 |
T176 |
13209 |
61 |
0 |
0 |
T177 |
14093 |
20 |
0 |
0 |
T178 |
4746 |
18 |
0 |
0 |
T179 |
11946 |
20 |
0 |
0 |
T180 |
101562 |
199 |
0 |
0 |
T181 |
6965 |
14 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421735679 |
3428 |
0 |
0 |
T106 |
2087 |
1 |
0 |
0 |
T124 |
91760 |
171 |
0 |
0 |
T147 |
75534 |
475 |
0 |
0 |
T175 |
13420 |
36 |
0 |
0 |
T176 |
13209 |
28 |
0 |
0 |
T177 |
14093 |
39 |
0 |
0 |
T178 |
4746 |
1 |
0 |
0 |
T179 |
11946 |
9 |
0 |
0 |
T180 |
101562 |
311 |
0 |
0 |
T181 |
6965 |
8 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421735679 |
5717 |
0 |
0 |
T65 |
277194 |
0 |
0 |
0 |
T100 |
0 |
30 |
0 |
0 |
T115 |
105149 |
0 |
0 |
0 |
T183 |
4751 |
43 |
0 |
0 |
T184 |
0 |
72 |
0 |
0 |
T185 |
0 |
9 |
0 |
0 |
T186 |
0 |
27 |
0 |
0 |
T187 |
0 |
18 |
0 |
0 |
T188 |
0 |
27 |
0 |
0 |
T189 |
0 |
36 |
0 |
0 |
T190 |
0 |
6 |
0 |
0 |
T191 |
0 |
21 |
0 |
0 |
T192 |
187237 |
0 |
0 |
0 |
T193 |
1230 |
0 |
0 |
0 |
T194 |
1159 |
0 |
0 |
0 |
T195 |
186496 |
0 |
0 |
0 |
T196 |
1267 |
0 |
0 |
0 |
T197 |
129914 |
0 |
0 |
0 |
T198 |
2103 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421735679 |
2362 |
0 |
0 |
T106 |
2087 |
2 |
0 |
0 |
T124 |
91760 |
118 |
0 |
0 |
T147 |
75534 |
416 |
0 |
0 |
T175 |
13420 |
81 |
0 |
0 |
T176 |
13209 |
33 |
0 |
0 |
T177 |
14093 |
11 |
0 |
0 |
T178 |
4746 |
6 |
0 |
0 |
T179 |
11946 |
15 |
0 |
0 |
T180 |
101562 |
136 |
0 |
0 |
T181 |
6965 |
8 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421735679 |
2455 |
0 |
0 |
T106 |
2087 |
4 |
0 |
0 |
T124 |
91760 |
85 |
0 |
0 |
T147 |
75534 |
464 |
0 |
0 |
T175 |
13420 |
44 |
0 |
0 |
T176 |
13209 |
47 |
0 |
0 |
T177 |
14093 |
35 |
0 |
0 |
T178 |
4746 |
11 |
0 |
0 |
T179 |
11946 |
25 |
0 |
0 |
T180 |
101562 |
179 |
0 |
0 |
T181 |
6965 |
4 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421735679 |
1967 |
0 |
0 |
T106 |
2087 |
1 |
0 |
0 |
T124 |
91760 |
46 |
0 |
0 |
T147 |
75534 |
436 |
0 |
0 |
T175 |
13420 |
85 |
0 |
0 |
T176 |
13209 |
32 |
0 |
0 |
T177 |
14093 |
12 |
0 |
0 |
T178 |
4746 |
6 |
0 |
0 |
T179 |
11946 |
13 |
0 |
0 |
T180 |
101562 |
110 |
0 |
0 |
T181 |
6965 |
9 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421735679 |
1883 |
0 |
0 |
T124 |
91760 |
60 |
0 |
0 |
T147 |
75534 |
475 |
0 |
0 |
T175 |
13420 |
76 |
0 |
0 |
T176 |
13209 |
33 |
0 |
0 |
T177 |
14093 |
18 |
0 |
0 |
T178 |
4746 |
10 |
0 |
0 |
T179 |
11946 |
24 |
0 |
0 |
T180 |
101562 |
87 |
0 |
0 |
T181 |
6965 |
52 |
0 |
0 |
T182 |
155853 |
249 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421735679 |
1900 |
0 |
0 |
T106 |
2087 |
6 |
0 |
0 |
T124 |
91760 |
65 |
0 |
0 |
T147 |
75534 |
443 |
0 |
0 |
T175 |
13420 |
43 |
0 |
0 |
T176 |
13209 |
28 |
0 |
0 |
T177 |
14093 |
6 |
0 |
0 |
T178 |
4746 |
4 |
0 |
0 |
T179 |
11946 |
11 |
0 |
0 |
T180 |
101562 |
105 |
0 |
0 |
T181 |
6965 |
19 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421735679 |
1974 |
0 |
0 |
T124 |
91760 |
77 |
0 |
0 |
T147 |
75534 |
485 |
0 |
0 |
T175 |
13420 |
15 |
0 |
0 |
T176 |
13209 |
22 |
0 |
0 |
T177 |
14093 |
14 |
0 |
0 |
T178 |
4746 |
12 |
0 |
0 |
T179 |
11946 |
4 |
0 |
0 |
T180 |
101562 |
114 |
0 |
0 |
T181 |
6965 |
6 |
0 |
0 |
T182 |
155853 |
295 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421735679 |
3052 |
0 |
0 |
T106 |
2087 |
3 |
0 |
0 |
T124 |
91760 |
166 |
0 |
0 |
T147 |
75534 |
431 |
0 |
0 |
T175 |
13420 |
14 |
0 |
0 |
T176 |
13209 |
50 |
0 |
0 |
T177 |
14093 |
20 |
0 |
0 |
T178 |
4746 |
1 |
0 |
0 |
T179 |
11946 |
17 |
0 |
0 |
T180 |
101562 |
282 |
0 |
0 |
T181 |
6965 |
31 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421735679 |
2010 |
0 |
0 |
T124 |
91760 |
79 |
0 |
0 |
T147 |
75534 |
492 |
0 |
0 |
T175 |
13420 |
66 |
0 |
0 |
T176 |
13209 |
28 |
0 |
0 |
T177 |
14093 |
17 |
0 |
0 |
T178 |
4746 |
11 |
0 |
0 |
T179 |
11946 |
38 |
0 |
0 |
T180 |
101562 |
123 |
0 |
0 |
T181 |
6965 |
12 |
0 |
0 |
T182 |
155853 |
260 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421735679 |
3372 |
0 |
0 |
T106 |
2087 |
9 |
0 |
0 |
T124 |
91760 |
129 |
0 |
0 |
T147 |
75534 |
437 |
0 |
0 |
T175 |
13420 |
24 |
0 |
0 |
T176 |
13209 |
46 |
0 |
0 |
T177 |
14093 |
23 |
0 |
0 |
T178 |
4746 |
3 |
0 |
0 |
T179 |
11946 |
18 |
0 |
0 |
T180 |
101562 |
295 |
0 |
0 |
T181 |
6965 |
39 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421735679 |
2261 |
0 |
0 |
T124 |
91760 |
84 |
0 |
0 |
T147 |
75534 |
491 |
0 |
0 |
T175 |
13420 |
14 |
0 |
0 |
T176 |
13209 |
81 |
0 |
0 |
T177 |
14093 |
22 |
0 |
0 |
T178 |
4746 |
4 |
0 |
0 |
T179 |
11946 |
21 |
0 |
0 |
T180 |
101562 |
167 |
0 |
0 |
T181 |
6965 |
17 |
0 |
0 |
T182 |
155853 |
206 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421735679 |
1801 |
0 |
0 |
T106 |
2087 |
7 |
0 |
0 |
T124 |
91760 |
24 |
0 |
0 |
T147 |
75534 |
472 |
0 |
0 |
T175 |
13420 |
65 |
0 |
0 |
T176 |
13209 |
13 |
0 |
0 |
T177 |
14093 |
21 |
0 |
0 |
T178 |
4746 |
7 |
0 |
0 |
T179 |
11946 |
16 |
0 |
0 |
T180 |
101562 |
126 |
0 |
0 |
T181 |
6965 |
38 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421735679 |
1817 |
0 |
0 |
T106 |
2087 |
1 |
0 |
0 |
T124 |
91760 |
60 |
0 |
0 |
T147 |
75534 |
496 |
0 |
0 |
T175 |
13420 |
28 |
0 |
0 |
T176 |
13209 |
51 |
0 |
0 |
T177 |
14093 |
23 |
0 |
0 |
T178 |
4746 |
7 |
0 |
0 |
T179 |
11946 |
6 |
0 |
0 |
T180 |
101562 |
101 |
0 |
0 |
T181 |
6965 |
23 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421735679 |
1944 |
0 |
0 |
T106 |
2087 |
3 |
0 |
0 |
T124 |
91760 |
39 |
0 |
0 |
T147 |
75534 |
534 |
0 |
0 |
T175 |
13420 |
38 |
0 |
0 |
T176 |
13209 |
33 |
0 |
0 |
T177 |
14093 |
15 |
0 |
0 |
T178 |
4746 |
6 |
0 |
0 |
T179 |
11946 |
11 |
0 |
0 |
T180 |
101562 |
134 |
0 |
0 |
T182 |
155853 |
242 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421735679 |
1917 |
0 |
0 |
T106 |
2087 |
2 |
0 |
0 |
T118 |
8956 |
4 |
0 |
0 |
T124 |
91760 |
48 |
0 |
0 |
T147 |
75534 |
453 |
0 |
0 |
T175 |
13420 |
54 |
0 |
0 |
T176 |
13209 |
57 |
0 |
0 |
T177 |
14093 |
11 |
0 |
0 |
T179 |
11946 |
44 |
0 |
0 |
T180 |
101562 |
136 |
0 |
0 |
T181 |
6965 |
50 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421735679 |
1968 |
0 |
0 |
T106 |
2087 |
2 |
0 |
0 |
T124 |
91760 |
69 |
0 |
0 |
T147 |
75534 |
524 |
0 |
0 |
T175 |
13420 |
67 |
0 |
0 |
T176 |
13209 |
56 |
0 |
0 |
T177 |
14093 |
5 |
0 |
0 |
T178 |
4746 |
8 |
0 |
0 |
T179 |
11946 |
23 |
0 |
0 |
T180 |
101562 |
141 |
0 |
0 |
T181 |
6965 |
2 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
421735679 |
1829 |
0 |
0 |
T106 |
2087 |
2 |
0 |
0 |
T124 |
91760 |
60 |
0 |
0 |
T147 |
75534 |
381 |
0 |
0 |
T175 |
13420 |
57 |
0 |
0 |
T176 |
13209 |
26 |
0 |
0 |
T177 |
14093 |
11 |
0 |
0 |
T178 |
4746 |
12 |
0 |
0 |
T179 |
11946 |
15 |
0 |
0 |
T180 |
101562 |
132 |
0 |
0 |
T181 |
6965 |
8 |
0 |
0 |