Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486771839 |
2621 |
0 |
0 |
T114 |
6157 |
64 |
0 |
0 |
T115 |
14210 |
186 |
0 |
0 |
T116 |
4968 |
108 |
0 |
0 |
T120 |
21426 |
355 |
0 |
0 |
T123 |
4244 |
98 |
0 |
0 |
T124 |
5145 |
5 |
0 |
0 |
T125 |
16861 |
275 |
0 |
0 |
T128 |
11835 |
9 |
0 |
0 |
T131 |
14691 |
2 |
0 |
0 |
T132 |
2517 |
3 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486771839 |
2036 |
0 |
0 |
T98 |
4021 |
1 |
0 |
0 |
T102 |
3089 |
7 |
0 |
0 |
T128 |
11835 |
21 |
0 |
0 |
T131 |
14691 |
19 |
0 |
0 |
T136 |
6304 |
2 |
0 |
0 |
T160 |
3608 |
4 |
0 |
0 |
T161 |
7106 |
46 |
0 |
0 |
T162 |
6460 |
7 |
0 |
0 |
T163 |
9070 |
1 |
0 |
0 |
T164 |
10049 |
12 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486771839 |
1971 |
0 |
0 |
T98 |
4021 |
1 |
0 |
0 |
T102 |
3089 |
3 |
0 |
0 |
T119 |
63959 |
39 |
0 |
0 |
T128 |
11835 |
19 |
0 |
0 |
T131 |
14691 |
29 |
0 |
0 |
T136 |
6304 |
5 |
0 |
0 |
T161 |
7106 |
44 |
0 |
0 |
T163 |
9070 |
2 |
0 |
0 |
T164 |
10049 |
3 |
0 |
0 |
T165 |
7555 |
43 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486771839 |
2473 |
0 |
0 |
T98 |
4021 |
13 |
0 |
0 |
T102 |
3089 |
9 |
0 |
0 |
T128 |
11835 |
21 |
0 |
0 |
T131 |
14691 |
50 |
0 |
0 |
T136 |
6304 |
23 |
0 |
0 |
T160 |
3608 |
1 |
0 |
0 |
T161 |
7106 |
26 |
0 |
0 |
T162 |
6460 |
38 |
0 |
0 |
T163 |
9070 |
9 |
0 |
0 |
T165 |
7555 |
20 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486771839 |
6076 |
0 |
0 |
T98 |
4021 |
7 |
0 |
0 |
T102 |
3089 |
12 |
0 |
0 |
T128 |
11835 |
163 |
0 |
0 |
T131 |
14691 |
135 |
0 |
0 |
T136 |
6304 |
105 |
0 |
0 |
T161 |
7106 |
16 |
0 |
0 |
T162 |
6460 |
15 |
0 |
0 |
T163 |
9070 |
224 |
0 |
0 |
T164 |
10049 |
61 |
0 |
0 |
T165 |
7555 |
47 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486771839 |
5903 |
0 |
0 |
T98 |
4021 |
6 |
0 |
0 |
T119 |
63959 |
640 |
0 |
0 |
T128 |
11835 |
124 |
0 |
0 |
T131 |
14691 |
136 |
0 |
0 |
T136 |
6304 |
95 |
0 |
0 |
T161 |
7106 |
20 |
0 |
0 |
T162 |
6460 |
17 |
0 |
0 |
T163 |
9070 |
216 |
0 |
0 |
T164 |
10049 |
140 |
0 |
0 |
T165 |
7555 |
32 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486771839 |
6862 |
0 |
0 |
T98 |
4021 |
5 |
0 |
0 |
T102 |
3089 |
8 |
0 |
0 |
T128 |
11835 |
175 |
0 |
0 |
T131 |
14691 |
16 |
0 |
0 |
T136 |
6304 |
13 |
0 |
0 |
T160 |
3608 |
6 |
0 |
0 |
T161 |
7106 |
4 |
0 |
0 |
T162 |
6460 |
8 |
0 |
0 |
T163 |
9070 |
250 |
0 |
0 |
T165 |
7555 |
8 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486771839 |
7107 |
0 |
0 |
T98 |
4021 |
4 |
0 |
0 |
T102 |
3089 |
12 |
0 |
0 |
T128 |
11835 |
149 |
0 |
0 |
T131 |
14691 |
16 |
0 |
0 |
T136 |
6304 |
10 |
0 |
0 |
T160 |
3608 |
63 |
0 |
0 |
T161 |
7106 |
28 |
0 |
0 |
T162 |
6460 |
20 |
0 |
0 |
T163 |
9070 |
233 |
0 |
0 |
T165 |
7555 |
8 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486771839 |
8003 |
0 |
0 |
T98 |
4021 |
1 |
0 |
0 |
T102 |
3089 |
4 |
0 |
0 |
T119 |
63959 |
588 |
0 |
0 |
T128 |
11835 |
157 |
0 |
0 |
T131 |
14691 |
262 |
0 |
0 |
T136 |
6304 |
228 |
0 |
0 |
T161 |
7106 |
5 |
0 |
0 |
T163 |
9070 |
11 |
0 |
0 |
T164 |
10049 |
7 |
0 |
0 |
T165 |
7555 |
22 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486771839 |
6335 |
0 |
0 |
T98 |
4021 |
1 |
0 |
0 |
T102 |
3089 |
7 |
0 |
0 |
T128 |
11835 |
274 |
0 |
0 |
T131 |
14691 |
152 |
0 |
0 |
T136 |
6304 |
9 |
0 |
0 |
T160 |
3608 |
8 |
0 |
0 |
T161 |
7106 |
3 |
0 |
0 |
T162 |
6460 |
17 |
0 |
0 |
T163 |
9070 |
122 |
0 |
0 |
T165 |
7555 |
12 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486771839 |
6597 |
0 |
0 |
T98 |
4021 |
7 |
0 |
0 |
T102 |
3089 |
2 |
0 |
0 |
T115 |
14210 |
6 |
0 |
0 |
T128 |
11835 |
14 |
0 |
0 |
T131 |
14691 |
230 |
0 |
0 |
T136 |
6304 |
246 |
0 |
0 |
T160 |
3608 |
4 |
0 |
0 |
T161 |
7106 |
35 |
0 |
0 |
T162 |
6460 |
15 |
0 |
0 |
T165 |
7555 |
7 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486771839 |
6972 |
0 |
0 |
T98 |
4021 |
2 |
0 |
0 |
T102 |
3089 |
5 |
0 |
0 |
T128 |
11835 |
266 |
0 |
0 |
T131 |
14691 |
301 |
0 |
0 |
T136 |
6304 |
140 |
0 |
0 |
T160 |
3608 |
2 |
0 |
0 |
T161 |
7106 |
45 |
0 |
0 |
T162 |
6460 |
9 |
0 |
0 |
T163 |
9070 |
127 |
0 |
0 |
T165 |
7555 |
17 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486771839 |
3995 |
0 |
0 |
T102 |
3089 |
10 |
0 |
0 |
T114 |
6157 |
4 |
0 |
0 |
T119 |
63959 |
371 |
0 |
0 |
T128 |
11835 |
102 |
0 |
0 |
T131 |
14691 |
53 |
0 |
0 |
T136 |
6304 |
105 |
0 |
0 |
T161 |
7106 |
27 |
0 |
0 |
T163 |
9070 |
89 |
0 |
0 |
T164 |
10049 |
52 |
0 |
0 |
T165 |
7555 |
41 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486771839 |
4246 |
0 |
0 |
T98 |
4021 |
7 |
0 |
0 |
T102 |
3089 |
11 |
0 |
0 |
T128 |
11835 |
113 |
0 |
0 |
T131 |
14691 |
104 |
0 |
0 |
T136 |
6304 |
7 |
0 |
0 |
T160 |
3608 |
16 |
0 |
0 |
T161 |
7106 |
8 |
0 |
0 |
T162 |
6460 |
8 |
0 |
0 |
T163 |
9070 |
115 |
0 |
0 |
T165 |
7555 |
34 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486771839 |
3463 |
0 |
0 |
T98 |
4021 |
9 |
0 |
0 |
T102 |
3089 |
3 |
0 |
0 |
T119 |
63959 |
268 |
0 |
0 |
T128 |
11835 |
77 |
0 |
0 |
T131 |
14691 |
63 |
0 |
0 |
T136 |
6304 |
108 |
0 |
0 |
T161 |
7106 |
4 |
0 |
0 |
T163 |
9070 |
50 |
0 |
0 |
T164 |
10049 |
44 |
0 |
0 |
T165 |
7555 |
36 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486771839 |
3826 |
0 |
0 |
T98 |
4021 |
7 |
0 |
0 |
T102 |
3089 |
7 |
0 |
0 |
T128 |
11835 |
106 |
0 |
0 |
T131 |
14691 |
73 |
0 |
0 |
T136 |
6304 |
4 |
0 |
0 |
T160 |
3608 |
6 |
0 |
0 |
T161 |
7106 |
28 |
0 |
0 |
T163 |
9070 |
12 |
0 |
0 |
T164 |
10049 |
99 |
0 |
0 |
T165 |
7555 |
7 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486771839 |
3835 |
0 |
0 |
T102 |
3089 |
3 |
0 |
0 |
T128 |
11835 |
68 |
0 |
0 |
T131 |
14691 |
75 |
0 |
0 |
T136 |
6304 |
62 |
0 |
0 |
T160 |
3608 |
3 |
0 |
0 |
T161 |
7106 |
25 |
0 |
0 |
T162 |
6460 |
9 |
0 |
0 |
T163 |
9070 |
12 |
0 |
0 |
T164 |
10049 |
39 |
0 |
0 |
T165 |
7555 |
46 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486771839 |
3462 |
0 |
0 |
T98 |
4021 |
10 |
0 |
0 |
T102 |
3089 |
8 |
0 |
0 |
T128 |
11835 |
83 |
0 |
0 |
T131 |
14691 |
55 |
0 |
0 |
T136 |
6304 |
14 |
0 |
0 |
T160 |
3608 |
7 |
0 |
0 |
T161 |
7106 |
14 |
0 |
0 |
T162 |
6460 |
1 |
0 |
0 |
T163 |
9070 |
40 |
0 |
0 |
T165 |
7555 |
8 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486771839 |
3880 |
0 |
0 |
T98 |
4021 |
1 |
0 |
0 |
T102 |
3089 |
3 |
0 |
0 |
T128 |
11835 |
59 |
0 |
0 |
T131 |
14691 |
155 |
0 |
0 |
T136 |
6304 |
105 |
0 |
0 |
T160 |
3608 |
29 |
0 |
0 |
T161 |
7106 |
36 |
0 |
0 |
T162 |
6460 |
19 |
0 |
0 |
T163 |
9070 |
50 |
0 |
0 |
T165 |
7555 |
26 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486771839 |
3671 |
0 |
0 |
T98 |
4021 |
3 |
0 |
0 |
T102 |
3089 |
9 |
0 |
0 |
T128 |
11835 |
19 |
0 |
0 |
T131 |
14691 |
151 |
0 |
0 |
T136 |
6304 |
11 |
0 |
0 |
T160 |
3608 |
2 |
0 |
0 |
T161 |
7106 |
10 |
0 |
0 |
T162 |
6460 |
2 |
0 |
0 |
T163 |
9070 |
55 |
0 |
0 |
T165 |
7555 |
10 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486771839 |
3707 |
0 |
0 |
T98 |
4021 |
4 |
0 |
0 |
T102 |
3089 |
5 |
0 |
0 |
T128 |
11835 |
124 |
0 |
0 |
T131 |
14691 |
66 |
0 |
0 |
T136 |
6304 |
73 |
0 |
0 |
T160 |
3608 |
30 |
0 |
0 |
T161 |
7106 |
17 |
0 |
0 |
T162 |
6460 |
11 |
0 |
0 |
T163 |
9070 |
42 |
0 |
0 |
T165 |
7555 |
23 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486771839 |
4312 |
0 |
0 |
T98 |
4021 |
4 |
0 |
0 |
T102 |
3089 |
5 |
0 |
0 |
T128 |
11835 |
77 |
0 |
0 |
T131 |
14691 |
165 |
0 |
0 |
T136 |
6304 |
10 |
0 |
0 |
T160 |
3608 |
22 |
0 |
0 |
T161 |
7106 |
27 |
0 |
0 |
T162 |
6460 |
8 |
0 |
0 |
T163 |
9070 |
47 |
0 |
0 |
T165 |
7555 |
27 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486771839 |
4025 |
0 |
0 |
T98 |
4021 |
4 |
0 |
0 |
T102 |
3089 |
11 |
0 |
0 |
T128 |
11835 |
62 |
0 |
0 |
T131 |
14691 |
69 |
0 |
0 |
T136 |
6304 |
69 |
0 |
0 |
T160 |
3608 |
27 |
0 |
0 |
T161 |
7106 |
27 |
0 |
0 |
T162 |
6460 |
21 |
0 |
0 |
T163 |
9070 |
65 |
0 |
0 |
T165 |
7555 |
11 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486771839 |
3443 |
0 |
0 |
T98 |
4021 |
2 |
0 |
0 |
T102 |
3089 |
12 |
0 |
0 |
T128 |
11835 |
67 |
0 |
0 |
T131 |
14691 |
69 |
0 |
0 |
T136 |
6304 |
64 |
0 |
0 |
T160 |
3608 |
5 |
0 |
0 |
T161 |
7106 |
10 |
0 |
0 |
T162 |
6460 |
3 |
0 |
0 |
T163 |
9070 |
52 |
0 |
0 |
T165 |
7555 |
20 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486771839 |
3915 |
0 |
0 |
T98 |
4021 |
6 |
0 |
0 |
T102 |
3089 |
8 |
0 |
0 |
T128 |
11835 |
17 |
0 |
0 |
T131 |
14691 |
142 |
0 |
0 |
T136 |
6304 |
72 |
0 |
0 |
T160 |
3608 |
1 |
0 |
0 |
T161 |
7106 |
7 |
0 |
0 |
T162 |
6460 |
6 |
0 |
0 |
T163 |
9070 |
13 |
0 |
0 |
T165 |
7555 |
21 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486771839 |
3887 |
0 |
0 |
T98 |
4021 |
1 |
0 |
0 |
T102 |
3089 |
12 |
0 |
0 |
T128 |
11835 |
84 |
0 |
0 |
T131 |
14691 |
148 |
0 |
0 |
T136 |
6304 |
4 |
0 |
0 |
T161 |
7106 |
5 |
0 |
0 |
T162 |
6460 |
4 |
0 |
0 |
T163 |
9070 |
63 |
0 |
0 |
T164 |
10049 |
61 |
0 |
0 |
T165 |
7555 |
33 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486771839 |
3514 |
0 |
0 |
T98 |
4021 |
1 |
0 |
0 |
T102 |
3089 |
11 |
0 |
0 |
T128 |
11835 |
74 |
0 |
0 |
T131 |
14691 |
92 |
0 |
0 |
T136 |
6304 |
11 |
0 |
0 |
T160 |
3608 |
44 |
0 |
0 |
T161 |
7106 |
24 |
0 |
0 |
T162 |
6460 |
23 |
0 |
0 |
T163 |
9070 |
61 |
0 |
0 |
T165 |
7555 |
21 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486771839 |
3994 |
0 |
0 |
T98 |
4021 |
1 |
0 |
0 |
T102 |
3089 |
5 |
0 |
0 |
T114 |
6157 |
6 |
0 |
0 |
T128 |
11835 |
75 |
0 |
0 |
T131 |
14691 |
120 |
0 |
0 |
T136 |
6304 |
66 |
0 |
0 |
T160 |
3608 |
7 |
0 |
0 |
T161 |
7106 |
12 |
0 |
0 |
T162 |
6460 |
31 |
0 |
0 |
T165 |
7555 |
25 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486771839 |
3622 |
0 |
0 |
T102 |
3089 |
17 |
0 |
0 |
T128 |
11835 |
99 |
0 |
0 |
T131 |
14691 |
63 |
0 |
0 |
T136 |
6304 |
14 |
0 |
0 |
T160 |
3608 |
11 |
0 |
0 |
T161 |
7106 |
14 |
0 |
0 |
T162 |
6460 |
35 |
0 |
0 |
T163 |
9070 |
109 |
0 |
0 |
T164 |
10049 |
3 |
0 |
0 |
T165 |
7555 |
30 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486771839 |
3824 |
0 |
0 |
T98 |
4021 |
3 |
0 |
0 |
T102 |
3089 |
8 |
0 |
0 |
T128 |
11835 |
67 |
0 |
0 |
T131 |
14691 |
26 |
0 |
0 |
T136 |
6304 |
55 |
0 |
0 |
T160 |
3608 |
16 |
0 |
0 |
T161 |
7106 |
6 |
0 |
0 |
T162 |
6460 |
11 |
0 |
0 |
T163 |
9070 |
47 |
0 |
0 |
T165 |
7555 |
12 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486771839 |
3669 |
0 |
0 |
T102 |
3089 |
14 |
0 |
0 |
T128 |
11835 |
95 |
0 |
0 |
T131 |
14691 |
140 |
0 |
0 |
T136 |
6304 |
54 |
0 |
0 |
T160 |
3608 |
3 |
0 |
0 |
T161 |
7106 |
4 |
0 |
0 |
T162 |
6460 |
16 |
0 |
0 |
T163 |
9070 |
5 |
0 |
0 |
T164 |
10049 |
50 |
0 |
0 |
T165 |
7555 |
45 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486771839 |
3835 |
0 |
0 |
T98 |
4021 |
10 |
0 |
0 |
T102 |
3089 |
13 |
0 |
0 |
T128 |
11835 |
54 |
0 |
0 |
T131 |
14691 |
75 |
0 |
0 |
T136 |
6304 |
57 |
0 |
0 |
T160 |
3608 |
7 |
0 |
0 |
T161 |
7106 |
58 |
0 |
0 |
T162 |
6460 |
4 |
0 |
0 |
T163 |
9070 |
62 |
0 |
0 |
T165 |
7555 |
30 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486771839 |
4033 |
0 |
0 |
T98 |
4021 |
17 |
0 |
0 |
T128 |
11835 |
84 |
0 |
0 |
T131 |
14691 |
120 |
0 |
0 |
T136 |
6304 |
4 |
0 |
0 |
T160 |
3608 |
21 |
0 |
0 |
T161 |
7106 |
19 |
0 |
0 |
T162 |
6460 |
22 |
0 |
0 |
T163 |
9070 |
72 |
0 |
0 |
T164 |
10049 |
60 |
0 |
0 |
T165 |
7555 |
22 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486771839 |
3755 |
0 |
0 |
T98 |
4021 |
16 |
0 |
0 |
T102 |
3089 |
11 |
0 |
0 |
T128 |
11835 |
73 |
0 |
0 |
T131 |
14691 |
127 |
0 |
0 |
T136 |
6304 |
10 |
0 |
0 |
T161 |
7106 |
53 |
0 |
0 |
T162 |
6460 |
6 |
0 |
0 |
T163 |
9070 |
119 |
0 |
0 |
T164 |
10049 |
53 |
0 |
0 |
T165 |
7555 |
47 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486771839 |
3589 |
0 |
0 |
T98 |
4021 |
5 |
0 |
0 |
T102 |
3089 |
9 |
0 |
0 |
T128 |
11835 |
68 |
0 |
0 |
T131 |
14691 |
87 |
0 |
0 |
T136 |
6304 |
6 |
0 |
0 |
T160 |
3608 |
8 |
0 |
0 |
T161 |
7106 |
1 |
0 |
0 |
T162 |
6460 |
12 |
0 |
0 |
T163 |
9070 |
8 |
0 |
0 |
T165 |
7555 |
16 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486771839 |
3910 |
0 |
0 |
T102 |
3089 |
6 |
0 |
0 |
T128 |
11835 |
128 |
0 |
0 |
T131 |
14691 |
88 |
0 |
0 |
T136 |
6304 |
5 |
0 |
0 |
T160 |
3608 |
7 |
0 |
0 |
T161 |
7106 |
15 |
0 |
0 |
T162 |
6460 |
5 |
0 |
0 |
T163 |
9070 |
50 |
0 |
0 |
T164 |
10049 |
50 |
0 |
0 |
T165 |
7555 |
36 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486771839 |
2203 |
0 |
0 |
T98 |
4021 |
1 |
0 |
0 |
T102 |
3089 |
7 |
0 |
0 |
T128 |
11835 |
5 |
0 |
0 |
T131 |
14691 |
22 |
0 |
0 |
T136 |
6304 |
11 |
0 |
0 |
T160 |
3608 |
2 |
0 |
0 |
T161 |
7106 |
31 |
0 |
0 |
T162 |
6460 |
19 |
0 |
0 |
T163 |
9070 |
12 |
0 |
0 |
T165 |
7555 |
31 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486771839 |
2368 |
0 |
0 |
T98 |
4021 |
10 |
0 |
0 |
T102 |
3089 |
13 |
0 |
0 |
T119 |
63959 |
51 |
0 |
0 |
T128 |
11835 |
15 |
0 |
0 |
T131 |
14691 |
33 |
0 |
0 |
T136 |
6304 |
16 |
0 |
0 |
T161 |
7106 |
25 |
0 |
0 |
T162 |
6460 |
31 |
0 |
0 |
T163 |
9070 |
14 |
0 |
0 |
T164 |
10049 |
17 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486771839 |
2106 |
0 |
0 |
T98 |
4021 |
8 |
0 |
0 |
T102 |
3089 |
6 |
0 |
0 |
T128 |
11835 |
25 |
0 |
0 |
T131 |
14691 |
43 |
0 |
0 |
T136 |
6304 |
9 |
0 |
0 |
T161 |
7106 |
19 |
0 |
0 |
T162 |
6460 |
6 |
0 |
0 |
T163 |
9070 |
7 |
0 |
0 |
T164 |
10049 |
9 |
0 |
0 |
T165 |
7555 |
58 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486771839 |
2147 |
0 |
0 |
T98 |
4021 |
6 |
0 |
0 |
T102 |
3089 |
5 |
0 |
0 |
T128 |
11835 |
32 |
0 |
0 |
T131 |
14691 |
44 |
0 |
0 |
T136 |
6304 |
4 |
0 |
0 |
T160 |
3608 |
2 |
0 |
0 |
T161 |
7106 |
1 |
0 |
0 |
T162 |
6460 |
18 |
0 |
0 |
T163 |
9070 |
2 |
0 |
0 |
T165 |
7555 |
10 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486771839 |
2391 |
0 |
0 |
T98 |
4021 |
6 |
0 |
0 |
T102 |
3089 |
6 |
0 |
0 |
T128 |
11835 |
42 |
0 |
0 |
T131 |
14691 |
42 |
0 |
0 |
T136 |
6304 |
25 |
0 |
0 |
T160 |
3608 |
3 |
0 |
0 |
T161 |
7106 |
7 |
0 |
0 |
T162 |
6460 |
9 |
0 |
0 |
T163 |
9070 |
14 |
0 |
0 |
T165 |
7555 |
26 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486771839 |
3779 |
0 |
0 |
T22 |
263135 |
48 |
0 |
0 |
T23 |
3832 |
0 |
0 |
0 |
T30 |
61288 |
0 |
0 |
0 |
T31 |
80093 |
0 |
0 |
0 |
T32 |
266836 |
0 |
0 |
0 |
T37 |
0 |
37 |
0 |
0 |
T41 |
0 |
32 |
0 |
0 |
T45 |
722071 |
0 |
0 |
0 |
T47 |
15273 |
0 |
0 |
0 |
T53 |
78606 |
0 |
0 |
0 |
T56 |
28090 |
0 |
0 |
0 |
T73 |
0 |
19 |
0 |
0 |
T103 |
8429 |
0 |
0 |
0 |
T166 |
0 |
10 |
0 |
0 |
T167 |
0 |
70 |
0 |
0 |
T168 |
0 |
58 |
0 |
0 |
T169 |
0 |
26 |
0 |
0 |
T170 |
0 |
43 |
0 |
0 |
T171 |
0 |
18 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486771839 |
2219 |
0 |
0 |
T98 |
4021 |
12 |
0 |
0 |
T102 |
3089 |
12 |
0 |
0 |
T128 |
11835 |
25 |
0 |
0 |
T131 |
14691 |
30 |
0 |
0 |
T136 |
6304 |
8 |
0 |
0 |
T161 |
7106 |
13 |
0 |
0 |
T162 |
6460 |
12 |
0 |
0 |
T163 |
9070 |
10 |
0 |
0 |
T164 |
10049 |
1 |
0 |
0 |
T165 |
7555 |
8 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486771839 |
2243 |
0 |
0 |
T98 |
4021 |
9 |
0 |
0 |
T102 |
3089 |
8 |
0 |
0 |
T119 |
63959 |
70 |
0 |
0 |
T128 |
11835 |
15 |
0 |
0 |
T131 |
14691 |
31 |
0 |
0 |
T136 |
6304 |
16 |
0 |
0 |
T161 |
7106 |
32 |
0 |
0 |
T163 |
9070 |
18 |
0 |
0 |
T164 |
10049 |
15 |
0 |
0 |
T165 |
7555 |
30 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486771839 |
2047 |
0 |
0 |
T98 |
4021 |
3 |
0 |
0 |
T102 |
3089 |
1 |
0 |
0 |
T128 |
11835 |
22 |
0 |
0 |
T131 |
14691 |
14 |
0 |
0 |
T136 |
6304 |
9 |
0 |
0 |
T160 |
3608 |
2 |
0 |
0 |
T161 |
7106 |
4 |
0 |
0 |
T163 |
9070 |
4 |
0 |
0 |
T164 |
10049 |
18 |
0 |
0 |
T165 |
7555 |
14 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486771839 |
2072 |
0 |
0 |
T98 |
4021 |
5 |
0 |
0 |
T102 |
3089 |
5 |
0 |
0 |
T128 |
11835 |
12 |
0 |
0 |
T131 |
14691 |
31 |
0 |
0 |
T136 |
6304 |
2 |
0 |
0 |
T160 |
3608 |
2 |
0 |
0 |
T161 |
7106 |
26 |
0 |
0 |
T162 |
6460 |
7 |
0 |
0 |
T163 |
9070 |
6 |
0 |
0 |
T165 |
7555 |
20 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486771839 |
2124 |
0 |
0 |
T98 |
4021 |
4 |
0 |
0 |
T102 |
3089 |
10 |
0 |
0 |
T119 |
63959 |
72 |
0 |
0 |
T128 |
11835 |
6 |
0 |
0 |
T131 |
14691 |
26 |
0 |
0 |
T136 |
6304 |
11 |
0 |
0 |
T161 |
7106 |
26 |
0 |
0 |
T162 |
6460 |
28 |
0 |
0 |
T163 |
9070 |
3 |
0 |
0 |
T164 |
10049 |
3 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486771839 |
2023 |
0 |
0 |
T98 |
4021 |
6 |
0 |
0 |
T102 |
3089 |
5 |
0 |
0 |
T128 |
11835 |
18 |
0 |
0 |
T131 |
14691 |
26 |
0 |
0 |
T136 |
6304 |
12 |
0 |
0 |
T161 |
7106 |
35 |
0 |
0 |
T162 |
6460 |
5 |
0 |
0 |
T163 |
9070 |
6 |
0 |
0 |
T164 |
10049 |
11 |
0 |
0 |
T165 |
7555 |
5 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486771839 |
2448 |
0 |
0 |
T98 |
4021 |
5 |
0 |
0 |
T102 |
3089 |
4 |
0 |
0 |
T128 |
11835 |
43 |
0 |
0 |
T131 |
14691 |
35 |
0 |
0 |
T136 |
6304 |
17 |
0 |
0 |
T160 |
3608 |
17 |
0 |
0 |
T161 |
7106 |
25 |
0 |
0 |
T162 |
6460 |
10 |
0 |
0 |
T163 |
9070 |
22 |
0 |
0 |
T165 |
7555 |
24 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486771839 |
2167 |
0 |
0 |
T98 |
4021 |
7 |
0 |
0 |
T102 |
3089 |
11 |
0 |
0 |
T128 |
11835 |
8 |
0 |
0 |
T131 |
14691 |
23 |
0 |
0 |
T136 |
6304 |
3 |
0 |
0 |
T160 |
3608 |
2 |
0 |
0 |
T161 |
7106 |
23 |
0 |
0 |
T162 |
6460 |
34 |
0 |
0 |
T163 |
9070 |
8 |
0 |
0 |
T164 |
10049 |
1 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486771839 |
2685 |
0 |
0 |
T98 |
4021 |
2 |
0 |
0 |
T102 |
3089 |
7 |
0 |
0 |
T128 |
11835 |
49 |
0 |
0 |
T131 |
14691 |
86 |
0 |
0 |
T136 |
6304 |
22 |
0 |
0 |
T160 |
3608 |
14 |
0 |
0 |
T161 |
7106 |
4 |
0 |
0 |
T162 |
6460 |
10 |
0 |
0 |
T163 |
9070 |
32 |
0 |
0 |
T165 |
7555 |
26 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486771839 |
2146 |
0 |
0 |
T98 |
4021 |
4 |
0 |
0 |
T102 |
3089 |
9 |
0 |
0 |
T119 |
63959 |
60 |
0 |
0 |
T128 |
11835 |
21 |
0 |
0 |
T131 |
14691 |
18 |
0 |
0 |
T136 |
6304 |
10 |
0 |
0 |
T160 |
3608 |
2 |
0 |
0 |
T161 |
7106 |
12 |
0 |
0 |
T163 |
9070 |
7 |
0 |
0 |
T165 |
7555 |
47 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486771839 |
1879 |
0 |
0 |
T98 |
4021 |
3 |
0 |
0 |
T102 |
3089 |
10 |
0 |
0 |
T115 |
14210 |
3 |
0 |
0 |
T128 |
11835 |
7 |
0 |
0 |
T131 |
14691 |
28 |
0 |
0 |
T136 |
6304 |
8 |
0 |
0 |
T161 |
7106 |
11 |
0 |
0 |
T162 |
6460 |
19 |
0 |
0 |
T163 |
9070 |
3 |
0 |
0 |
T165 |
7555 |
17 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486771839 |
2028 |
0 |
0 |
T98 |
4021 |
10 |
0 |
0 |
T102 |
3089 |
12 |
0 |
0 |
T128 |
11835 |
13 |
0 |
0 |
T131 |
14691 |
23 |
0 |
0 |
T136 |
6304 |
3 |
0 |
0 |
T161 |
7106 |
32 |
0 |
0 |
T162 |
6460 |
20 |
0 |
0 |
T163 |
9070 |
8 |
0 |
0 |
T164 |
10049 |
7 |
0 |
0 |
T165 |
7555 |
13 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486771839 |
2049 |
0 |
0 |
T98 |
4021 |
11 |
0 |
0 |
T102 |
3089 |
8 |
0 |
0 |
T128 |
11835 |
7 |
0 |
0 |
T131 |
14691 |
24 |
0 |
0 |
T136 |
6304 |
13 |
0 |
0 |
T160 |
3608 |
2 |
0 |
0 |
T161 |
7106 |
13 |
0 |
0 |
T162 |
6460 |
6 |
0 |
0 |
T163 |
9070 |
9 |
0 |
0 |
T165 |
7555 |
6 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486771839 |
2045 |
0 |
0 |
T98 |
4021 |
4 |
0 |
0 |
T102 |
3089 |
2 |
0 |
0 |
T128 |
11835 |
20 |
0 |
0 |
T131 |
14691 |
30 |
0 |
0 |
T136 |
6304 |
11 |
0 |
0 |
T161 |
7106 |
10 |
0 |
0 |
T162 |
6460 |
14 |
0 |
0 |
T163 |
9070 |
7 |
0 |
0 |
T164 |
10049 |
8 |
0 |
0 |
T165 |
7555 |
40 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486771839 |
2037 |
0 |
0 |
T98 |
4021 |
9 |
0 |
0 |
T102 |
3089 |
10 |
0 |
0 |
T128 |
11835 |
21 |
0 |
0 |
T131 |
14691 |
26 |
0 |
0 |
T136 |
6304 |
13 |
0 |
0 |
T161 |
7106 |
34 |
0 |
0 |
T162 |
6460 |
9 |
0 |
0 |
T163 |
9070 |
4 |
0 |
0 |
T164 |
10049 |
8 |
0 |
0 |
T165 |
7555 |
10 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486771839 |
1950 |
0 |
0 |
T98 |
4021 |
3 |
0 |
0 |
T102 |
3089 |
9 |
0 |
0 |
T128 |
11835 |
21 |
0 |
0 |
T131 |
14691 |
29 |
0 |
0 |
T136 |
6304 |
13 |
0 |
0 |
T160 |
3608 |
3 |
0 |
0 |
T161 |
7106 |
16 |
0 |
0 |
T162 |
6460 |
6 |
0 |
0 |
T163 |
9070 |
9 |
0 |
0 |
T165 |
7555 |
32 |
0 |
0 |