SPI_HOST Simulation Results

Tuesday May 16 2023 07:02:31 UTC

GitHub Revision: `50278df8b`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 1341560578

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	9.250m	22.370ms	47	50	94.00
V1	csr_hw_reset	spi_host_csr_hw_reset	3.000s	253.196us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	3.000s	76.289us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	167.639us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	3.000s	104.652us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	38.318us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	3.000s	76.289us	20	20	100.00
		spi_host_csr_aliasing	3.000s	104.652us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	2.000s	41.235us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	3.000s	77.987us	5	5	100.00
V1		TOTAL			112	115	97.39
V2	performance	spi_host_performance	4.000s	29.657us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	3.067m	22.256ms	49	50	98.00
		spi_host_error_cmd	3.000s	44.295us	50	50	100.00
		spi_host_event	18.283m	232.814ms	50	50	100.00
V2	clock_rate	spi_host_speed	5.033m	6.864ms	50	50	100.00
V2	speed	spi_host_speed	5.033m	6.864ms	50	50	100.00
V2	chip_select_timing	spi_host_speed	5.033m	6.864ms	50	50	100.00
V2	sw_reset	spi_host_sw_reset	6.483m	11.121ms	45	50	90.00
V2	passthrough_mode	spi_host_passthrough_mode	4.000s	1.168ms	50	50	100.00
V2	cpol_cpha	spi_host_speed	5.033m	6.864ms	50	50	100.00
V2	full_cycle	spi_host_speed	5.033m	6.864ms	50	50	100.00
V2	duplex	spi_host_smoke	9.250m	22.370ms	47	50	94.00
V2	tx_rx_only	spi_host_smoke	9.250m	22.370ms	47	50	94.00
V2	stress_all	spi_host_stress_all	3.367m	18.169ms	48	50	96.00
V2	spien	spi_host_spien	4.950m	6.809ms	49	50	98.00
V2	stall	spi_host_status_stall	11.550m	64.351ms	48	50	96.00
V2	Idlecsbactive	spi_host_idlecsbactive	1.317m	6.735ms	50	50	100.00
V2	alert_test	spi_host_alert_test	4.000s	37.384us	50	50	100.00
V2	intr_test	spi_host_intr_test	4.000s	44.795us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	6.000s	138.932us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	6.000s	138.932us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	3.000s	253.196us	5	5	100.00
		spi_host_csr_rw	3.000s	76.289us	20	20	100.00
		spi_host_csr_aliasing	3.000s	104.652us	5	5	100.00
		spi_host_same_csr_outstanding	3.000s	37.627us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	3.000s	253.196us	5	5	100.00
		spi_host_csr_rw	3.000s	76.289us	20	20	100.00
		spi_host_csr_aliasing	3.000s	104.652us	5	5	100.00
		spi_host_same_csr_outstanding	3.000s	37.627us	20	20	100.00
V2		TOTAL			679	690	98.41
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	202.830us	20	20	100.00
		spi_host_sec_cm	3.000s	240.643us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	202.830us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	winbond	winbond			0	0	--
V3	stress_all_with_rand_reset	spi_host_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			816	830	98.31

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	15	15	10	66.67
V2S	2	2	2	100.00
V3	2	0	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.07	98.19	95.98	99.74	96.25	95.70	100.00	98.60	90.87

Failure Buckets

UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 4 failures:

Test spi_host_sw_reset has 3 failures.

2.spi_host_sw_reset.705120156
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_sw_reset/latest/run.log

  UVM_FATAL @ 10623736897 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xbb8576d4) == 0x0
  UVM_INFO @ 10623736897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

22.spi_host_sw_reset.4112982733
Line 287, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/22.spi_host_sw_reset/latest/run.log

  UVM_FATAL @ 14487848555 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xe09aee54) == 0x0
  UVM_INFO @ 14487848555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test spi_host_stress_all has 1 failures.

11.spi_host_stress_all.945356643
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/11.spi_host_stress_all/latest/run.log

  UVM_FATAL @ 10055920162 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x90fb3414) == 0x0
  UVM_INFO @ 10055920162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 4 failures:

Test spi_host_smoke has 3 failures.

5.spi_host_smoke.3302785787
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_smoke/latest/run.log

  UVM_FATAL @ 181340785493 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xa5aa3594) == 0x0
  UVM_INFO @ 181340785493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

27.spi_host_smoke.1799374332
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/27.spi_host_smoke/latest/run.log

  UVM_FATAL @ 100398003066 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x1bfc0414) == 0x0
  UVM_INFO @ 100398003066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test spi_host_overflow_underflow has 1 failures.

38.spi_host_overflow_underflow.3453581180
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/38.spi_host_overflow_underflow/latest/run.log

  UVM_FATAL @ 41221006268 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x4c70b754) == 0x0
  UVM_INFO @ 41221006268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:

Test spi_host_status_stall has 2 failures.

34.spi_host_status_stall.125654618
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/34.spi_host_status_stall/latest/run.log

  UVM_FATAL @ 100000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 100000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 100000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

44.spi_host_status_stall.3477209039
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/44.spi_host_status_stall/latest/run.log

  UVM_FATAL @ 100000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 100000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 100000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 2 failures:

Test spi_host_sw_reset has 2 failures.

35.spi_host_sw_reset.1952259207
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/35.spi_host_sw_reset/latest/run.log

  UVM_FATAL @ 10001009110 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x44267a14) == 0x0
  UVM_INFO @ 10001009110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

43.spi_host_sw_reset.3963095499
Line 269, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/43.spi_host_sw_reset/latest/run.log

  UVM_FATAL @ 10464941043 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xb43b06d4) == 0x0
  UVM_INFO @ 10464941043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 1 failures:
- Test spi_host_stress_all has 1 failures.
  - 28.spi_host_stress_all.1808739402
    Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/28.spi_host_stress_all/latest/run.log
```
  UVM_FATAL @ 10026246307 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xd252be54) == 0x0
  UVM_INFO @ 10026246307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 1 failures:
- Test spi_host_spien has 1 failures.
  - 38.spi_host_spien.272757025
    Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/38.spi_host_spien/latest/run.log
```
  UVM_FATAL @ 50678681934 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xb350e0d4) == 0x1
  UVM_INFO @ 50678681934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```