4ddd81322f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_host_smoke | 0 | 50 | 0.00 | ||
| V1 | csr_hw_reset | spi_host_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | csr_rw | spi_host_csr_rw | 0 | 20 | 0.00 | ||
| V1 | csr_bit_bash | spi_host_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | csr_aliasing | spi_host_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw | 0 | 20 | 0.00 | ||
| spi_host_csr_aliasing | 0 | 5 | 0.00 | ||||
| V1 | mem_walk | spi_host_mem_walk | 0 | 5 | 0.00 | ||
| V1 | mem_partial_access | spi_host_mem_partial_access | 0 | 5 | 0.00 | ||
| V1 | TOTAL | 0 | 115 | 0.00 | |||
| V2 | performance | spi_host_performance | 0 | 50 | 0.00 | ||
| V2 | error_event_intr | spi_host_overflow_underflow | 0 | 50 | 0.00 | ||
| spi_host_error_cmd | 0 | 50 | 0.00 | ||||
| spi_host_event | 0 | 50 | 0.00 | ||||
| V2 | clock_rate | spi_host_speed | 0 | 50 | 0.00 | ||
| V2 | speed | spi_host_speed | 0 | 50 | 0.00 | ||
| V2 | chip_select_timing | spi_host_speed | 0 | 50 | 0.00 | ||
| V2 | sw_reset | spi_host_sw_reset | 0 | 50 | 0.00 | ||
| V2 | passthrough_mode | spi_host_passthrough_mode | 0 | 50 | 0.00 | ||
| V2 | cpol_cpha | spi_host_speed | 0 | 50 | 0.00 | ||
| V2 | full_cycle | spi_host_speed | 0 | 50 | 0.00 | ||
| V2 | duplex | spi_host_smoke | 0 | 50 | 0.00 | ||
| V2 | tx_rx_only | spi_host_smoke | 0 | 50 | 0.00 | ||
| V2 | stress_all | spi_host_stress_all | 0 | 50 | 0.00 | ||
| V2 | spien | spi_host_spien | 0 | 50 | 0.00 | ||
| V2 | stall | spi_host_status_stall | 0 | 50 | 0.00 | ||
| V2 | Idlecsbactive | spi_host_idlecsbactive | 0 | 50 | 0.00 | ||
| V2 | alert_test | spi_host_alert_test | 0 | 50 | 0.00 | ||
| V2 | intr_test | spi_host_intr_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | spi_host_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_illegal_access | spi_host_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_outstanding_access | spi_host_csr_hw_reset | 0 | 5 | 0.00 | ||
| spi_host_csr_rw | 0 | 20 | 0.00 | ||||
| spi_host_csr_aliasing | 0 | 5 | 0.00 | ||||
| spi_host_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | tl_d_partial_access | spi_host_csr_hw_reset | 0 | 5 | 0.00 | ||
| spi_host_csr_rw | 0 | 20 | 0.00 | ||||
| spi_host_csr_aliasing | 0 | 5 | 0.00 | ||||
| spi_host_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | TOTAL | 0 | 690 | 0.00 | |||
| V2S | tl_intg_err | spi_host_tl_intg_err | 0 | 20 | 0.00 | ||
| spi_host_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_bus_integrity | spi_host_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | TOTAL | 0 | 25 | 0.00 | |||
| V3 | winbond | winbond | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | spi_host_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 0 | 830 | 0.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 0 | 0.00 |
| V2 | 15 | 15 | 0 | 0.00 |
| V2S | 2 | 2 | 0 | 0.00 |
| V3 | 2 | 0 | 0 | 0.00 |
Job killed most likely because its dependent job failed. has 832 failures:
0.spi_host_smoke.114074046299899338959474992775476876228249318674952689475269660151385849053342
Log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_smoke/latest/run.log
1.spi_host_smoke.31760641476301978455193106032758177877881000965495907998555616261055753025852
Log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_smoke/latest/run.log
... and 48 more failures.
0.spi_host_speed.72800769918498486159698236587352230619697991298531752473095493111350275579679
Log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_speed/latest/run.log
1.spi_host_speed.108581824948841224967566750137800462002249784029959144380139783509603186020830
Log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_speed/latest/run.log
... and 48 more failures.
0.spi_host_performance.95948431394935418717488696309032584958625059595707234530090105922618438868561
Log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_performance/latest/run.log
1.spi_host_performance.62219799191799420489934903425339778992319193289219067205431555002893066141483
Log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_performance/latest/run.log
... and 48 more failures.
0.spi_host_sw_reset.10097409377396216782989337697826931128663366552308928301689667788484926144338
Log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_sw_reset/latest/run.log
1.spi_host_sw_reset.15823116666068197628399452625585736490602468615712065679888847858769603751369
Log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_sw_reset/latest/run.log
... and 48 more failures.
0.spi_host_overflow_underflow.4033700170069243289208690483630155145386051230451286197440555349557035758644
Log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_overflow_underflow/latest/run.log
1.spi_host_overflow_underflow.32990310304463406715028552781379774836290231780122481243943798216076780610722
Log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_overflow_underflow/latest/run.log
... and 48 more failures.
Test default has 1 failures.
Test cover_reg_top has 1 failures.