Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	5	11	68.75

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	5	11	68.75	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	288676580	1			T1	243114		T2	7260		T3	243114
instr_valid_dis	268269080	1			T2	7260		T7	7260		T8	17578
instr_en	3273640	1			T11	65472		T17	65472		T104	65472

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	3341800	1			T1	25510		T3	25510		T11	41326
sram_ifetch_valid_disable	269738780	1			T1	40990		T2	7260		T3	40990
sram_ifetch_enable	15596000	1			T1	176614		T3	176614		T11	135306

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	288676580	1			T1	243114		T2	7260		T3	243114
hw_debug_en_valid_off	271431780	1			T1	58696		T2	7260		T3	58696
hw_debug_en_on	12560700	1			T1	116654		T3	116654		T11	134560

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	5	11	68.75	4
Automatically Generated Cross Bins	12	4	8	66.67	4
User Defined Cross Bins	4	1	3	75.00

Automatically Generated Cross Bins for executable_cross

Uncovered bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	NUMBER	STATUS
[hw_debug_en_valid_off]	[sram_ifetch_invalid_disable]	[instr_valid_dis]	0	1	1
[hw_debug_en_on]	[sram_ifetch_invalid_disable]	[instr_valid_dis , instr_en]	--	--	2
[hw_debug_en_on]	[sram_ifetch_valid_disable]	[instr_valid_dis]	0	1	1

Covered bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	269738780	1			T1	40990		T2	7260		T3	40990
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	265166780	1			T2	7260		T7	7260		T8	17578
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	2515740	1			T11	50314		T17	50314		T104	50314
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	757900	1			T11	15158		T17	15158		T104	15158
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	757900	1			T11	15158		T17	15158		T104	15158
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	2083200	1			T1	15496		T3	15496		T11	26168
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	1844900	1			T1	5346		T3	5346		T11	31552
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	1577600	1			T11	31552		T17	31552		T104	31552

User Defined Cross Bins for executable_cross

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
csr_exec_en	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lc_exec_en	8632600	1			T1	95812		T3	95812		T11	76840
valid_exec_dis	270133080	1			T1	32116		T2	7260		T3	32116
invalid_exec_dis	18937800	1			T1	202124		T3	202124		T11	176632