Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	119053350	1			T1	45841		T3	45841		T8	8789
triple_byte_access	3335000	1			T1	945		T3	945		T9	2598
halfword_access	5076750	1			T1	1438		T3	1438		T9	3955
byte_access	6922550	1			T1	1827		T3	1827		T9	5124
zero_access	1954650	1			T1	458		T3	458		T9	1316

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

67527400

1

T1

26192

T3

26192

T8

4275

auto[1]

68814900

1

T1

24317

T3

24317

T8

4514

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	58854600	1			T1	23775		T3	23775		T8	4275
auto[0]	triple_byte_access	1613400	1			T1	486		T3	486		T9	1284
auto[0]	halfword_access	2493900	1			T1	739		T3	739		T9	1952
auto[0]	byte_access	3477650	1			T1	955		T3	955		T9	2505
auto[0]	zero_access	1087850	1			T1	237		T3	237		T9	662
auto[1]	word_access	60198750	1			T1	22066		T3	22066		T8	4514
auto[1]	triple_byte_access	1721600	1			T1	459		T3	459		T9	1314
auto[1]	halfword_access	2582850	1			T1	699		T3	699		T9	2003
auto[1]	byte_access	3444900	1			T1	872		T3	872		T9	2619
auto[1]	zero_access	866800	1			T1	221		T3	221		T9	654