Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

15867031

1

T1

10240

T3

1499

T4

59407

full_word

128657585

1

T1

103307

T2

150732

T3

15142

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	144524326	1			T1	113547		T2	150732		T3	16641
auto[TlIntgErrCmd]	98	1			T33	12		T53	4		T54	5
auto[TlIntgErrData]	96	1			T33	3		T53	4		T54	3
auto[TlIntgErrBoth]	96	1			T33	5		T53	2		T54	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

69779713

1

T1

56786

T2

753664

T3

6133

auto[1]

74744903

1

T1

56761

T2

753664

T3

10508

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7813856	1			T1	5153		T3	554		T4	30919
auto[TlIntgErrNone]	partial	auto[1]	8052913	1			T1	5087		T3	945		T4	28488
auto[TlIntgErrNone]	full_word	auto[0]	61965727	1			T1	51633		T2	753664		T3	5579
auto[TlIntgErrNone]	full_word	auto[1]	66691830	1			T1	51674		T2	753664		T3	9563
auto[TlIntgErrCmd]	partial	auto[0]	37	1			T33	4		T53	1		T54	1
auto[TlIntgErrCmd]	partial	auto[1]	52	1			T33	7		T53	2		T54	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T53	1		T123	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T33	1		T54	2		T120	1
auto[TlIntgErrData]	partial	auto[0]	41	1			T33	1		T53	1		T54	3
auto[TlIntgErrData]	partial	auto[1]	44	1			T33	2		T53	3		T58	2
auto[TlIntgErrData]	full_word	auto[0]	7	1			T58	1		T119	1		T122	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T63	1		T121	1		T124	1
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T33	4		T54	1		T58	4
auto[TlIntgErrBoth]	partial	auto[1]	50	1			T33	1		T53	1		T54	1
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T58	1		T119	1		T120	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T53	1		T121	1		T125	1