Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	616936	1			T4	8249		T14	1148		T15	1481
auto[1]	10773089	1			T1	28083		T3	751		T5	3709
auto[2]	465133	1			T4	5682		T14	811		T15	1331
auto[3]	10623398	1			T1	27674		T3	763		T5	3671

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13329826	1			T1	46312		T3	1285		T5	7380
auto[1]	2145824	1			T1	4450		T3	108		T4	852
auto[2]	2172177	1			T1	4530		T3	107		T4	673
auto[3]	4830729	1			T1	465		T3	14		T4	25294

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8559433

1

T1

55753

T3

1514

T5

7380

auto[1]

13919123

1

T1

4

T4

3

T15

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	225731	1			T4	1		T14	34		T15	54
auto[0]	auto[0]	auto[1]	24560	1			T4	71		T14	156		T15	224
auto[0]	auto[0]	auto[2]	24679	1			T4	65		T14	193		T15	214
auto[0]	auto[0]	auto[3]	107605	1			T4	8109		T14	765		T15	988
auto[0]	auto[1]	auto[0]	2888550	1			T1	23380		T3	645		T5	3709
auto[0]	auto[1]	auto[1]	303121	1			T1	2193		T3	45		T4	62
auto[0]	auto[1]	auto[2]	325462	1			T1	2275		T3	55		T4	129
auto[0]	auto[1]	auto[3]	485368	1			T1	233		T3	6		T4	7548
auto[0]	auto[2]	auto[0]	159837	1			T4	3		T14	27		T15	55
auto[0]	auto[2]	auto[1]	24616	1			T4	656		T14	162		T15	195
auto[0]	auto[2]	auto[2]	18016	1			T4	39		T14	106		T15	217
auto[0]	auto[2]	auto[3]	74305	1			T4	4984		T14	516		T15	864
auto[0]	auto[3]	auto[0]	2819222	1			T1	22928		T3	640		T5	3671
auto[0]	auto[3]	auto[1]	315287	1			T1	2257		T3	63		T4	63
auto[0]	auto[3]	auto[2]	330690	1			T1	2255		T3	52		T4	440
auto[0]	auto[3]	auto[3]	432384	1			T1	232		T3	8		T4	4650
auto[1]	auto[0]	auto[0]	7736	1			T16	1		T52	1		T128	845
auto[1]	auto[0]	auto[1]	34908	1			T128	3838		T129	3538		T130	2805
auto[1]	auto[0]	auto[2]	35199	1			T128	3739		T129	3464		T130	2858
auto[1]	auto[0]	auto[3]	156518	1			T4	3		T15	1		T81	3
auto[1]	auto[1]	auto[0]	3613490	1			T1	2		T49	3405		T99	40022
auto[1]	auto[1]	auto[1]	716419	1			T49	13544		T99	4029		T100	13095
auto[1]	auto[1]	auto[2]	702179	1			T49	15348		T99	4000		T27	1
auto[1]	auto[1]	auto[3]	1738500	1			T49	61774		T99	394		T100	58391
auto[1]	auto[2]	auto[0]	6780	1			T128	813		T129	716		T130	592
auto[1]	auto[2]	auto[1]	29625	1			T128	3451		T129	3175		T130	2609
auto[1]	auto[2]	auto[2]	27569	1			T128	2593		T129	2973		T130	2369
auto[1]	auto[2]	auto[3]	124385	1			T50	1		T128	11297		T129	13013
auto[1]	auto[3]	auto[0]	3608480	1			T1	2		T49	3477		T99	40111
auto[1]	auto[3]	auto[1]	697288	1			T49	15197		T99	4079		T100	14282
auto[1]	auto[3]	auto[2]	708383	1			T49	13642		T99	4111		T27	1
auto[1]	auto[3]	auto[3]	1711664	1			T49	61892		T99	378		T100	58611