Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.85	100.00	97.56	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1006224816	135398	0	0
ctrl_regwen_rd_A	1006224816	7313	0	0
exec_rd_A	1006224816	6769	0	0
exec_regwen_rd_A	1006224816	7606	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1006224816	135398	0	0
T10	60123	2875	0	0
T11	394820	0	0	0
T12	623978	0	0	0
T13	240382	0	0	0
T14	93424	0	0	0
T15	138878	0	0	0
T16	248601	0	0	0
T17	198688	0	0	0
T18	74847	0	0	0
T22	897	0	0	0
T32	0	2623	0	0
T33	0	4	0	0
T34	0	216	0	0
T53	0	4	0	0
T54	0	3	0	0
T55	0	48	0	0
T56	0	22	0	0
T57	0	12	0	0
T58	0	5	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1006224816	7313	0	0
T33	18529	0	0	0
T53	6338	0	0	0
T54	6302	0	0	0
T55	34840	0	0	0
T56	35001	2	0	0
T57	35574	2	0	0
T64	0	43	0	0
T66	704913	0	0	0
T67	793	0	0	0
T68	745	0	0	0
T69	0	8	0	0
T71	0	31	0	0
T73	0	17	0	0
T75	0	4	0	0
T104	2041	9	0	0
T114	0	13	0	0
T115	0	31	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1006224816	6769	0	0
T33	18529	0	0	0
T53	6338	0	0	0
T54	6302	0	0	0
T55	34840	0	0	0
T56	35001	2	0	0
T57	35574	1	0	0
T64	0	49	0	0
T66	704913	0	0	0
T67	793	0	0	0
T68	745	0	0	0
T69	0	6	0	0
T71	0	4	0	0
T73	0	16	0	0
T75	0	8	0	0
T104	2041	35	0	0
T114	0	9	0	0
T115	0	57	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1006224816	7606	0	0
T33	18529	0	0	0
T53	6338	0	0	0
T54	6302	0	0	0
T55	34840	0	0	0
T56	35001	1	0	0
T57	35574	9	0	0
T64	0	19	0	0
T66	704913	0	0	0
T67	793	0	0	0
T68	745	0	0	0
T69	0	19	0	0
T71	0	3	0	0
T73	0	1	0	0
T75	0	2	0	0
T104	2041	34	0	0
T114	0	13	0	0
T115	0	65	0	0