Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	298481009	1			T1	296990		T2	324740		T3	30937
instr_valid_dis	269431826	1			T1	296990		T2	324740		T3	30937
instr_en	21065661	1			T13	260124		T47	169936		T48	74824

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	8657812	1			T11	101892		T13	6434		T47	107244
sram_ifetch_valid_disable	273683986	1			T1	296990		T2	324740		T3	30937
sram_ifetch_enable	16139211	1			T11	15836		T13	176300		T47	131926

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	298481009	1			T1	296990		T2	324740		T3	30937
hw_debug_en_valid_off	272040121	1			T1	296990		T2	324740		T3	30937
hw_debug_en_on	13734619	1			T11	31206		T13	81796		T47	29616

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	273683986	1			T1	296990		T2	324740		T3	30937
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	261514584	1			T1	296990		T2	324740		T3	30937
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9723628	1			T13	77390		T47	54276		T48	47830
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	2930860	1			T11	61786		T13	6434		T47	87278
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1151234	1			T11	61786		T47	26142		T48	492
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1353878	1			T13	6434		T47	61136		T129	33748
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	2148378	1			T11	11206		T48	26994		T131	31932
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	723408	1			T11	11206		T131	1528		T29	14348
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1082822	1			T48	26994		T131	20000		T132	71658
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	6347481	1			T11	20000		T13	18780		T47	29616
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3164314	1			T11	20000		T47	13164		T48	27732
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	2493260	1			T13	18780		T47	16452		T48	20000

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	6034179	1			T13	176300		T47	43950		T49	189684
lc_exec_en	5238760	1			T13	63016		T48	38192		T28	53564
valid_exec_dis	267054190	1			T1	296990		T2	324740		T3	30937
invalid_exec_dis	24797023	1			T11	117728		T13	182734		T47	239170