Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.67 100.00 98.27 100.00 100.00 99.71 99.70 100.00


Total tests in report: 983
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
86.71 86.71 97.45 97.45 84.13 84.13 94.92 94.92 71.43 71.43 89.63 89.63 95.10 95.10 74.30 74.30 /workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.1731146856
92.52 5.82 98.72 1.28 88.74 4.62 95.27 0.36 100.00 28.57 93.66 4.03 95.10 0.00 76.17 1.88 /workspace/coverage/default/34.sram_ctrl_lc_escalation.2646601684
95.21 2.69 99.27 0.55 93.51 4.76 96.06 0.78 100.00 0.00 97.12 3.46 96.29 1.19 84.24 8.07 /workspace/coverage/default/25.sram_ctrl_regwen.1937969471
96.43 1.22 99.45 0.18 94.23 0.72 96.62 0.57 100.00 0.00 97.98 0.86 96.29 0.00 90.43 6.19 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.817950873
97.10 0.67 99.73 0.27 94.81 0.58 98.93 2.31 100.00 0.00 98.27 0.29 97.18 0.89 90.81 0.38 /workspace/coverage/default/32.sram_ctrl_access_during_key_req.3197500095
97.74 0.64 99.91 0.18 96.97 2.16 99.22 0.28 100.00 0.00 99.14 0.86 97.77 0.59 91.18 0.38 /workspace/coverage/default/0.sram_ctrl_sec_cm.1285079774
98.23 0.49 99.91 0.00 96.97 0.00 99.22 0.00 100.00 0.00 99.42 0.29 97.92 0.15 94.18 3.00 /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.1127976003
98.68 0.45 99.91 0.00 97.40 0.43 99.22 0.00 100.00 0.00 99.71 0.29 97.92 0.00 96.62 2.44 /workspace/coverage/default/21.sram_ctrl_executable.1764605642
98.92 0.24 99.91 0.00 97.40 0.00 99.22 0.00 100.00 0.00 99.71 0.00 97.92 0.00 98.31 1.69 /workspace/coverage/default/16.sram_ctrl_stress_all.2899554716
99.16 0.23 99.91 0.00 97.55 0.14 99.22 0.00 100.00 0.00 99.71 0.00 99.41 1.49 98.31 0.00 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3254342768
99.27 0.11 100.00 0.09 97.55 0.00 99.93 0.71 100.00 0.00 99.71 0.00 99.41 0.00 98.31 0.00 /workspace/coverage/default/12.sram_ctrl_ram_cfg.2274067422
99.35 0.08 100.00 0.00 97.55 0.00 99.93 0.00 100.00 0.00 99.71 0.00 99.41 0.00 98.87 0.56 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3157580818
99.43 0.07 100.00 0.00 97.69 0.14 99.93 0.00 100.00 0.00 99.71 0.00 99.41 0.00 99.25 0.38 /workspace/coverage/default/1.sram_ctrl_stress_all.2530298023
99.48 0.05 100.00 0.00 97.98 0.29 100.00 0.07 100.00 0.00 99.71 0.00 99.41 0.00 99.25 0.00 /workspace/coverage/default/0.sram_ctrl_alert_test.2663195368
99.52 0.04 100.00 0.00 97.98 0.00 100.00 0.00 100.00 0.00 99.71 0.00 99.70 0.30 99.25 0.00 /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3273589669
99.55 0.03 100.00 0.00 97.98 0.00 100.00 0.00 100.00 0.00 99.71 0.00 99.70 0.00 99.44 0.19 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2467865953
99.57 0.03 100.00 0.00 97.98 0.00 100.00 0.00 100.00 0.00 99.71 0.00 99.70 0.00 99.62 0.19 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1769514020
99.60 0.03 100.00 0.00 97.98 0.00 100.00 0.00 100.00 0.00 99.71 0.00 99.70 0.00 99.81 0.19 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2559355948
99.63 0.03 100.00 0.00 97.98 0.00 100.00 0.00 100.00 0.00 99.71 0.00 99.70 0.00 100.00 0.19 /workspace/coverage/default/0.sram_ctrl_stress_all.3354085288

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2749516664
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.4289729744
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3760592758
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.407754856
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1339174053
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.930530295
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3645021463
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.4010862868
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2613023143
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2280569740
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3307074167
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.168157083
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3827332477
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3330244408
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.380691665
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2120471516
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1186036639
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1223693648
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2829893410
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.100723328
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3173439074
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2258601897
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3037254632
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1388977085
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.4151286334
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2580134832
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1040150498
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3747397312
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2559981286
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.162923130
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3532061767
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1653313878
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2756543615
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.647267471
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.999987520
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1248452247
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2218435395
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.233346026
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2884751515
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2651427211
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2270345133
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3249127968
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.4176170553
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1514730
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2944346639
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3923521211
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3117814838
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.365443162
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1660335131
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.281072254
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2611489415
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3283516659
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2373430159
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1771920277
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.260120329
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3337751087
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1899459212
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.721458199
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3804328565
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1296628114
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3924724881
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3230958087
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3115003739
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2498299529
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3210244815
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.4048097277
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1068191708
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1765300590
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2928315233
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1618713707
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2123628948
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1059119661
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.779041439
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.566649855
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2955258854
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2008335095
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.4127948239
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.4055455906
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2499417450
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.596993857
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2100334199
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3397001884
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.4103636883
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2182268546
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3240978122
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1619489637
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2662148371
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.455348630
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3943408093
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.4195905747
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3039456934
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.4149469091
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3349665956
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3374083541
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3661778891
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.649964792
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.174016670
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.4123015756
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.4054610407
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2979840497
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2087956452
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1930566130
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2996297884
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3149658103
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.260909851
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1975872385
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2366952425
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1712741781
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2270912160
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1300429271
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.968166863
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2051040664
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2475975299
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.21676817
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2507963586
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.234431713
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.563782360
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.874377028
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1600853695
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.385699631
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.379286394
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1317835332
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.4081130905
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.767978127
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2845878591
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3015961303
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1881889732
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1544129645
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.2782381546
/workspace/coverage/default/0.sram_ctrl_bijection.1420865751
/workspace/coverage/default/0.sram_ctrl_lc_escalation.3221829728
/workspace/coverage/default/0.sram_ctrl_max_throughput.3754858246
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.691861434
/workspace/coverage/default/0.sram_ctrl_mem_walk.2044381473
/workspace/coverage/default/0.sram_ctrl_multiple_keys.356322672
/workspace/coverage/default/0.sram_ctrl_partial_access.3527731766
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.2996993020
/workspace/coverage/default/0.sram_ctrl_ram_cfg.182142004
/workspace/coverage/default/0.sram_ctrl_regwen.1236076247
/workspace/coverage/default/0.sram_ctrl_smoke.1333050764
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.2752743508
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.2546445170
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.821608283
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.48404111
/workspace/coverage/default/1.sram_ctrl_alert_test.1322148141
/workspace/coverage/default/1.sram_ctrl_bijection.945286837
/workspace/coverage/default/1.sram_ctrl_executable.587476712
/workspace/coverage/default/1.sram_ctrl_lc_escalation.2614112097
/workspace/coverage/default/1.sram_ctrl_max_throughput.613015460
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.1618555439
/workspace/coverage/default/1.sram_ctrl_mem_walk.3897192217
/workspace/coverage/default/1.sram_ctrl_multiple_keys.1763799174
/workspace/coverage/default/1.sram_ctrl_partial_access.3040100319
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.1640305659
/workspace/coverage/default/1.sram_ctrl_ram_cfg.131545225
/workspace/coverage/default/1.sram_ctrl_regwen.2728728753
/workspace/coverage/default/1.sram_ctrl_sec_cm.2836654865
/workspace/coverage/default/1.sram_ctrl_smoke.3857728164
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.1916192662
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.2744155794
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.2148607186
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.1868813840
/workspace/coverage/default/10.sram_ctrl_alert_test.2541967473
/workspace/coverage/default/10.sram_ctrl_bijection.3021222361
/workspace/coverage/default/10.sram_ctrl_executable.2903845786
/workspace/coverage/default/10.sram_ctrl_lc_escalation.1217999631
/workspace/coverage/default/10.sram_ctrl_max_throughput.3912831119
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.3719329200
/workspace/coverage/default/10.sram_ctrl_mem_walk.3676810092
/workspace/coverage/default/10.sram_ctrl_multiple_keys.941872488
/workspace/coverage/default/10.sram_ctrl_partial_access.3222325815
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.2834280995
/workspace/coverage/default/10.sram_ctrl_ram_cfg.1606685228
/workspace/coverage/default/10.sram_ctrl_regwen.1493173272
/workspace/coverage/default/10.sram_ctrl_smoke.3514595916
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.60305671
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.1632982539
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2313450978
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.1351367602
/workspace/coverage/default/11.sram_ctrl_alert_test.3482318110
/workspace/coverage/default/11.sram_ctrl_bijection.3116960152
/workspace/coverage/default/11.sram_ctrl_lc_escalation.805238652
/workspace/coverage/default/11.sram_ctrl_max_throughput.3152799740
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.4126792388
/workspace/coverage/default/11.sram_ctrl_mem_walk.944374051
/workspace/coverage/default/11.sram_ctrl_multiple_keys.408913500
/workspace/coverage/default/11.sram_ctrl_partial_access.3907931672
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.1653813008
/workspace/coverage/default/11.sram_ctrl_ram_cfg.740510756
/workspace/coverage/default/11.sram_ctrl_regwen.2675456383
/workspace/coverage/default/11.sram_ctrl_smoke.3524857504
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.1514049718
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.2153420284
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.1053296656
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.1604171993
/workspace/coverage/default/12.sram_ctrl_alert_test.3774451256
/workspace/coverage/default/12.sram_ctrl_bijection.1889449156
/workspace/coverage/default/12.sram_ctrl_executable.4147644987
/workspace/coverage/default/12.sram_ctrl_lc_escalation.2466646190
/workspace/coverage/default/12.sram_ctrl_max_throughput.3736197895
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.2003453348
/workspace/coverage/default/12.sram_ctrl_mem_walk.3823981254
/workspace/coverage/default/12.sram_ctrl_multiple_keys.3324465044
/workspace/coverage/default/12.sram_ctrl_partial_access.2133521693
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.2761658517
/workspace/coverage/default/12.sram_ctrl_regwen.167565266
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/workspace/coverage/default/45.sram_ctrl_multiple_keys.82358727
/workspace/coverage/default/45.sram_ctrl_partial_access.1429081969
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.745982101
/workspace/coverage/default/45.sram_ctrl_ram_cfg.475756607
/workspace/coverage/default/45.sram_ctrl_regwen.3408440014
/workspace/coverage/default/45.sram_ctrl_smoke.2210150596
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.3199321593
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.1428785766
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.954183199
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.2425938579
/workspace/coverage/default/46.sram_ctrl_alert_test.2105275474
/workspace/coverage/default/46.sram_ctrl_bijection.2543753530
/workspace/coverage/default/46.sram_ctrl_executable.1311318632
/workspace/coverage/default/46.sram_ctrl_lc_escalation.298926802
/workspace/coverage/default/46.sram_ctrl_max_throughput.2812175478
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.1322973709
/workspace/coverage/default/46.sram_ctrl_mem_walk.1913431731
/workspace/coverage/default/46.sram_ctrl_multiple_keys.2501839583
/workspace/coverage/default/46.sram_ctrl_partial_access.8566292
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.3521582912
/workspace/coverage/default/46.sram_ctrl_ram_cfg.3033833568
/workspace/coverage/default/46.sram_ctrl_regwen.1944803275
/workspace/coverage/default/46.sram_ctrl_smoke.1837857529
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.1293024626
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.645681177
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.3227839069
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.3383225237
/workspace/coverage/default/47.sram_ctrl_alert_test.3949251364
/workspace/coverage/default/47.sram_ctrl_bijection.431257112
/workspace/coverage/default/47.sram_ctrl_executable.1850391554
/workspace/coverage/default/47.sram_ctrl_lc_escalation.659954420
/workspace/coverage/default/47.sram_ctrl_max_throughput.1706402953
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.1681603516
/workspace/coverage/default/47.sram_ctrl_mem_walk.2714302125
/workspace/coverage/default/47.sram_ctrl_multiple_keys.2995228282
/workspace/coverage/default/47.sram_ctrl_partial_access.1904992885
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.2970319731
/workspace/coverage/default/47.sram_ctrl_ram_cfg.2320803232
/workspace/coverage/default/47.sram_ctrl_regwen.662143185
/workspace/coverage/default/47.sram_ctrl_smoke.1806136677
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1790115531
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.977272504
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.4109403975
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.3246201033
/workspace/coverage/default/48.sram_ctrl_alert_test.3342898186
/workspace/coverage/default/48.sram_ctrl_bijection.3380078574
/workspace/coverage/default/48.sram_ctrl_lc_escalation.594636044
/workspace/coverage/default/48.sram_ctrl_max_throughput.3704042728
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.822997796
/workspace/coverage/default/48.sram_ctrl_mem_walk.1464789463
/workspace/coverage/default/48.sram_ctrl_multiple_keys.3218096762
/workspace/coverage/default/48.sram_ctrl_partial_access.2897413687
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.77412495
/workspace/coverage/default/48.sram_ctrl_ram_cfg.2760532900
/workspace/coverage/default/48.sram_ctrl_regwen.2073837501
/workspace/coverage/default/48.sram_ctrl_smoke.2639670504
/workspace/coverage/default/48.sram_ctrl_stress_all.2410269146
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.847260632
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.2950661400
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.328267020
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.1843670291
/workspace/coverage/default/49.sram_ctrl_alert_test.3435796918
/workspace/coverage/default/49.sram_ctrl_bijection.131793787
/workspace/coverage/default/49.sram_ctrl_executable.459597569
/workspace/coverage/default/49.sram_ctrl_lc_escalation.3004468930
/workspace/coverage/default/49.sram_ctrl_max_throughput.1641985314
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.4014678380
/workspace/coverage/default/49.sram_ctrl_mem_walk.1618005114
/workspace/coverage/default/49.sram_ctrl_multiple_keys.2617411980
/workspace/coverage/default/49.sram_ctrl_partial_access.490068547
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.3128949071
/workspace/coverage/default/49.sram_ctrl_ram_cfg.357949357
/workspace/coverage/default/49.sram_ctrl_regwen.2680318742
/workspace/coverage/default/49.sram_ctrl_smoke.136600681
/workspace/coverage/default/49.sram_ctrl_stress_all.2580419151
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.4102552094
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.1633490033
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.4234096164
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.3167448732
/workspace/coverage/default/5.sram_ctrl_alert_test.865016981
/workspace/coverage/default/5.sram_ctrl_bijection.3987297113
/workspace/coverage/default/5.sram_ctrl_executable.2761221153
/workspace/coverage/default/5.sram_ctrl_lc_escalation.4063503109
/workspace/coverage/default/5.sram_ctrl_max_throughput.150229360
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.2951922040
/workspace/coverage/default/5.sram_ctrl_mem_walk.986595257
/workspace/coverage/default/5.sram_ctrl_multiple_keys.3943459140
/workspace/coverage/default/5.sram_ctrl_partial_access.2136722087
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.1268696274
/workspace/coverage/default/5.sram_ctrl_ram_cfg.1578126917
/workspace/coverage/default/5.sram_ctrl_regwen.2765682529
/workspace/coverage/default/5.sram_ctrl_smoke.4208566217
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.788126995
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.617589301
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.418527525
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.219149499
/workspace/coverage/default/6.sram_ctrl_alert_test.2293342710
/workspace/coverage/default/6.sram_ctrl_bijection.2088875866
/workspace/coverage/default/6.sram_ctrl_executable.943665241
/workspace/coverage/default/6.sram_ctrl_lc_escalation.3324733718
/workspace/coverage/default/6.sram_ctrl_max_throughput.2279255108
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.1746413865
/workspace/coverage/default/6.sram_ctrl_mem_walk.525058296
/workspace/coverage/default/6.sram_ctrl_multiple_keys.1009654325
/workspace/coverage/default/6.sram_ctrl_partial_access.2613014541
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.4173556938
/workspace/coverage/default/6.sram_ctrl_ram_cfg.2167808279
/workspace/coverage/default/6.sram_ctrl_regwen.1993164972
/workspace/coverage/default/6.sram_ctrl_smoke.350030618
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.3121415702
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.2078826305
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.3486548603
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.1504060095
/workspace/coverage/default/7.sram_ctrl_alert_test.3506974911
/workspace/coverage/default/7.sram_ctrl_bijection.503819408
/workspace/coverage/default/7.sram_ctrl_max_throughput.3781946701
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.924302327
/workspace/coverage/default/7.sram_ctrl_mem_walk.2209719319
/workspace/coverage/default/7.sram_ctrl_multiple_keys.4206165098
/workspace/coverage/default/7.sram_ctrl_partial_access.1182678296
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.1089698279
/workspace/coverage/default/7.sram_ctrl_ram_cfg.3562016026
/workspace/coverage/default/7.sram_ctrl_regwen.397054742
/workspace/coverage/default/7.sram_ctrl_smoke.1733098439
/workspace/coverage/default/7.sram_ctrl_stress_all.1374701088
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2701365858
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.2404687490
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2392494439
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.2928297749
/workspace/coverage/default/8.sram_ctrl_alert_test.1245083194
/workspace/coverage/default/8.sram_ctrl_bijection.2610886178
/workspace/coverage/default/8.sram_ctrl_lc_escalation.3912046426
/workspace/coverage/default/8.sram_ctrl_max_throughput.4001330818
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.1957737001
/workspace/coverage/default/8.sram_ctrl_mem_walk.2570209667
/workspace/coverage/default/8.sram_ctrl_multiple_keys.2485641764
/workspace/coverage/default/8.sram_ctrl_partial_access.4093791320
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.1899036727
/workspace/coverage/default/8.sram_ctrl_ram_cfg.4109984716
/workspace/coverage/default/8.sram_ctrl_regwen.2021820650
/workspace/coverage/default/8.sram_ctrl_smoke.503989315
/workspace/coverage/default/8.sram_ctrl_stress_all.1337761516
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3774279214
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.2555082634
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.4161276290
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.2932719366
/workspace/coverage/default/9.sram_ctrl_alert_test.944567563
/workspace/coverage/default/9.sram_ctrl_bijection.1866702304
/workspace/coverage/default/9.sram_ctrl_executable.2011629216
/workspace/coverage/default/9.sram_ctrl_lc_escalation.1444275042
/workspace/coverage/default/9.sram_ctrl_max_throughput.1252629805
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.726243066
/workspace/coverage/default/9.sram_ctrl_mem_walk.512980431
/workspace/coverage/default/9.sram_ctrl_multiple_keys.235675034
/workspace/coverage/default/9.sram_ctrl_partial_access.1261596249
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.2352474546
/workspace/coverage/default/9.sram_ctrl_ram_cfg.2351462428
/workspace/coverage/default/9.sram_ctrl_regwen.2385469219
/workspace/coverage/default/9.sram_ctrl_smoke.3774375511
/workspace/coverage/default/9.sram_ctrl_stress_all.3282389486
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3039747076
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.2426038609
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3308036753



Total test records in report: 983
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/27.sram_ctrl_multiple_keys.3310837667 Dec 24 01:24:35 PM PST 23 Dec 24 01:43:29 PM PST 23 35646513191 ps
T2 /workspace/coverage/default/32.sram_ctrl_access_during_key_req.3197500095 Dec 24 01:25:50 PM PST 23 Dec 24 01:47:09 PM PST 23 61803041497 ps
T3 /workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.1731146856 Dec 24 01:24:36 PM PST 23 Dec 24 03:03:40 PM PST 23 6550840955 ps
T8 /workspace/coverage/default/23.sram_ctrl_alert_test.2754512671 Dec 24 01:24:33 PM PST 23 Dec 24 01:24:35 PM PST 23 12905186 ps
T9 /workspace/coverage/default/31.sram_ctrl_mem_partial_access.2401750447 Dec 24 01:25:52 PM PST 23 Dec 24 01:27:16 PM PST 23 4298092307 ps
T4 /workspace/coverage/default/36.sram_ctrl_smoke.3516748828 Dec 24 01:25:52 PM PST 23 Dec 24 01:26:34 PM PST 23 4984945455 ps
T10 /workspace/coverage/default/24.sram_ctrl_max_throughput.3547596678 Dec 24 01:24:30 PM PST 23 Dec 24 01:27:43 PM PST 23 2554004402 ps
T11 /workspace/coverage/default/26.sram_ctrl_regwen.2543406432 Dec 24 01:24:35 PM PST 23 Dec 24 01:31:12 PM PST 23 1422360425 ps
T12 /workspace/coverage/default/18.sram_ctrl_partial_access.3450613940 Dec 24 01:23:35 PM PST 23 Dec 24 01:23:58 PM PST 23 4004452226 ps
T13 /workspace/coverage/default/25.sram_ctrl_regwen.1937969471 Dec 24 01:24:35 PM PST 23 Dec 24 01:37:16 PM PST 23 3378023574 ps
T18 /workspace/coverage/default/15.sram_ctrl_bijection.703245584 Dec 24 01:23:27 PM PST 23 Dec 24 01:56:52 PM PST 23 253299068418 ps
T14 /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.1293024626 Dec 24 01:27:08 PM PST 23 Dec 24 02:16:32 PM PST 23 9971264067 ps
T19 /workspace/coverage/default/49.sram_ctrl_stress_pipeline.1633490033 Dec 24 01:27:42 PM PST 23 Dec 24 01:34:49 PM PST 23 19580141458 ps
T15 /workspace/coverage/default/20.sram_ctrl_smoke.264599903 Dec 24 01:23:41 PM PST 23 Dec 24 01:25:34 PM PST 23 1243160175 ps
T20 /workspace/coverage/default/23.sram_ctrl_access_during_key_req.3150251302 Dec 24 01:24:34 PM PST 23 Dec 24 01:46:57 PM PST 23 33805938005 ps
T101 /workspace/coverage/default/4.sram_ctrl_stress_pipeline.2309356728 Dec 24 01:22:05 PM PST 23 Dec 24 01:28:29 PM PST 23 9577995663 ps
T102 /workspace/coverage/default/9.sram_ctrl_max_throughput.1252629805 Dec 24 01:22:45 PM PST 23 Dec 24 01:24:58 PM PST 23 4023497654 ps
T103 /workspace/coverage/default/40.sram_ctrl_bijection.3173745149 Dec 24 01:26:47 PM PST 23 Dec 24 01:40:47 PM PST 23 39355943378 ps
T33 /workspace/coverage/default/39.sram_ctrl_ram_cfg.2916428117 Dec 24 01:26:33 PM PST 23 Dec 24 01:26:48 PM PST 23 2275345810 ps
T21 /workspace/coverage/default/39.sram_ctrl_access_during_key_req.3711989242 Dec 24 01:26:38 PM PST 23 Dec 24 01:43:54 PM PST 23 28682175710 ps
T142 /workspace/coverage/default/22.sram_ctrl_partial_access.1493931386 Dec 24 01:24:28 PM PST 23 Dec 24 01:26:09 PM PST 23 2374641677 ps
T74 /workspace/coverage/default/9.sram_ctrl_access_during_key_req.2932719366 Dec 24 01:22:44 PM PST 23 Dec 24 01:52:10 PM PST 23 10183650595 ps
T16 /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.1127976003 Dec 24 01:25:49 PM PST 23 Dec 24 01:30:13 PM PST 23 56248886313 ps
T17 /workspace/coverage/default/40.sram_ctrl_mem_partial_access.9162455 Dec 24 01:26:47 PM PST 23 Dec 24 01:28:08 PM PST 23 6377202745 ps
T106 /workspace/coverage/default/32.sram_ctrl_stress_pipeline.131371347 Dec 24 01:25:52 PM PST 23 Dec 24 01:31:42 PM PST 23 18067890810 ps
T143 /workspace/coverage/default/4.sram_ctrl_multiple_keys.3636008709 Dec 24 01:22:06 PM PST 23 Dec 24 01:42:05 PM PST 23 7250883995 ps
T144 /workspace/coverage/default/25.sram_ctrl_bijection.1959329532 Dec 24 01:24:31 PM PST 23 Dec 24 02:07:06 PM PST 23 115052134579 ps
T22 /workspace/coverage/default/13.sram_ctrl_alert_test.279349834 Dec 24 01:23:26 PM PST 23 Dec 24 01:23:28 PM PST 23 95274434 ps
T138 /workspace/coverage/default/25.sram_ctrl_partial_access.2683298549 Dec 24 01:24:34 PM PST 23 Dec 24 01:24:44 PM PST 23 2070227887 ps
T47 /workspace/coverage/default/19.sram_ctrl_executable.636455457 Dec 24 01:23:50 PM PST 23 Dec 24 01:42:13 PM PST 23 36649793725 ps
T107 /workspace/coverage/default/22.sram_ctrl_stress_pipeline.3373964077 Dec 24 01:24:13 PM PST 23 Dec 24 01:26:48 PM PST 23 2031597852 ps
T80 /workspace/coverage/default/0.sram_ctrl_access_during_key_req.2782381546 Dec 24 01:21:23 PM PST 23 Dec 24 01:31:44 PM PST 23 68047672822 ps
T108 /workspace/coverage/default/17.sram_ctrl_stress_pipeline.3364283671 Dec 24 01:23:26 PM PST 23 Dec 24 01:29:06 PM PST 23 18666927672 ps
T34 /workspace/coverage/default/12.sram_ctrl_ram_cfg.2274067422 Dec 24 01:23:24 PM PST 23 Dec 24 01:23:30 PM PST 23 355411630 ps
T145 /workspace/coverage/default/48.sram_ctrl_multiple_keys.3218096762 Dec 24 01:27:28 PM PST 23 Dec 24 01:31:47 PM PST 23 5197767142 ps
T146 /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.2622969456 Dec 24 01:26:09 PM PST 23 Dec 24 01:27:57 PM PST 23 1004166684 ps
T137 /workspace/coverage/default/46.sram_ctrl_partial_access.8566292 Dec 24 01:27:07 PM PST 23 Dec 24 01:29:05 PM PST 23 3702316662 ps
T48 /workspace/coverage/default/21.sram_ctrl_executable.1764605642 Dec 24 01:24:27 PM PST 23 Dec 24 01:35:14 PM PST 23 11734402046 ps
T147 /workspace/coverage/default/5.sram_ctrl_multiple_keys.3943459140 Dec 24 01:22:06 PM PST 23 Dec 24 01:40:46 PM PST 23 27504779482 ps
T148 /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.256969791 Dec 24 01:22:10 PM PST 23 Dec 24 01:23:04 PM PST 23 1754914333 ps
T149 /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.4095931564 Dec 24 01:26:15 PM PST 23 Dec 24 01:26:45 PM PST 23 714045541 ps
T27 /workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.534886550 Dec 24 01:26:31 PM PST 23 Dec 24 02:55:32 PM PST 23 10072209171 ps
T150 /workspace/coverage/default/30.sram_ctrl_partial_access.1641760838 Dec 24 01:25:24 PM PST 23 Dec 24 01:25:51 PM PST 23 4345252210 ps
T81 /workspace/coverage/default/15.sram_ctrl_mem_partial_access.4019418733 Dec 24 01:23:26 PM PST 23 Dec 24 01:25:52 PM PST 23 26111489138 ps
T109 /workspace/coverage/default/35.sram_ctrl_partial_access_b2b.2751361539 Dec 24 01:26:07 PM PST 23 Dec 24 01:34:45 PM PST 23 7950774374 ps
T28 /workspace/coverage/default/47.sram_ctrl_regwen.662143185 Dec 24 01:27:28 PM PST 23 Dec 24 01:39:00 PM PST 23 45324377295 ps
T5 /workspace/coverage/default/34.sram_ctrl_lc_escalation.2646601684 Dec 24 01:26:07 PM PST 23 Dec 24 01:26:33 PM PST 23 10372926813 ps
T110 /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.77412495 Dec 24 01:27:27 PM PST 23 Dec 24 01:31:26 PM PST 23 22411737198 ps
T32 /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.365443162 Dec 24 12:56:54 PM PST 23 Dec 24 12:56:58 PM PST 23 43220727 ps
T50 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3173439074 Dec 24 12:56:16 PM PST 23 Dec 24 12:56:21 PM PST 23 190213392 ps
T66 /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.174016670 Dec 24 12:56:12 PM PST 23 Dec 24 12:56:17 PM PST 23 55945819 ps
T53 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.4081130905 Dec 24 12:56:16 PM PST 23 Dec 24 12:56:34 PM PST 23 1387383464 ps
T104 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3115003739 Dec 24 12:56:58 PM PST 23 Dec 24 12:57:05 PM PST 23 195237851 ps
T54 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1068191708 Dec 24 12:57:10 PM PST 23 Dec 24 12:57:29 PM PST 23 369294224 ps
T67 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3254342768 Dec 24 12:56:02 PM PST 23 Dec 24 12:56:06 PM PST 23 33507209 ps
T112 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1619489637 Dec 24 12:56:13 PM PST 23 Dec 24 12:56:17 PM PST 23 22026002 ps
T105 /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.4151286334 Dec 24 12:56:20 PM PST 23 Dec 24 12:56:23 PM PST 23 18200944 ps
T68 /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2373430159 Dec 24 12:57:01 PM PST 23 Dec 24 01:01:43 PM PST 23 7536768487 ps
T51 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.817950873 Dec 24 12:57:10 PM PST 23 Dec 24 12:57:19 PM PST 23 318758871 ps
T69 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3923521211 Dec 24 12:56:57 PM PST 23 Dec 24 12:57:02 PM PST 23 32771980 ps
T52 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1059119661 Dec 24 12:57:01 PM PST 23 Dec 24 12:57:08 PM PST 23 395686321 ps
T113 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2955258854 Dec 24 12:56:13 PM PST 23 Dec 24 12:56:18 PM PST 23 45291524 ps
T114 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2182268546 Dec 24 12:56:14 PM PST 23 Dec 24 12:56:18 PM PST 23 30500358 ps
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T155 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.874377028 Dec 24 12:56:12 PM PST 23 Dec 24 12:56:16 PM PST 23 14147862 ps
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T65 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2218435395 Dec 24 12:56:56 PM PST 23 Dec 24 12:57:02 PM PST 23 314971079 ps
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T159 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.647267471 Dec 24 12:56:53 PM PST 23 Dec 24 12:56:55 PM PST 23 42949729 ps
T160 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3374083541 Dec 24 12:56:30 PM PST 23 Dec 24 12:56:46 PM PST 23 539346012 ps
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T164 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.767978127 Dec 24 12:56:16 PM PST 23 Dec 24 12:56:20 PM PST 23 24119218 ps
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T119 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1769514020 Dec 24 12:56:26 PM PST 23 Dec 24 12:56:29 PM PST 23 80511092 ps
T85 /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2498299529 Dec 24 12:56:59 PM PST 23 Dec 24 12:57:56 PM PST 23 7729199742 ps
T168 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3149658103 Dec 24 12:56:11 PM PST 23 Dec 24 12:56:17 PM PST 23 279908878 ps
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T169 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.100723328 Dec 24 12:56:23 PM PST 23 Dec 24 12:56:27 PM PST 23 70244104 ps
T170 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3645021463 Dec 24 12:56:07 PM PST 23 Dec 24 12:56:14 PM PST 23 53006178 ps
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T172 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.407754856 Dec 24 12:56:04 PM PST 23 Dec 24 12:56:10 PM PST 23 15359073 ps
T122 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.234431713 Dec 24 12:56:10 PM PST 23 Dec 24 12:56:15 PM PST 23 326766210 ps
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T174 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2120471516 Dec 24 12:56:26 PM PST 23 Dec 24 12:56:32 PM PST 23 745304386 ps
T99 /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.168157083 Dec 24 12:56:01 PM PST 23 Dec 24 01:00:37 PM PST 23 7431373218 ps
T175 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.563782360 Dec 24 12:56:17 PM PST 23 Dec 24 12:56:25 PM PST 23 702434733 ps
T120 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.4054610407 Dec 24 12:56:29 PM PST 23 Dec 24 12:56:33 PM PST 23 296650793 ps
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T177 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3532061767 Dec 24 12:56:29 PM PST 23 Dec 24 12:56:33 PM PST 23 29162558 ps
T92 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2087956452 Dec 24 12:56:17 PM PST 23 Dec 24 12:56:21 PM PST 23 40402871 ps
T178 /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3210244815 Dec 24 12:57:05 PM PST 23 Dec 24 12:57:13 PM PST 23 38919644 ps
T100 /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1600853695 Dec 24 12:56:12 PM PST 23 Dec 24 12:57:07 PM PST 23 3778646420 ps
T179 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.4010862868 Dec 24 12:56:05 PM PST 23 Dec 24 12:56:11 PM PST 23 19803964 ps
T93 /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2366952425 Dec 24 12:56:29 PM PST 23 Dec 24 12:58:29 PM PST 23 117657487333 ps
T180 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.4123015756 Dec 24 12:56:09 PM PST 23 Dec 24 12:56:14 PM PST 23 87801049 ps
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T125 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1317835332 Dec 24 12:56:11 PM PST 23 Dec 24 12:56:16 PM PST 23 524049174 ps
T182 /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2829893410 Dec 24 12:56:21 PM PST 23 Dec 24 12:56:24 PM PST 23 39286005 ps
T183 /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.4055455906 Dec 24 12:56:11 PM PST 23 Dec 24 12:57:18 PM PST 23 16077069196 ps
T184 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2100334199 Dec 24 12:56:22 PM PST 23 Dec 24 12:56:27 PM PST 23 366162471 ps
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T121 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.233346026 Dec 24 12:57:17 PM PST 23 Dec 24 12:57:26 PM PST 23 105583154 ps
T188 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2756543615 Dec 24 12:56:55 PM PST 23 Dec 24 12:57:13 PM PST 23 3111630575 ps
T189 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.281072254 Dec 24 12:56:59 PM PST 23 Dec 24 12:57:07 PM PST 23 325000078 ps
T190 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1899459212 Dec 24 12:56:57 PM PST 23 Dec 24 12:57:14 PM PST 23 352573354 ps
T191 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1040150498 Dec 24 12:56:13 PM PST 23 Dec 24 12:56:19 PM PST 23 360328896 ps
T192 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.4149469091 Dec 24 12:56:11 PM PST 23 Dec 24 12:56:15 PM PST 23 224409825 ps
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T195 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2611489415 Dec 24 12:56:55 PM PST 23 Dec 24 12:57:10 PM PST 23 696477290 ps
T196 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2051040664 Dec 24 12:56:15 PM PST 23 Dec 24 12:56:19 PM PST 23 12418045 ps
T197 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2884751515 Dec 24 12:56:58 PM PST 23 Dec 24 12:57:09 PM PST 23 347171070 ps
T95 /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1930566130 Dec 24 12:56:30 PM PST 23 Dec 24 01:01:02 PM PST 23 31253001229 ps
T198 /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3249127968 Dec 24 12:57:09 PM PST 23 Dec 24 12:57:17 PM PST 23 58296159 ps
T199 /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2662148371 Dec 24 12:56:11 PM PST 23 Dec 24 12:57:06 PM PST 23 14765215972 ps
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T206 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.4127948239 Dec 24 12:56:14 PM PST 23 Dec 24 12:56:18 PM PST 23 14414194 ps
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T207 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1186036639 Dec 24 12:56:20 PM PST 23 Dec 24 12:56:23 PM PST 23 26373974 ps
T208 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.380691665 Dec 24 12:56:09 PM PST 23 Dec 24 12:56:14 PM PST 23 275992566 ps
T209 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2944346639 Dec 24 12:57:01 PM PST 23 Dec 24 12:57:11 PM PST 23 1361731156 ps
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T213 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.260909851 Dec 24 12:56:15 PM PST 23 Dec 24 12:56:34 PM PST 23 729616943 ps
T214 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1514730 Dec 24 12:56:56 PM PST 23 Dec 24 12:57:01 PM PST 23 701518855 ps
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T224 /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.2970319731 Dec 24 01:27:13 PM PST 23 Dec 24 01:32:23 PM PST 23 20904366702 ps
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T23 /workspace/coverage/default/0.sram_ctrl_alert_test.2663195368 Dec 24 01:22:04 PM PST 23 Dec 24 01:22:06 PM PST 23 24945099 ps
T49 /workspace/coverage/default/13.sram_ctrl_regwen.3679793084 Dec 24 01:23:28 PM PST 23 Dec 24 01:43:33 PM PST 23 20665971284 ps
T226 /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.2591010079 Dec 24 01:26:09 PM PST 23 Dec 24 01:28:17 PM PST 23 1695304818 ps
T227 /workspace/coverage/default/3.sram_ctrl_mem_walk.3332274970 Dec 24 01:22:04 PM PST 23 Dec 24 01:24:44 PM PST 23 10550538640 ps
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T229 /workspace/coverage/default/9.sram_ctrl_partial_access.1261596249 Dec 24 01:22:42 PM PST 23 Dec 24 01:23:48 PM PST 23 7629060376 ps
T230 /workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.2656324116 Dec 24 01:24:31 PM PST 23 Dec 24 02:12:44 PM PST 23 851578343 ps
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