Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	125803510	1			T1	134975		T2	147580		T3	3510
triple_byte_access	2643240	1			T1	2739		T2	3062		T3	9
halfword_access	4061297	1			T1	3939		T2	4394		T3	8
byte_access	5692555	1			T1	5469		T2	5888		T3	18
zero_access	1743296	1			T1	1373		T2	1446		T3	6

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

69338359

1

T1

74486

T2

81116

T3

239

auto[1]

70605539

1

T1

74009

T2

81254

T3

3312

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	62165133	1			T1	67599		T2	73700		T3	223
auto[0]	triple_byte_access	1247961	1			T1	1415		T2	1506		T3	4
auto[0]	halfword_access	1970313	1			T1	1999		T2	2203		T3	4
auto[0]	byte_access	2906752	1			T1	2760		T2	2988		T3	7
auto[0]	zero_access	1048200	1			T1	713		T2	719		T3	1
auto[1]	word_access	63638377	1			T1	67376		T2	73880		T3	3287
auto[1]	triple_byte_access	1395279	1			T1	1324		T2	1556		T3	5
auto[1]	halfword_access	2090984	1			T1	1940		T2	2191		T3	4
auto[1]	byte_access	2785803	1			T1	2709		T2	2900		T3	11
auto[1]	zero_access	695096	1			T1	660		T2	727		T3	5