Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

14987411

1

T1

10924

T2

5119

T3

11

full_word

124790269

1

T1

27227

T2

49237

T3

122

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	139777370	1			T1	38151		T2	54356		T3	133
auto[TlIntgErrCmd]	101	1			T49	6		T50	4		T51	7
auto[TlIntgErrData]	100	1			T49	10		T50	2		T51	8
auto[TlIntgErrBoth]	109	1			T49	4		T50	4		T51	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

67443168

1

T1

13502

T2

27266

T3

66

auto[1]

72334512

1

T1

24649

T2

27090

T3

67

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7380090	1			T1	2661		T2	2513		T3	8
auto[TlIntgErrNone]	partial	auto[1]	7607037	1			T1	8263		T2	2606		T3	3
auto[TlIntgErrNone]	full_word	auto[0]	60062945	1			T1	10841		T2	24753		T3	58
auto[TlIntgErrNone]	full_word	auto[1]	64727298	1			T1	16386		T2	24484		T3	64
auto[TlIntgErrCmd]	partial	auto[0]	36	1			T49	3		T50	2		T51	3
auto[TlIntgErrCmd]	partial	auto[1]	60	1			T49	3		T50	2		T51	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T51	1		T104	1		T105	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T105	1		T110	1		-	-
auto[TlIntgErrData]	partial	auto[0]	45	1			T49	5		T50	2		T51	2
auto[TlIntgErrData]	partial	auto[1]	44	1			T49	5		T51	6		T104	1
auto[TlIntgErrData]	full_word	auto[0]	6	1			T90	2		T108	1		T111	2
auto[TlIntgErrData]	full_word	auto[1]	5	1			T109	2		T105	1		T106	1
auto[TlIntgErrBoth]	partial	auto[0]	37	1			T49	2		T50	2		T51	1
auto[TlIntgErrBoth]	partial	auto[1]	62	1			T49	2		T50	2		T51	4
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T104	3		T112	1		T113	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T109	1		T112	1		T114	2