Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	827218	1			T14	2173		T15	627		T16	845
auto[1]	9524957	1			T1	1086		T2	915		T3	1
auto[2]	653819	1			T14	2122		T15	402		T16	786
auto[3]	9368862	1			T1	566		T2	887		T3	2

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	12354666	1			T1	1392		T2	1238		T3	3
auto[1]	1870518	1			T1	123		T2	243		T10	1708
auto[2]	1913425	1			T1	122		T2	282		T10	1651
auto[3]	4236247	1			T1	15		T2	39		T10	165

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8055584

1

T1

1652

T2

1802

T3

3

auto[1]

12319272

1

T11

3

T13

3

T14

2

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	314361	1			T15	513		T16	683		T74	1
auto[0]	auto[0]	auto[1]	32730	1			T14	18		T15	55		T16	69
auto[0]	auto[0]	auto[2]	32674	1			T14	16		T15	50		T16	80
auto[0]	auto[0]	auto[3]	99521	1			T14	2139		T15	9		T16	13
auto[0]	auto[1]	auto[0]	2458376	1			T1	908		T2	634		T3	1
auto[0]	auto[1]	auto[1]	277223	1			T1	79		T2	182		T10	990
auto[0]	auto[1]	auto[2]	300702	1			T1	86		T2	76		T10	971
auto[0]	auto[1]	auto[3]	627219	1			T1	13		T2	23		T10	116
auto[0]	auto[2]	auto[0]	234834	1			T15	312		T16	637		T74	5
auto[0]	auto[2]	auto[1]	31374	1			T14	133		T15	35		T16	73
auto[0]	auto[2]	auto[2]	21643	1			T14	15		T15	50		T16	73
auto[0]	auto[2]	auto[3]	69469	1			T14	1973		T15	5		T16	3
auto[0]	auto[3]	auto[0]	2391419	1			T1	484		T2	604		T3	2
auto[0]	auto[3]	auto[1]	289100	1			T1	44		T2	61		T10	718
auto[0]	auto[3]	auto[2]	309171	1			T1	36		T2	206		T10	680
auto[0]	auto[3]	auto[3]	565768	1			T1	2		T2	16		T10	49
auto[1]	auto[0]	auto[0]	11461	1			T127	1		T99	414		T100	1069
auto[1]	auto[0]	auto[1]	51446	1			T99	1940		T100	4968		T128	5037
auto[1]	auto[0]	auto[2]	51695	1			T99	1896		T100	4966		T128	5024
auto[1]	auto[0]	auto[3]	233330	1			T74	1		T99	8778		T100	22723
auto[1]	auto[1]	auto[0]	3467162	1			T11	1		T20	50294		T95	181
auto[1]	auto[1]	auto[1]	594862	1			T20	4611		T95	2089		T96	6119
auto[1]	auto[1]	auto[2]	563558	1			T20	4961		T95	696		T96	6277
auto[1]	auto[1]	auto[3]	1235855	1			T13	1		T14	1		T18	2
auto[1]	auto[2]	auto[0]	9532	1			T99	246		T100	1076		T128	1070
auto[1]	auto[2]	auto[1]	40968	1			T99	1176		T100	4588		T128	4630
auto[1]	auto[2]	auto[2]	44827	1			T99	1877		T100	4164		T128	3390
auto[1]	auto[2]	auto[3]	201172	1			T14	1		T99	8149		T100	19024
auto[1]	auto[3]	auto[0]	3467521	1			T11	1		T19	1		T20	50346
auto[1]	auto[3]	auto[1]	552815	1			T20	5030		T95	696		T96	6133
auto[1]	auto[3]	auto[2]	589155	1			T20	4544		T95	2149		T96	6124
auto[1]	auto[3]	auto[3]	1203913	1			T11	1		T13	2		T20	459