Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.85	100.00	97.56	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1026433771	172930	0	0
ctrl_regwen_rd_A	1026433771	7553	0	0
exec_rd_A	1026433771	7260	0	0
exec_regwen_rd_A	1026433771	7692	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1026433771	172930	0	0
T1	157967	6957	0	0
T2	619470	0	0	0
T3	707356	0	0	0
T4	197597	0	0	0
T9	108326	0	0	0
T10	319845	0	0	0
T11	882662	0	0	0
T12	890	0	0	0
T13	156329	0	0	0
T14	242116	0	0	0
T17	0	1870	0	0
T31	0	1220	0	0
T49	0	5	0	0
T52	0	3973	0	0
T53	0	3116	0	0
T54	0	33	0	0
T55	0	778	0	0
T56	0	696	0	0
T57	0	288	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1026433771	7553	0	0
T15	129406	0	0	0
T17	81198	432	0	0
T18	154516	0	0	0
T19	820527	0	0	0
T20	336157	0	0	0
T31	48041	351	0	0
T49	0	31	0	0
T50	0	48	0	0
T55	0	41	0	0
T57	0	38	0	0
T59	393903	0	0	0
T61	0	15	0	0
T62	0	22	0	0
T63	0	18	0	0
T64	0	45	0	0
T93	875107	0	0	0
T102	72796	0	0	0
T103	44709	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1026433771	7260	0	0
T15	129406	0	0	0
T17	81198	492	0	0
T18	154516	0	0	0
T19	820527	0	0	0
T20	336157	0	0	0
T31	48041	405	0	0
T49	0	55	0	0
T50	0	26	0	0
T55	0	35	0	0
T57	0	38	0	0
T59	393903	0	0	0
T61	0	28	0	0
T62	0	15	0	0
T63	0	28	0	0
T64	0	57	0	0
T93	875107	0	0	0
T102	72796	0	0	0
T103	44709	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1026433771	7692	0	0
T15	129406	0	0	0
T17	81198	401	0	0
T18	154516	0	0	0
T19	820527	0	0	0
T20	336157	0	0	0
T31	48041	322	0	0
T49	0	52	0	0
T50	0	34	0	0
T55	0	106	0	0
T57	0	36	0	0
T59	393903	0	0	0
T61	0	29	0	0
T62	0	25	0	0
T63	0	25	0	0
T64	0	48	0	0
T93	875107	0	0	0
T102	72796	0	0	0
T103	44709	0	0	0