Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	278854214	1			T1	17734		T2	267688		T3	408802
instr_valid_dis	255319631	1			T1	17734		T2	267688		T3	408802
instr_en	18360039	1			T14	36232		T44	114462		T57	267566

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	13462201	1			T13	85096		T14	119114		T44	29776
sram_ifetch_valid_disable	252434352	1			T1	17734		T2	267688		T3	408802
sram_ifetch_enable	12957661	1			T13	90728		T14	142890		T44	55234

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	278854214	1			T1	17734		T2	267688		T3	408802
hw_debug_en_valid_off	254321982	1			T1	17734		T2	267688		T3	408802
hw_debug_en_on	17830002	1			T13	102412		T14	260538		T44	87516

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	252434352	1			T1	17734		T2	267688		T3	408802
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	240850178	1			T1	17734		T2	267688		T3	408802
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9451827	1			T14	12604		T44	91590		T57	65798
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4370429	1			T13	27576		T14	5384		T44	29776
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	2748430	1			T14	5384		T129	27570		T123	278
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1149984	1			T24	9018		T130	3382		T41	16112
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	7739306	1			T13	40044		T14	41140		T57	48614
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	5870728	1			T14	41140		T125	5344		T129	19552
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1375096	1			T57	48614		T129	7490		T24	48700
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	5391797	1			T13	23178		T14	142542		T44	64718
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	2149018	1			T14	129874		T44	48370		T125	6556
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	2352730	1			T14	12604		T44	16348		T57	65798

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	5835086	1			T14	23628		T44	22872		T57	153154
lc_exec_en	4698899	1			T13	39190		T14	76856		T44	22798
valid_exec_dis	249793564	1			T1	17734		T2	267688		T3	408802
invalid_exec_dis	26419862	1			T13	175824		T14	262004		T44	85010