Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.67 100.00 98.27 100.00 100.00 99.71 99.70 100.00


Total tests in report: 979
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
84.53 84.53 97.90 97.90 79.22 79.22 86.85 86.85 71.43 71.43 91.35 91.35 94.80 94.80 70.17 70.17 /workspace/coverage/default/13.sram_ctrl_stress_all.1712591611
91.00 6.47 99.18 1.28 86.15 6.93 87.21 0.36 100.00 28.57 96.54 5.19 94.95 0.15 72.98 2.81 /workspace/coverage/default/1.sram_ctrl_lc_escalation.726997098
95.35 4.35 99.54 0.36 92.93 6.78 96.66 9.45 100.00 0.00 97.41 0.86 96.29 1.34 84.62 11.63 /workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.1953665917
96.56 1.21 99.73 0.18 93.80 0.87 98.15 1.49 100.00 0.00 98.27 0.86 96.29 0.00 89.68 5.07 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1313361670
97.26 0.70 99.73 0.00 95.09 1.30 98.15 0.00 100.00 0.00 98.85 0.58 96.29 0.00 92.68 3.00 /workspace/coverage/default/46.sram_ctrl_regwen.3452362217
97.90 0.65 99.91 0.18 97.26 2.16 98.51 0.36 100.00 0.00 99.71 0.86 96.88 0.59 93.06 0.38 /workspace/coverage/default/0.sram_ctrl_sec_cm.3364453552
98.38 0.48 99.91 0.00 97.26 0.00 98.51 0.00 100.00 0.00 99.71 0.00 97.03 0.15 96.25 3.19 /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.2426272260
98.66 0.28 99.91 0.00 97.55 0.29 99.29 0.78 100.00 0.00 99.71 0.00 97.92 0.89 96.25 0.00 /workspace/coverage/default/46.sram_ctrl_access_during_key_req.1397645439
98.89 0.23 99.91 0.00 97.55 0.00 99.29 0.00 100.00 0.00 99.71 0.00 99.55 1.63 96.25 0.00 /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2526140797
99.05 0.16 99.91 0.00 97.55 0.00 99.29 0.00 100.00 0.00 99.71 0.00 99.55 0.00 97.37 1.13 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3884618198
99.19 0.13 99.91 0.00 97.55 0.00 99.29 0.00 100.00 0.00 99.71 0.00 99.55 0.00 98.31 0.94 /workspace/coverage/default/12.sram_ctrl_stress_all.3188010018
99.30 0.11 100.00 0.09 97.55 0.00 100.00 0.71 100.00 0.00 99.71 0.00 99.55 0.00 98.31 0.00 /workspace/coverage/default/21.sram_ctrl_ram_cfg.3729808813
99.38 0.08 100.00 0.00 97.55 0.00 100.00 0.00 100.00 0.00 99.71 0.00 99.55 0.00 98.87 0.56 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2979201137
99.43 0.05 100.00 0.00 97.69 0.14 100.00 0.00 100.00 0.00 99.71 0.00 99.55 0.00 99.06 0.19 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2628379608
99.47 0.04 100.00 0.00 97.98 0.29 100.00 0.00 100.00 0.00 99.71 0.00 99.55 0.00 99.06 0.00 /workspace/coverage/default/1.sram_ctrl_alert_test.2235691826
99.50 0.03 100.00 0.00 97.98 0.00 100.00 0.00 100.00 0.00 99.71 0.00 99.55 0.00 99.25 0.19 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2457688486
99.53 0.03 100.00 0.00 97.98 0.00 100.00 0.00 100.00 0.00 99.71 0.00 99.55 0.00 99.44 0.19 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1218936307
99.55 0.03 100.00 0.00 97.98 0.00 100.00 0.00 100.00 0.00 99.71 0.00 99.55 0.00 99.62 0.19 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3150731427
99.58 0.03 100.00 0.00 97.98 0.00 100.00 0.00 100.00 0.00 99.71 0.00 99.55 0.00 99.81 0.19 /workspace/coverage/default/10.sram_ctrl_lc_escalation.705312266
99.61 0.03 100.00 0.00 97.98 0.00 100.00 0.00 100.00 0.00 99.71 0.00 99.55 0.00 100.00 0.19 /workspace/coverage/default/11.sram_ctrl_stress_all.1322573982
99.63 0.02 100.00 0.00 97.98 0.00 100.00 0.00 100.00 0.00 99.71 0.00 99.70 0.15 100.00 0.00 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1191887976


Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1094881599
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.369348657
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1242735917
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2804568572
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2515756037
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.348113442
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3306312811
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2719125820
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3747711637
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1088790453
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1719286949
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.4023954558
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2091990901
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1739964545
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2476570408
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2100117365
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.488267104
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2826650064
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.650313587
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1970613563
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.4141812016
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2686221198
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.167100802
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2149219141
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1540561112
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3317898508
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3793138324
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2577587783
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3138520522
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1023795980
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1414395303
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2095161001
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3568051916
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2106938536
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1494368745
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3019660177
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3440197052
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1863960663
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.138865500
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2208318364
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3176287454
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1522865303
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.604444829
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1133381848
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3706176020
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.579294162
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.4078080866
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.839703274
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1882639375
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3906145155
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3458593857
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2373694817
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3549482257
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.334170472
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.68208195
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.417531667
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3104123573
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3408603734
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3807313016
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1304139466
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.427693786
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2484408166
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2708757564
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1366349417
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3771237397
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2438514903
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2349488447
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2144364934
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1785980893
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2384997939
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1606678196
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1051879356
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2817362173
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3521076961
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2184622625
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.249343325
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3278071552
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3620127277
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1749818249
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.883674441
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1248865341
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3149450531
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.994045914
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3936326067
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3923463508
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.4163821741
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.800355773
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3690977086
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.203724813
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2425179912
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.345507399
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3780801539
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3381838094
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1547780631
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3356776197
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2252462819
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3663825124
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3864616443
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2336147618
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1508829913
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1719834383
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.44360554
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3759728402
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1176572390
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.34552757
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1863137286
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.616611582
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3149949480
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1507212416
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2595059776
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1579448823
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2205501977
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.552072265
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1535258184
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.806565908
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1917881828
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1903005138
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1388691893
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1860918661
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1019666657
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2387881859
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2131404969
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3006319626
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3350284351
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.548458902
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3918557886
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.1274620772
/workspace/coverage/default/0.sram_ctrl_alert_test.540052504
/workspace/coverage/default/0.sram_ctrl_bijection.872720544
/workspace/coverage/default/0.sram_ctrl_lc_escalation.2784751360
/workspace/coverage/default/0.sram_ctrl_max_throughput.2307884060
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.191723626
/workspace/coverage/default/0.sram_ctrl_mem_walk.1767546528
/workspace/coverage/default/0.sram_ctrl_multiple_keys.997129049
/workspace/coverage/default/0.sram_ctrl_partial_access.3212887577
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.1439294004
/workspace/coverage/default/0.sram_ctrl_ram_cfg.462648484
/workspace/coverage/default/0.sram_ctrl_regwen.2928452543
/workspace/coverage/default/0.sram_ctrl_smoke.1398259638
/workspace/coverage/default/0.sram_ctrl_stress_all.4067851699
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.4232814767
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.4233716901
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.1692721595
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.3018692125
/workspace/coverage/default/1.sram_ctrl_bijection.2593717491
/workspace/coverage/default/1.sram_ctrl_max_throughput.3545467767
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.905484294
/workspace/coverage/default/1.sram_ctrl_mem_walk.1865622201
/workspace/coverage/default/1.sram_ctrl_multiple_keys.297962178
/workspace/coverage/default/1.sram_ctrl_partial_access.2936971784
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.1207703133
/workspace/coverage/default/1.sram_ctrl_ram_cfg.843487656
/workspace/coverage/default/1.sram_ctrl_regwen.3205216264
/workspace/coverage/default/1.sram_ctrl_sec_cm.3941481200
/workspace/coverage/default/1.sram_ctrl_smoke.1799264288
/workspace/coverage/default/1.sram_ctrl_stress_all.1606876688
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.654964474
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.1008442944
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.3553167637
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.763302532
/workspace/coverage/default/10.sram_ctrl_alert_test.3403327665
/workspace/coverage/default/10.sram_ctrl_bijection.4266992198
/workspace/coverage/default/10.sram_ctrl_executable.913063762
/workspace/coverage/default/10.sram_ctrl_max_throughput.3636432786
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.3178683416
/workspace/coverage/default/10.sram_ctrl_mem_walk.1338357036
/workspace/coverage/default/10.sram_ctrl_multiple_keys.3008947427
/workspace/coverage/default/10.sram_ctrl_partial_access.3629458997
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.1429488806
/workspace/coverage/default/10.sram_ctrl_ram_cfg.1821667050
/workspace/coverage/default/10.sram_ctrl_regwen.2437692711
/workspace/coverage/default/10.sram_ctrl_smoke.962708767
/workspace/coverage/default/10.sram_ctrl_stress_all.1804880124
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.465786670
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.3487077754
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.4253659043
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.2919067479
/workspace/coverage/default/11.sram_ctrl_alert_test.519452394
/workspace/coverage/default/11.sram_ctrl_bijection.1688602999
/workspace/coverage/default/11.sram_ctrl_executable.843659091
/workspace/coverage/default/11.sram_ctrl_max_throughput.1039954596
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.3878744346
/workspace/coverage/default/11.sram_ctrl_mem_walk.3940221246
/workspace/coverage/default/11.sram_ctrl_multiple_keys.4140640127
/workspace/coverage/default/11.sram_ctrl_partial_access.1067173630
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.934756139
/workspace/coverage/default/11.sram_ctrl_ram_cfg.2895892515
/workspace/coverage/default/11.sram_ctrl_regwen.3223554572
/workspace/coverage/default/11.sram_ctrl_smoke.1133640007
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.3088861192
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.2122676441
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.570463468
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.912210043
/workspace/coverage/default/12.sram_ctrl_alert_test.2368431177
/workspace/coverage/default/12.sram_ctrl_bijection.402609615
/workspace/coverage/default/12.sram_ctrl_lc_escalation.3991296232
/workspace/coverage/default/12.sram_ctrl_max_throughput.205546547
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.289813627
/workspace/coverage/default/12.sram_ctrl_mem_walk.2028521294
/workspace/coverage/default/12.sram_ctrl_multiple_keys.2601413027
/workspace/coverage/default/12.sram_ctrl_partial_access.1468604071
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.3479176637
/workspace/coverage/default/12.sram_ctrl_ram_cfg.879703148
/workspace/coverage/default/12.sram_ctrl_regwen.2555843922
/workspace/coverage/default/12.sram_ctrl_smoke.1947088718
/workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.4272143423
/workspace/coverage/default/12.sram_ctrl_stress_pipeline.1474515780
/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.1334053753
/workspace/coverage/default/13.sram_ctrl_access_during_key_req.531018322
/workspace/coverage/default/13.sram_ctrl_alert_test.453959174
/workspace/coverage/default/13.sram_ctrl_bijection.1703021864
/workspace/coverage/default/13.sram_ctrl_lc_escalation.2395919152
/workspace/coverage/default/13.sram_ctrl_max_throughput.4147088670
/workspace/coverage/default/13.sram_ctrl_mem_partial_access.298947928
/workspace/coverage/default/13.sram_ctrl_mem_walk.495069178
/workspace/coverage/default/13.sram_ctrl_multiple_keys.2940209503
/workspace/coverage/default/13.sram_ctrl_partial_access.3331255475
/workspace/coverage/default/13.sram_ctrl_partial_access_b2b.1647941095
/workspace/coverage/default/13.sram_ctrl_ram_cfg.1836186019
/workspace/coverage/default/13.sram_ctrl_regwen.3867640882
/workspace/coverage/default/13.sram_ctrl_smoke.385402294
/workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.1195030907
/workspace/coverage/default/13.sram_ctrl_stress_pipeline.515511919
/workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.419057275
/workspace/coverage/default/14.sram_ctrl_access_during_key_req.2938234892
/workspace/coverage/default/14.sram_ctrl_alert_test.148593827
/workspace/coverage/default/14.sram_ctrl_bijection.2131873546
/workspace/coverage/default/14.sram_ctrl_lc_escalation.3920341383
/workspace/coverage/default/14.sram_ctrl_max_throughput.2286465073
/workspace/coverage/default/14.sram_ctrl_mem_partial_access.917000498
/workspace/coverage/default/14.sram_ctrl_mem_walk.1877493735
/workspace/coverage/default/14.sram_ctrl_multiple_keys.3497508145
/workspace/coverage/default/14.sram_ctrl_partial_access.2265934626
/workspace/coverage/default/14.sram_ctrl_partial_access_b2b.3179542296
/workspace/coverage/default/14.sram_ctrl_ram_cfg.466463539
/workspace/coverage/default/14.sram_ctrl_regwen.4115412946
/workspace/coverage/default/14.sram_ctrl_smoke.1801975257
/workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.3570082278
/workspace/coverage/default/14.sram_ctrl_stress_pipeline.3053784112
/workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.4212848615
/workspace/coverage/default/15.sram_ctrl_access_during_key_req.3418955854
/workspace/coverage/default/15.sram_ctrl_alert_test.2054919032
/workspace/coverage/default/15.sram_ctrl_bijection.3579014040
/workspace/coverage/default/15.sram_ctrl_lc_escalation.3191675895
/workspace/coverage/default/15.sram_ctrl_max_throughput.1000318559
/workspace/coverage/default/15.sram_ctrl_mem_partial_access.4015748770
/workspace/coverage/default/15.sram_ctrl_mem_walk.2158925593
/workspace/coverage/default/15.sram_ctrl_multiple_keys.701946842
/workspace/coverage/default/15.sram_ctrl_partial_access.4248353347
/workspace/coverage/default/15.sram_ctrl_partial_access_b2b.2135056229
/workspace/coverage/default/15.sram_ctrl_ram_cfg.59428818
/workspace/coverage/default/15.sram_ctrl_regwen.1652510124
/workspace/coverage/default/15.sram_ctrl_smoke.1700930767
/workspace/coverage/default/15.sram_ctrl_stress_all.561884112
/workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.3688480437
/workspace/coverage/default/15.sram_ctrl_stress_pipeline.653648578
/workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.1897070652
/workspace/coverage/default/16.sram_ctrl_access_during_key_req.2662937369
/workspace/coverage/default/16.sram_ctrl_alert_test.2096903503
/workspace/coverage/default/16.sram_ctrl_bijection.3007765490
/workspace/coverage/default/16.sram_ctrl_lc_escalation.410110614
/workspace/coverage/default/16.sram_ctrl_max_throughput.4150137823
/workspace/coverage/default/16.sram_ctrl_mem_partial_access.321194888
/workspace/coverage/default/16.sram_ctrl_mem_walk.4161009375
/workspace/coverage/default/16.sram_ctrl_multiple_keys.1872141658
/workspace/coverage/default/16.sram_ctrl_partial_access.4167595816
/workspace/coverage/default/16.sram_ctrl_partial_access_b2b.3103577507
/workspace/coverage/default/16.sram_ctrl_ram_cfg.92254757
/workspace/coverage/default/16.sram_ctrl_regwen.1750265326
/workspace/coverage/default/16.sram_ctrl_smoke.2819614201
/workspace/coverage/default/16.sram_ctrl_stress_pipeline.2415183545
/workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.961852319
/workspace/coverage/default/17.sram_ctrl_access_during_key_req.2790583234
/workspace/coverage/default/17.sram_ctrl_alert_test.778691912
/workspace/coverage/default/17.sram_ctrl_bijection.796843239
/workspace/coverage/default/17.sram_ctrl_executable.2792804561
/workspace/coverage/default/17.sram_ctrl_lc_escalation.1366542909
/workspace/coverage/default/17.sram_ctrl_max_throughput.2506770028
/workspace/coverage/default/17.sram_ctrl_mem_partial_access.3437595391
/workspace/coverage/default/17.sram_ctrl_mem_walk.671352237
/workspace/coverage/default/17.sram_ctrl_multiple_keys.3106162155
/workspace/coverage/default/17.sram_ctrl_partial_access.2479542943
/workspace/coverage/default/17.sram_ctrl_partial_access_b2b.4156046991
/workspace/coverage/default/17.sram_ctrl_ram_cfg.2957469120
/workspace/coverage/default/17.sram_ctrl_regwen.2567893989
/workspace/coverage/default/17.sram_ctrl_smoke.1243636463
/workspace/coverage/default/17.sram_ctrl_stress_all.3484830138
/workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.168760242
/workspace/coverage/default/17.sram_ctrl_stress_pipeline.2807495941
/workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.1659747964
/workspace/coverage/default/18.sram_ctrl_access_during_key_req.277392574
/workspace/coverage/default/18.sram_ctrl_alert_test.1483857535
/workspace/coverage/default/18.sram_ctrl_bijection.3477433208
/workspace/coverage/default/18.sram_ctrl_lc_escalation.568863656
/workspace/coverage/default/18.sram_ctrl_max_throughput.1309787876
/workspace/coverage/default/18.sram_ctrl_mem_partial_access.1451391923
/workspace/coverage/default/18.sram_ctrl_mem_walk.1639565559
/workspace/coverage/default/18.sram_ctrl_multiple_keys.236369110
/workspace/coverage/default/18.sram_ctrl_partial_access.963776621
/workspace/coverage/default/18.sram_ctrl_partial_access_b2b.1846623128
/workspace/coverage/default/18.sram_ctrl_ram_cfg.875998916
/workspace/coverage/default/18.sram_ctrl_regwen.3913304365
/workspace/coverage/default/18.sram_ctrl_smoke.634781574
/workspace/coverage/default/18.sram_ctrl_stress_all.3842059303
/workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.2051202305
/workspace/coverage/default/18.sram_ctrl_stress_pipeline.4071922649
/workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.2675847624
/workspace/coverage/default/19.sram_ctrl_access_during_key_req.4076253261
/workspace/coverage/default/19.sram_ctrl_alert_test.2447753076
/workspace/coverage/default/19.sram_ctrl_bijection.108285201
/workspace/coverage/default/19.sram_ctrl_lc_escalation.1108163772
/workspace/coverage/default/19.sram_ctrl_max_throughput.2527225859
/workspace/coverage/default/19.sram_ctrl_mem_partial_access.2262636952
/workspace/coverage/default/19.sram_ctrl_mem_walk.2702957749
/workspace/coverage/default/19.sram_ctrl_multiple_keys.1733345997
/workspace/coverage/default/19.sram_ctrl_partial_access.862915909
/workspace/coverage/default/19.sram_ctrl_partial_access_b2b.154441281
/workspace/coverage/default/19.sram_ctrl_ram_cfg.57689411
/workspace/coverage/default/19.sram_ctrl_regwen.4198723071
/workspace/coverage/default/19.sram_ctrl_smoke.772761558
/workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.3344757235
/workspace/coverage/default/19.sram_ctrl_stress_pipeline.3101549507
/workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.1688871910
/workspace/coverage/default/2.sram_ctrl_access_during_key_req.1648353812
/workspace/coverage/default/2.sram_ctrl_alert_test.809028151
/workspace/coverage/default/2.sram_ctrl_bijection.1420765910
/workspace/coverage/default/2.sram_ctrl_executable.1939473767
/workspace/coverage/default/2.sram_ctrl_lc_escalation.2743508494
/workspace/coverage/default/2.sram_ctrl_max_throughput.2303067328
/workspace/coverage/default/2.sram_ctrl_mem_partial_access.2925145522
/workspace/coverage/default/2.sram_ctrl_mem_walk.2878538069
/workspace/coverage/default/2.sram_ctrl_multiple_keys.128965879
/workspace/coverage/default/2.sram_ctrl_partial_access.121017432
/workspace/coverage/default/2.sram_ctrl_partial_access_b2b.1842673625
/workspace/coverage/default/2.sram_ctrl_ram_cfg.1284554199
/workspace/coverage/default/2.sram_ctrl_regwen.2957333510
/workspace/coverage/default/2.sram_ctrl_sec_cm.518891795
/workspace/coverage/default/2.sram_ctrl_smoke.1291568786
/workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.1162066148
/workspace/coverage/default/2.sram_ctrl_stress_pipeline.1787848456
/workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.911838724
/workspace/coverage/default/20.sram_ctrl_access_during_key_req.444345011
/workspace/coverage/default/20.sram_ctrl_alert_test.422165128
/workspace/coverage/default/20.sram_ctrl_bijection.1315834364
/workspace/coverage/default/20.sram_ctrl_executable.3624574819
/workspace/coverage/default/20.sram_ctrl_lc_escalation.1294204499
/workspace/coverage/default/20.sram_ctrl_max_throughput.546806696
/workspace/coverage/default/20.sram_ctrl_mem_partial_access.4099979452
/workspace/coverage/default/20.sram_ctrl_mem_walk.739160195
/workspace/coverage/default/20.sram_ctrl_partial_access.3136249612
/workspace/coverage/default/20.sram_ctrl_partial_access_b2b.1685912429
/workspace/coverage/default/20.sram_ctrl_ram_cfg.4112397412
/workspace/coverage/default/20.sram_ctrl_regwen.3606592222
/workspace/coverage/default/20.sram_ctrl_smoke.1092858295
/workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.3321023334
/workspace/coverage/default/20.sram_ctrl_stress_pipeline.1461818789
/workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.1943081127
/workspace/coverage/default/21.sram_ctrl_access_during_key_req.3629603006
/workspace/coverage/default/21.sram_ctrl_alert_test.4212583212
/workspace/coverage/default/21.sram_ctrl_bijection.3876593511
/workspace/coverage/default/21.sram_ctrl_max_throughput.882471632
/workspace/coverage/default/21.sram_ctrl_mem_partial_access.462547267
/workspace/coverage/default/21.sram_ctrl_mem_walk.2874380653
/workspace/coverage/default/21.sram_ctrl_multiple_keys.3099661077
/workspace/coverage/default/21.sram_ctrl_partial_access.1652890199
/workspace/coverage/default/21.sram_ctrl_partial_access_b2b.821309773
/workspace/coverage/default/21.sram_ctrl_regwen.2536475031
/workspace/coverage/default/21.sram_ctrl_smoke.1053697684
/workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.3492310379
/workspace/coverage/default/21.sram_ctrl_stress_pipeline.2814274434
/workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.3596999552
/workspace/coverage/default/22.sram_ctrl_access_during_key_req.1109512429
/workspace/coverage/default/22.sram_ctrl_alert_test.215790581
/workspace/coverage/default/22.sram_ctrl_bijection.2726749456
/workspace/coverage/default/22.sram_ctrl_lc_escalation.1869312863
/workspace/coverage/default/22.sram_ctrl_max_throughput.4124180784
/workspace/coverage/default/22.sram_ctrl_mem_partial_access.3682435805
/workspace/coverage/default/22.sram_ctrl_mem_walk.3727570037
/workspace/coverage/default/22.sram_ctrl_multiple_keys.109389419
/workspace/coverage/default/22.sram_ctrl_partial_access.3399442578
/workspace/coverage/default/22.sram_ctrl_partial_access_b2b.2049169506
/workspace/coverage/default/22.sram_ctrl_ram_cfg.2793670600
/workspace/coverage/default/22.sram_ctrl_regwen.3455495496
/workspace/coverage/default/22.sram_ctrl_smoke.456284617
/workspace/coverage/default/22.sram_ctrl_stress_all.3500340993
/workspace/coverage/default/22.sram_ctrl_stress_pipeline.226034646
/workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.3006103750
/workspace/coverage/default/23.sram_ctrl_access_during_key_req.52349846
/workspace/coverage/default/23.sram_ctrl_alert_test.3560949821
/workspace/coverage/default/23.sram_ctrl_bijection.2716785070
/workspace/coverage/default/23.sram_ctrl_executable.1310307811
/workspace/coverage/default/23.sram_ctrl_lc_escalation.3545914004
/workspace/coverage/default/23.sram_ctrl_max_throughput.1324848539
/workspace/coverage/default/23.sram_ctrl_mem_partial_access.127972534
/workspace/coverage/default/23.sram_ctrl_mem_walk.380369691
/workspace/coverage/default/23.sram_ctrl_multiple_keys.2731993829
/workspace/coverage/default/23.sram_ctrl_partial_access.2708601841
/workspace/coverage/default/23.sram_ctrl_partial_access_b2b.2425021225
/workspace/coverage/default/23.sram_ctrl_ram_cfg.2741897903
/workspace/coverage/default/23.sram_ctrl_regwen.3822088223
/workspace/coverage/default/23.sram_ctrl_smoke.2392343287
/workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.352940876
/workspace/coverage/default/23.sram_ctrl_stress_pipeline.2497122425
/workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.1081356584
/workspace/coverage/default/24.sram_ctrl_access_during_key_req.2913966122
/workspace/coverage/default/24.sram_ctrl_alert_test.107376225
/workspace/coverage/default/24.sram_ctrl_bijection.110874697
/workspace/coverage/default/24.sram_ctrl_lc_escalation.621439699
/workspace/coverage/default/24.sram_ctrl_max_throughput.2305151345
/workspace/coverage/default/24.sram_ctrl_mem_partial_access.2957576149
/workspace/coverage/default/24.sram_ctrl_mem_walk.1680551080
/workspace/coverage/default/24.sram_ctrl_multiple_keys.4183449857
/workspace/coverage/default/24.sram_ctrl_partial_access.889770963
/workspace/coverage/default/24.sram_ctrl_partial_access_b2b.3593370996
/workspace/coverage/default/24.sram_ctrl_ram_cfg.495030774
/workspace/coverage/default/24.sram_ctrl_regwen.3115576737
/workspace/coverage/default/24.sram_ctrl_smoke.4216941143
/workspace/coverage/default/24.sram_ctrl_stress_all.3350964859
/workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.245339946
/workspace/coverage/default/24.sram_ctrl_stress_pipeline.2655369233
/workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.4271565423
/workspace/coverage/default/25.sram_ctrl_access_during_key_req.1412177269
/workspace/coverage/default/25.sram_ctrl_alert_test.463210605
/workspace/coverage/default/25.sram_ctrl_bijection.1630761648
/workspace/coverage/default/25.sram_ctrl_lc_escalation.4286044717
/workspace/coverage/default/25.sram_ctrl_max_throughput.215286322
/workspace/coverage/default/25.sram_ctrl_mem_partial_access.1012932154
/workspace/coverage/default/25.sram_ctrl_mem_walk.2802835109
/workspace/coverage/default/25.sram_ctrl_multiple_keys.297726748
/workspace/coverage/default/25.sram_ctrl_partial_access.3324929091
/workspace/coverage/default/25.sram_ctrl_partial_access_b2b.3486041028
/workspace/coverage/default/25.sram_ctrl_ram_cfg.1632326401
/workspace/coverage/default/25.sram_ctrl_regwen.403336501
/workspace/coverage/default/25.sram_ctrl_smoke.1086899563
/workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.3970481792
/workspace/coverage/default/25.sram_ctrl_stress_pipeline.93781670
/workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.1160673942
/workspace/coverage/default/26.sram_ctrl_access_during_key_req.4270480009
/workspace/coverage/default/26.sram_ctrl_alert_test.3938784278
/workspace/coverage/default/26.sram_ctrl_bijection.3015993934
/workspace/coverage/default/26.sram_ctrl_executable.3405011723
/workspace/coverage/default/26.sram_ctrl_lc_escalation.3810369272
/workspace/coverage/default/26.sram_ctrl_max_throughput.2836661654
/workspace/coverage/default/26.sram_ctrl_mem_partial_access.1765527886
/workspace/coverage/default/26.sram_ctrl_mem_walk.167193726
/workspace/coverage/default/26.sram_ctrl_multiple_keys.3902248649
/workspace/coverage/default/26.sram_ctrl_partial_access.2713011030
/workspace/coverage/default/26.sram_ctrl_partial_access_b2b.2230547537
/workspace/coverage/default/26.sram_ctrl_ram_cfg.1620071438
/workspace/coverage/default/26.sram_ctrl_regwen.3350349993
/workspace/coverage/default/26.sram_ctrl_smoke.40827714
/workspace/coverage/default/26.sram_ctrl_stress_all.2876793490
/workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.2568386962
/workspace/coverage/default/26.sram_ctrl_stress_pipeline.2658568810
/workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.462908943
/workspace/coverage/default/27.sram_ctrl_access_during_key_req.3428166002
/workspace/coverage/default/27.sram_ctrl_alert_test.3845306343
/workspace/coverage/default/27.sram_ctrl_bijection.4043366222
/workspace/coverage/default/27.sram_ctrl_executable.1797170336
/workspace/coverage/default/27.sram_ctrl_lc_escalation.3359198427
/workspace/coverage/default/27.sram_ctrl_max_throughput.3827506917
/workspace/coverage/default/27.sram_ctrl_mem_partial_access.490534951
/workspace/coverage/default/27.sram_ctrl_mem_walk.1250506080
/workspace/coverage/default/27.sram_ctrl_multiple_keys.2182262859
/workspace/coverage/default/27.sram_ctrl_partial_access.1647858543
/workspace/coverage/default/27.sram_ctrl_ram_cfg.80573566
/workspace/coverage/default/27.sram_ctrl_regwen.1001666218
/workspace/coverage/default/27.sram_ctrl_smoke.3820405723
/workspace/coverage/default/27.sram_ctrl_stress_all.1731277902
/workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.4177224918
/workspace/coverage/default/27.sram_ctrl_stress_pipeline.4000281805
/workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.2874650838
/workspace/coverage/default/28.sram_ctrl_access_during_key_req.1713657898
/workspace/coverage/default/28.sram_ctrl_alert_test.1647623587
/workspace/coverage/default/28.sram_ctrl_bijection.4060467941
/workspace/coverage/default/28.sram_ctrl_executable.733400138
/workspace/coverage/default/28.sram_ctrl_max_throughput.3945862077
/workspace/coverage/default/28.sram_ctrl_mem_partial_access.623859983
/workspace/coverage/default/28.sram_ctrl_mem_walk.3031553319
/workspace/coverage/default/28.sram_ctrl_multiple_keys.4171377026
/workspace/coverage/default/28.sram_ctrl_partial_access.3883598921
/workspace/coverage/default/28.sram_ctrl_partial_access_b2b.3060319359
/workspace/coverage/default/28.sram_ctrl_ram_cfg.3170490346
/workspace/coverage/default/28.sram_ctrl_regwen.2023337552
/workspace/coverage/default/28.sram_ctrl_smoke.1972124904
/workspace/coverage/default/28.sram_ctrl_stress_all.3720156750
/workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.1901554199
/workspace/coverage/default/28.sram_ctrl_stress_pipeline.3093714297
/workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.82294278
/workspace/coverage/default/29.sram_ctrl_access_during_key_req.2301359695
/workspace/coverage/default/29.sram_ctrl_alert_test.1898653993
/workspace/coverage/default/29.sram_ctrl_bijection.3593361024
/workspace/coverage/default/29.sram_ctrl_lc_escalation.2535022422
/workspace/coverage/default/29.sram_ctrl_max_throughput.965737893
/workspace/coverage/default/29.sram_ctrl_mem_partial_access.2300050253
/workspace/coverage/default/29.sram_ctrl_mem_walk.807504136
/workspace/coverage/default/29.sram_ctrl_multiple_keys.1158079523
/workspace/coverage/default/29.sram_ctrl_partial_access.3925323501
/workspace/coverage/default/29.sram_ctrl_partial_access_b2b.3231616476
/workspace/coverage/default/29.sram_ctrl_ram_cfg.640729002
/workspace/coverage/default/29.sram_ctrl_regwen.967841612
/workspace/coverage/default/29.sram_ctrl_smoke.3193496181
/workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.1070193829
/workspace/coverage/default/29.sram_ctrl_stress_pipeline.1472638472
/workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.376301187
/workspace/coverage/default/3.sram_ctrl_access_during_key_req.255222714
/workspace/coverage/default/3.sram_ctrl_alert_test.221509225
/workspace/coverage/default/3.sram_ctrl_bijection.384017241
/workspace/coverage/default/3.sram_ctrl_lc_escalation.1993383835
/workspace/coverage/default/3.sram_ctrl_max_throughput.1713603818
/workspace/coverage/default/3.sram_ctrl_mem_partial_access.197826165
/workspace/coverage/default/3.sram_ctrl_mem_walk.3398923337
/workspace/coverage/default/3.sram_ctrl_multiple_keys.2044512570
/workspace/coverage/default/3.sram_ctrl_partial_access.2537365167
/workspace/coverage/default/3.sram_ctrl_partial_access_b2b.3600766336
/workspace/coverage/default/3.sram_ctrl_ram_cfg.305839289
/workspace/coverage/default/3.sram_ctrl_regwen.823406606
/workspace/coverage/default/3.sram_ctrl_sec_cm.2624728443
/workspace/coverage/default/3.sram_ctrl_smoke.4220007099
/workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.3451018368
/workspace/coverage/default/3.sram_ctrl_stress_pipeline.1731656714
/workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.3104218118
/workspace/coverage/default/30.sram_ctrl_access_during_key_req.4257183516
/workspace/coverage/default/30.sram_ctrl_alert_test.1707058110
/workspace/coverage/default/30.sram_ctrl_bijection.3402728776
/workspace/coverage/default/30.sram_ctrl_lc_escalation.526128540
/workspace/coverage/default/30.sram_ctrl_max_throughput.3432559180
/workspace/coverage/default/30.sram_ctrl_mem_partial_access.2424076251
/workspace/coverage/default/30.sram_ctrl_mem_walk.1810583323
/workspace/coverage/default/30.sram_ctrl_multiple_keys.2271842047
/workspace/coverage/default/30.sram_ctrl_partial_access.1154807876
/workspace/coverage/default/30.sram_ctrl_partial_access_b2b.2910372063
/workspace/coverage/default/30.sram_ctrl_ram_cfg.469643537
/workspace/coverage/default/30.sram_ctrl_regwen.4111841495
/workspace/coverage/default/30.sram_ctrl_smoke.2746479351
/workspace/coverage/default/30.sram_ctrl_stress_all.3278356254
/workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.3910540943
/workspace/coverage/default/30.sram_ctrl_stress_pipeline.2074512022
/workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.769727990
/workspace/coverage/default/31.sram_ctrl_access_during_key_req.855507925
/workspace/coverage/default/31.sram_ctrl_alert_test.2523105420
/workspace/coverage/default/31.sram_ctrl_bijection.3227841981
/workspace/coverage/default/31.sram_ctrl_executable.3882025146
/workspace/coverage/default/31.sram_ctrl_lc_escalation.2546177096
/workspace/coverage/default/31.sram_ctrl_max_throughput.1398963447
/workspace/coverage/default/31.sram_ctrl_mem_partial_access.1173578586
/workspace/coverage/default/31.sram_ctrl_mem_walk.2105427602
/workspace/coverage/default/31.sram_ctrl_multiple_keys.384810884
/workspace/coverage/default/31.sram_ctrl_partial_access.11901568
/workspace/coverage/default/31.sram_ctrl_partial_access_b2b.2924116031
/workspace/coverage/default/31.sram_ctrl_ram_cfg.3091572022
/workspace/coverage/default/31.sram_ctrl_regwen.1808739714
/workspace/coverage/default/31.sram_ctrl_smoke.3060458061
/workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.156660631
/workspace/coverage/default/31.sram_ctrl_stress_pipeline.1112814366
/workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.200725699
/workspace/coverage/default/32.sram_ctrl_access_during_key_req.3828303930
/workspace/coverage/default/32.sram_ctrl_alert_test.285217299
/workspace/coverage/default/32.sram_ctrl_bijection.50310491
/workspace/coverage/default/32.sram_ctrl_lc_escalation.289196547
/workspace/coverage/default/32.sram_ctrl_max_throughput.1441150375
/workspace/coverage/default/32.sram_ctrl_mem_partial_access.3600699664
/workspace/coverage/default/32.sram_ctrl_mem_walk.356183264
/workspace/coverage/default/32.sram_ctrl_multiple_keys.1600024873
/workspace/coverage/default/32.sram_ctrl_partial_access.2656149272
/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.1934619835
/workspace/coverage/default/32.sram_ctrl_ram_cfg.2235538519
/workspace/coverage/default/32.sram_ctrl_regwen.508542335
/workspace/coverage/default/32.sram_ctrl_smoke.987121202
/workspace/coverage/default/32.sram_ctrl_stress_all.2845123873
/workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.2265506046
/workspace/coverage/default/32.sram_ctrl_stress_pipeline.3268088603
/workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.892614590
/workspace/coverage/default/33.sram_ctrl_access_during_key_req.5756475
/workspace/coverage/default/33.sram_ctrl_alert_test.4144911199
/workspace/coverage/default/33.sram_ctrl_bijection.3227649222
/workspace/coverage/default/33.sram_ctrl_max_throughput.2157998417
/workspace/coverage/default/33.sram_ctrl_mem_partial_access.3545918587
/workspace/coverage/default/33.sram_ctrl_mem_walk.2742481631
/workspace/coverage/default/33.sram_ctrl_multiple_keys.1752820122
/workspace/coverage/default/33.sram_ctrl_partial_access.3864352726
/workspace/coverage/default/33.sram_ctrl_partial_access_b2b.4088718193
/workspace/coverage/default/33.sram_ctrl_ram_cfg.449823531
/workspace/coverage/default/33.sram_ctrl_regwen.1468301971
/workspace/coverage/default/33.sram_ctrl_smoke.3287539563
/workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.1593576680
/workspace/coverage/default/33.sram_ctrl_stress_pipeline.3079003299
/workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.923235334
/workspace/coverage/default/34.sram_ctrl_access_during_key_req.3540927880
/workspace/coverage/default/34.sram_ctrl_alert_test.1216387038
/workspace/coverage/default/34.sram_ctrl_bijection.3558505692
/workspace/coverage/default/34.sram_ctrl_lc_escalation.3315560133
/workspace/coverage/default/34.sram_ctrl_max_throughput.2450588319
/workspace/coverage/default/34.sram_ctrl_mem_partial_access.811775967
/workspace/coverage/default/34.sram_ctrl_mem_walk.2629864615
/workspace/coverage/default/34.sram_ctrl_multiple_keys.3999331031
/workspace/coverage/default/34.sram_ctrl_partial_access.2906422830
/workspace/coverage/default/34.sram_ctrl_partial_access_b2b.3156435081
/workspace/coverage/default/34.sram_ctrl_ram_cfg.1723735345
/workspace/coverage/default/34.sram_ctrl_regwen.2864799389
/workspace/coverage/default/34.sram_ctrl_smoke.2285987898
/workspace/coverage/default/34.sram_ctrl_stress_all.4240220375
/workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.1101542828
/workspace/coverage/default/34.sram_ctrl_stress_pipeline.2670680826
/workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.3292759344
/workspace/coverage/default/35.sram_ctrl_access_during_key_req.3851096213
/workspace/coverage/default/35.sram_ctrl_alert_test.1017778775
/workspace/coverage/default/35.sram_ctrl_bijection.2078688253
/workspace/coverage/default/35.sram_ctrl_executable.4204581356
/workspace/coverage/default/35.sram_ctrl_lc_escalation.2949890749
/workspace/coverage/default/35.sram_ctrl_max_throughput.3247735610
/workspace/coverage/default/35.sram_ctrl_mem_partial_access.1693633543
/workspace/coverage/default/35.sram_ctrl_mem_walk.879791104
/workspace/coverage/default/35.sram_ctrl_multiple_keys.1535472880
/workspace/coverage/default/35.sram_ctrl_partial_access.1320271390
/workspace/coverage/default/35.sram_ctrl_partial_access_b2b.3074700497
/workspace/coverage/default/35.sram_ctrl_ram_cfg.2663850238
/workspace/coverage/default/35.sram_ctrl_regwen.3293730094
/workspace/coverage/default/35.sram_ctrl_smoke.225228614
/workspace/coverage/default/35.sram_ctrl_stress_all.1827176893
/workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.2517177214
/workspace/coverage/default/35.sram_ctrl_stress_pipeline.2749337298
/workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.471442819
/workspace/coverage/default/36.sram_ctrl_access_during_key_req.228113272
/workspace/coverage/default/36.sram_ctrl_alert_test.337780505
/workspace/coverage/default/36.sram_ctrl_bijection.2079434635
/workspace/coverage/default/36.sram_ctrl_lc_escalation.2459264684
/workspace/coverage/default/36.sram_ctrl_max_throughput.3418971482
/workspace/coverage/default/36.sram_ctrl_mem_partial_access.2732114896
/workspace/coverage/default/36.sram_ctrl_mem_walk.1838776846
/workspace/coverage/default/36.sram_ctrl_multiple_keys.1069191521
/workspace/coverage/default/36.sram_ctrl_partial_access.2879902511
/workspace/coverage/default/36.sram_ctrl_partial_access_b2b.3881915805
/workspace/coverage/default/36.sram_ctrl_ram_cfg.692760963
/workspace/coverage/default/36.sram_ctrl_regwen.1003453326
/workspace/coverage/default/36.sram_ctrl_smoke.656948911
/workspace/coverage/default/36.sram_ctrl_stress_all.2304950716
/workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.2053316295
/workspace/coverage/default/36.sram_ctrl_stress_pipeline.702429421
/workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.563439882
/workspace/coverage/default/37.sram_ctrl_access_during_key_req.1548416802
/workspace/coverage/default/37.sram_ctrl_alert_test.698622887
/workspace/coverage/default/37.sram_ctrl_bijection.3570397998
/workspace/coverage/default/37.sram_ctrl_lc_escalation.4143902268
/workspace/coverage/default/37.sram_ctrl_max_throughput.2956668169
/workspace/coverage/default/37.sram_ctrl_mem_partial_access.711605425
/workspace/coverage/default/37.sram_ctrl_mem_walk.3030518479
/workspace/coverage/default/37.sram_ctrl_multiple_keys.3445021797
/workspace/coverage/default/37.sram_ctrl_partial_access.1970568654
/workspace/coverage/default/37.sram_ctrl_partial_access_b2b.2530321074
/workspace/coverage/default/37.sram_ctrl_ram_cfg.1446754657
/workspace/coverage/default/37.sram_ctrl_regwen.1405007457
/workspace/coverage/default/37.sram_ctrl_smoke.1929444666
/workspace/coverage/default/37.sram_ctrl_stress_all.173411830
/workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.3165649599
/workspace/coverage/default/37.sram_ctrl_stress_pipeline.4059286352
/workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.100665017
/workspace/coverage/default/38.sram_ctrl_access_during_key_req.555121473
/workspace/coverage/default/38.sram_ctrl_alert_test.1015848929
/workspace/coverage/default/38.sram_ctrl_bijection.2109459875
/workspace/coverage/default/38.sram_ctrl_executable.2451398412
/workspace/coverage/default/38.sram_ctrl_lc_escalation.3329120489
/workspace/coverage/default/38.sram_ctrl_max_throughput.2444584936
/workspace/coverage/default/38.sram_ctrl_mem_partial_access.3254947094
/workspace/coverage/default/38.sram_ctrl_mem_walk.2321029919
/workspace/coverage/default/38.sram_ctrl_multiple_keys.4285717435
/workspace/coverage/default/38.sram_ctrl_partial_access.824466833
/workspace/coverage/default/38.sram_ctrl_partial_access_b2b.806011229
/workspace/coverage/default/38.sram_ctrl_ram_cfg.2955557239
/workspace/coverage/default/38.sram_ctrl_regwen.1912181753
/workspace/coverage/default/38.sram_ctrl_smoke.2799694839
/workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.1209783119
/workspace/coverage/default/38.sram_ctrl_stress_pipeline.2939491386
/workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.1577218502
/workspace/coverage/default/39.sram_ctrl_access_during_key_req.3495545431
/workspace/coverage/default/39.sram_ctrl_alert_test.122923526
/workspace/coverage/default/39.sram_ctrl_bijection.2401116505
/workspace/coverage/default/39.sram_ctrl_executable.2038752890
/workspace/coverage/default/39.sram_ctrl_lc_escalation.407833130
/workspace/coverage/default/39.sram_ctrl_max_throughput.907433490
/workspace/coverage/default/39.sram_ctrl_mem_partial_access.4149336201
/workspace/coverage/default/39.sram_ctrl_mem_walk.2387966465
/workspace/coverage/default/39.sram_ctrl_multiple_keys.1323000499
/workspace/coverage/default/39.sram_ctrl_partial_access.544637990
/workspace/coverage/default/39.sram_ctrl_partial_access_b2b.69083796
/workspace/coverage/default/39.sram_ctrl_ram_cfg.1816032472
/workspace/coverage/default/39.sram_ctrl_regwen.2424027733
/workspace/coverage/default/39.sram_ctrl_smoke.3840049788
/workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.1290980409
/workspace/coverage/default/39.sram_ctrl_stress_pipeline.3128695338
/workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.1734046344
/workspace/coverage/default/4.sram_ctrl_access_during_key_req.427054960
/workspace/coverage/default/4.sram_ctrl_alert_test.1511612671
/workspace/coverage/default/4.sram_ctrl_bijection.67506215
/workspace/coverage/default/4.sram_ctrl_lc_escalation.515633550
/workspace/coverage/default/4.sram_ctrl_max_throughput.2688720997
/workspace/coverage/default/4.sram_ctrl_mem_partial_access.3060744791
/workspace/coverage/default/4.sram_ctrl_mem_walk.3632536734
/workspace/coverage/default/4.sram_ctrl_multiple_keys.839265826
/workspace/coverage/default/4.sram_ctrl_partial_access.331135829
/workspace/coverage/default/4.sram_ctrl_partial_access_b2b.2731652989
/workspace/coverage/default/4.sram_ctrl_ram_cfg.1883811464
/workspace/coverage/default/4.sram_ctrl_regwen.1836636357
/workspace/coverage/default/4.sram_ctrl_sec_cm.1797404151
/workspace/coverage/default/4.sram_ctrl_smoke.1936590388
/workspace/coverage/default/4.sram_ctrl_stress_all.2913308319
/workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.2296947248
/workspace/coverage/default/4.sram_ctrl_stress_pipeline.211397883
/workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.936089178
/workspace/coverage/default/40.sram_ctrl_access_during_key_req.2736403842
/workspace/coverage/default/40.sram_ctrl_alert_test.2312384652
/workspace/coverage/default/40.sram_ctrl_bijection.440179957
/workspace/coverage/default/40.sram_ctrl_executable.2182824219
/workspace/coverage/default/40.sram_ctrl_max_throughput.694626363
/workspace/coverage/default/40.sram_ctrl_mem_partial_access.1690232479
/workspace/coverage/default/40.sram_ctrl_mem_walk.1223882983
/workspace/coverage/default/40.sram_ctrl_multiple_keys.124472746
/workspace/coverage/default/40.sram_ctrl_partial_access.2851157127
/workspace/coverage/default/40.sram_ctrl_partial_access_b2b.2622172656
/workspace/coverage/default/40.sram_ctrl_ram_cfg.1981976741
/workspace/coverage/default/40.sram_ctrl_regwen.3981265627
/workspace/coverage/default/40.sram_ctrl_smoke.4220321210
/workspace/coverage/default/40.sram_ctrl_stress_all.2604111742
/workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.2954702336
/workspace/coverage/default/40.sram_ctrl_stress_pipeline.1982096063
/workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.880102866
/workspace/coverage/default/41.sram_ctrl_access_during_key_req.485864652
/workspace/coverage/default/41.sram_ctrl_alert_test.3938253445
/workspace/coverage/default/41.sram_ctrl_bijection.730281498
/workspace/coverage/default/41.sram_ctrl_executable.735436767
/workspace/coverage/default/41.sram_ctrl_lc_escalation.15697656
/workspace/coverage/default/41.sram_ctrl_max_throughput.4092877537
/workspace/coverage/default/41.sram_ctrl_mem_partial_access.4088504497
/workspace/coverage/default/41.sram_ctrl_mem_walk.2932718476
/workspace/coverage/default/41.sram_ctrl_multiple_keys.3017886594
/workspace/coverage/default/41.sram_ctrl_partial_access.3160206342
/workspace/coverage/default/41.sram_ctrl_partial_access_b2b.2464960611
/workspace/coverage/default/41.sram_ctrl_ram_cfg.958560723
/workspace/coverage/default/41.sram_ctrl_regwen.2986502320
/workspace/coverage/default/41.sram_ctrl_smoke.4134884680
/workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.1137780619
/workspace/coverage/default/41.sram_ctrl_stress_pipeline.3465502229
/workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.1029167873
/workspace/coverage/default/42.sram_ctrl_access_during_key_req.1040813519
/workspace/coverage/default/42.sram_ctrl_alert_test.2094561755
/workspace/coverage/default/42.sram_ctrl_bijection.1527224968
/workspace/coverage/default/42.sram_ctrl_lc_escalation.3458807082
/workspace/coverage/default/42.sram_ctrl_max_throughput.1544680158
/workspace/coverage/default/42.sram_ctrl_mem_partial_access.106988317
/workspace/coverage/default/42.sram_ctrl_mem_walk.1382673979
/workspace/coverage/default/42.sram_ctrl_multiple_keys.1439858432
/workspace/coverage/default/42.sram_ctrl_partial_access.2495983039
/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.2739493938
/workspace/coverage/default/42.sram_ctrl_ram_cfg.3740878348
/workspace/coverage/default/42.sram_ctrl_regwen.769383461
/workspace/coverage/default/42.sram_ctrl_smoke.2765140576
/workspace/coverage/default/42.sram_ctrl_stress_all.1993875935
/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.2646492233
/workspace/coverage/default/42.sram_ctrl_stress_pipeline.717539411
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.1978392795
/workspace/coverage/default/43.sram_ctrl_access_during_key_req.2803936362
/workspace/coverage/default/43.sram_ctrl_alert_test.3609863076
/workspace/coverage/default/43.sram_ctrl_bijection.3185751174
/workspace/coverage/default/43.sram_ctrl_lc_escalation.3856307305
/workspace/coverage/default/43.sram_ctrl_max_throughput.675359954
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.2037044482
/workspace/coverage/default/43.sram_ctrl_mem_walk.774188634
/workspace/coverage/default/43.sram_ctrl_multiple_keys.4209148328
/workspace/coverage/default/43.sram_ctrl_partial_access.4125273109
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.83011887
/workspace/coverage/default/43.sram_ctrl_ram_cfg.3381639531
/workspace/coverage/default/43.sram_ctrl_regwen.100298380
/workspace/coverage/default/43.sram_ctrl_smoke.4004797889
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.2954327544
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.999821077
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.3092248122
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.3009496244
/workspace/coverage/default/44.sram_ctrl_alert_test.3914578354
/workspace/coverage/default/44.sram_ctrl_bijection.1140392611
/workspace/coverage/default/44.sram_ctrl_lc_escalation.3022186266
/workspace/coverage/default/44.sram_ctrl_max_throughput.3239593177
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.1479878060
/workspace/coverage/default/44.sram_ctrl_mem_walk.3839305392
/workspace/coverage/default/44.sram_ctrl_multiple_keys.2952992496
/workspace/coverage/default/44.sram_ctrl_partial_access.3464993423
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.436274894
/workspace/coverage/default/44.sram_ctrl_ram_cfg.2114290843
/workspace/coverage/default/44.sram_ctrl_regwen.1211927366
/workspace/coverage/default/44.sram_ctrl_smoke.2189088882
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.587689187
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.717617750
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.1055603694
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.2195346469
/workspace/coverage/default/45.sram_ctrl_alert_test.2913716949
/workspace/coverage/default/45.sram_ctrl_bijection.3570823034
/workspace/coverage/default/45.sram_ctrl_executable.1608166710
/workspace/coverage/default/45.sram_ctrl_lc_escalation.332945281
/workspace/coverage/default/45.sram_ctrl_max_throughput.4070665167
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.3190836017
/workspace/coverage/default/45.sram_ctrl_mem_walk.549714651
/workspace/coverage/default/45.sram_ctrl_multiple_keys.3637651719
/workspace/coverage/default/45.sram_ctrl_partial_access.2954491529
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.3378415371
/workspace/coverage/default/45.sram_ctrl_ram_cfg.2821000459
/workspace/coverage/default/45.sram_ctrl_regwen.2248426700
/workspace/coverage/default/45.sram_ctrl_smoke.925201667
/workspace/coverage/default/45.sram_ctrl_stress_all.45465246
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.3497362208
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.1283397789
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.3395989382
/workspace/coverage/default/46.sram_ctrl_alert_test.1389187344
/workspace/coverage/default/46.sram_ctrl_executable.2035934843
/workspace/coverage/default/46.sram_ctrl_lc_escalation.1838619157
/workspace/coverage/default/46.sram_ctrl_max_throughput.581560304
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.4082324526
/workspace/coverage/default/46.sram_ctrl_mem_walk.2183199816
/workspace/coverage/default/46.sram_ctrl_multiple_keys.332849608
/workspace/coverage/default/46.sram_ctrl_partial_access.3562672147
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.336249857
/workspace/coverage/default/46.sram_ctrl_ram_cfg.3236246646
/workspace/coverage/default/46.sram_ctrl_smoke.3406060038
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3988417956
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.2454841726
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.3657400548
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.676710852
/workspace/coverage/default/47.sram_ctrl_alert_test.3894157669
/workspace/coverage/default/47.sram_ctrl_bijection.3483911329
/workspace/coverage/default/47.sram_ctrl_executable.4006833649
/workspace/coverage/default/47.sram_ctrl_lc_escalation.3771282279
/workspace/coverage/default/47.sram_ctrl_max_throughput.1815335609
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.2785378907
/workspace/coverage/default/47.sram_ctrl_mem_walk.959234267
/workspace/coverage/default/47.sram_ctrl_multiple_keys.1101862132
/workspace/coverage/default/47.sram_ctrl_partial_access.2998660946
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.1130993828
/workspace/coverage/default/47.sram_ctrl_ram_cfg.1168228752
/workspace/coverage/default/47.sram_ctrl_regwen.4022753151
/workspace/coverage/default/47.sram_ctrl_smoke.3234634123
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.2782809888
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.1374779581
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.3607022907
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.657260832
/workspace/coverage/default/48.sram_ctrl_alert_test.3095525380
/workspace/coverage/default/48.sram_ctrl_bijection.65674261
/workspace/coverage/default/48.sram_ctrl_lc_escalation.3026860455
/workspace/coverage/default/48.sram_ctrl_max_throughput.4277632440
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.2291229271
/workspace/coverage/default/48.sram_ctrl_mem_walk.3713918954
/workspace/coverage/default/48.sram_ctrl_multiple_keys.3071560478
/workspace/coverage/default/48.sram_ctrl_partial_access.2594445303
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.2152457775
/workspace/coverage/default/48.sram_ctrl_ram_cfg.1698453089
/workspace/coverage/default/48.sram_ctrl_regwen.2830182696
/workspace/coverage/default/48.sram_ctrl_smoke.1466954227
/workspace/coverage/default/48.sram_ctrl_stress_all.1726070615
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.1065907365
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.3134075673
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.1074582904
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.1376858347
/workspace/coverage/default/49.sram_ctrl_alert_test.1719809700
/workspace/coverage/default/49.sram_ctrl_bijection.1518977771
/workspace/coverage/default/49.sram_ctrl_lc_escalation.1956263053
/workspace/coverage/default/49.sram_ctrl_max_throughput.1124014047
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.17526198
/workspace/coverage/default/49.sram_ctrl_mem_walk.2678014047
/workspace/coverage/default/49.sram_ctrl_multiple_keys.1397608342
/workspace/coverage/default/49.sram_ctrl_partial_access.1608513945
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.1130539009
/workspace/coverage/default/49.sram_ctrl_ram_cfg.802005859
/workspace/coverage/default/49.sram_ctrl_regwen.3618026463
/workspace/coverage/default/49.sram_ctrl_smoke.3321311697
/workspace/coverage/default/49.sram_ctrl_stress_all.105687938
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.4200582765
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.970458381
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.2668364483
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.1393362631
/workspace/coverage/default/5.sram_ctrl_alert_test.2553671348
/workspace/coverage/default/5.sram_ctrl_bijection.1481760605
/workspace/coverage/default/5.sram_ctrl_executable.2788242536
/workspace/coverage/default/5.sram_ctrl_lc_escalation.2149471632
/workspace/coverage/default/5.sram_ctrl_max_throughput.2794112739
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.1619455617
/workspace/coverage/default/5.sram_ctrl_mem_walk.1111300921
/workspace/coverage/default/5.sram_ctrl_multiple_keys.3199873402
/workspace/coverage/default/5.sram_ctrl_partial_access.312647026
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.666424208
/workspace/coverage/default/5.sram_ctrl_ram_cfg.422430371
/workspace/coverage/default/5.sram_ctrl_regwen.2718476161
/workspace/coverage/default/5.sram_ctrl_smoke.268527830
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.2974352093
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.1876884515
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.1961728026
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.1873411854
/workspace/coverage/default/6.sram_ctrl_alert_test.2533292515
/workspace/coverage/default/6.sram_ctrl_bijection.845075631
/workspace/coverage/default/6.sram_ctrl_executable.786688705
/workspace/coverage/default/6.sram_ctrl_max_throughput.2628324127
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.2341098068
/workspace/coverage/default/6.sram_ctrl_mem_walk.617945254
/workspace/coverage/default/6.sram_ctrl_multiple_keys.3564903229
/workspace/coverage/default/6.sram_ctrl_partial_access.289825977
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.667264996
/workspace/coverage/default/6.sram_ctrl_ram_cfg.1049029085
/workspace/coverage/default/6.sram_ctrl_regwen.361690253
/workspace/coverage/default/6.sram_ctrl_smoke.1319606504
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.1021658953
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.293985442
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.2763906108
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.107983790
/workspace/coverage/default/7.sram_ctrl_alert_test.130967565
/workspace/coverage/default/7.sram_ctrl_bijection.356126619
/workspace/coverage/default/7.sram_ctrl_executable.1255380294
/workspace/coverage/default/7.sram_ctrl_max_throughput.637722214
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.326504344
/workspace/coverage/default/7.sram_ctrl_mem_walk.2929198931
/workspace/coverage/default/7.sram_ctrl_multiple_keys.1830320382
/workspace/coverage/default/7.sram_ctrl_partial_access.846628446
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.4253336084
/workspace/coverage/default/7.sram_ctrl_ram_cfg.3639410523
/workspace/coverage/default/7.sram_ctrl_regwen.541430996
/workspace/coverage/default/7.sram_ctrl_smoke.2302033654
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.794092359
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.3954011560
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.200836116
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.3948475680
/workspace/coverage/default/8.sram_ctrl_alert_test.584988029
/workspace/coverage/default/8.sram_ctrl_bijection.1721802412
/workspace/coverage/default/8.sram_ctrl_executable.2018051106
/workspace/coverage/default/8.sram_ctrl_lc_escalation.2398765856
/workspace/coverage/default/8.sram_ctrl_max_throughput.1731219241
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.2745627705
/workspace/coverage/default/8.sram_ctrl_mem_walk.650307696
/workspace/coverage/default/8.sram_ctrl_multiple_keys.2729890453
/workspace/coverage/default/8.sram_ctrl_partial_access.3199656068
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.2280279979
/workspace/coverage/default/8.sram_ctrl_ram_cfg.3337501864
/workspace/coverage/default/8.sram_ctrl_regwen.246486005
/workspace/coverage/default/8.sram_ctrl_smoke.446653590
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3378544877
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.2288089216
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.1290901941
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.3721805531
/workspace/coverage/default/9.sram_ctrl_alert_test.3660053631
/workspace/coverage/default/9.sram_ctrl_bijection.1639553351
/workspace/coverage/default/9.sram_ctrl_executable.540058604
/workspace/coverage/default/9.sram_ctrl_lc_escalation.4258382516
/workspace/coverage/default/9.sram_ctrl_max_throughput.3608723139
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.2742852309
/workspace/coverage/default/9.sram_ctrl_mem_walk.546717755
/workspace/coverage/default/9.sram_ctrl_multiple_keys.3806894956
/workspace/coverage/default/9.sram_ctrl_partial_access.2802199588
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.3611584689
/workspace/coverage/default/9.sram_ctrl_ram_cfg.3811572250
/workspace/coverage/default/9.sram_ctrl_regwen.3353182291
/workspace/coverage/default/9.sram_ctrl_smoke.256372877
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.1574597954
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.2676136373
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.283253743




Total test records in report: 979
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html

TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/9.sram_ctrl_smoke.256372877 Dec 31 01:04:38 PM PST 23 Dec 31 01:06:55 PM PST 23 900345296 ps
T2 /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.3103577507 Dec 31 01:04:31 PM PST 23 Dec 31 01:09:04 PM PST 23 17387990103 ps
T3 /workspace/coverage/default/46.sram_ctrl_access_during_key_req.1397645439 Dec 31 01:06:17 PM PST 23 Dec 31 01:42:25 PM PST 23 69370794813 ps
T4 /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.1846623128 Dec 31 01:04:48 PM PST 23 Dec 31 01:10:04 PM PST 23 52508073961 ps
T8 /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.200725699 Dec 31 01:05:13 PM PST 23 Dec 31 01:05:57 PM PST 23 1468821606 ps
T9 /workspace/coverage/default/27.sram_ctrl_mem_partial_access.490534951 Dec 31 01:05:29 PM PST 23 Dec 31 01:08:03 PM PST 23 5148158953 ps
T10 /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.961852319 Dec 31 01:04:39 PM PST 23 Dec 31 01:06:08 PM PST 23 2603893852 ps
T11 /workspace/coverage/default/16.sram_ctrl_smoke.2819614201 Dec 31 01:04:44 PM PST 23 Dec 31 01:05:20 PM PST 23 1187472856 ps
T12 /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.2974352093 Dec 31 01:04:06 PM PST 23 Dec 31 01:41:56 PM PST 23 873549738 ps
T13 /workspace/coverage/default/13.sram_ctrl_stress_all.1712591611 Dec 31 01:04:31 PM PST 23 Dec 31 01:34:27 PM PST 23 76368745312 ps
T16 /workspace/coverage/default/18.sram_ctrl_access_during_key_req.277392574 Dec 31 01:04:51 PM PST 23 Dec 31 01:24:54 PM PST 23 6246692451 ps
T14 /workspace/coverage/default/46.sram_ctrl_regwen.3452362217 Dec 31 01:06:48 PM PST 23 Dec 31 01:32:26 PM PST 23 85260009438 ps
T56 /workspace/coverage/default/37.sram_ctrl_max_throughput.2956668169 Dec 31 01:05:49 PM PST 23 Dec 31 01:07:50 PM PST 23 3153789591 ps
T27 /workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.1953665917 Dec 31 01:04:57 PM PST 23 Dec 31 01:51:38 PM PST 23 323218921 ps
T44 /workspace/coverage/default/40.sram_ctrl_executable.2182824219 Dec 31 01:06:27 PM PST 23 Dec 31 01:13:07 PM PST 23 12365353622 ps
T57 /workspace/coverage/default/6.sram_ctrl_regwen.361690253 Dec 31 01:04:02 PM PST 23 Dec 31 01:16:26 PM PST 23 2533868019 ps
T18 /workspace/coverage/default/44.sram_ctrl_alert_test.3914578354 Dec 31 01:06:26 PM PST 23 Dec 31 01:06:29 PM PST 23 59894745 ps
T17 /workspace/coverage/default/10.sram_ctrl_access_during_key_req.763302532 Dec 31 01:04:37 PM PST 23 Dec 31 01:12:32 PM PST 23 14454598767 ps
T131 /workspace/coverage/default/2.sram_ctrl_partial_access.121017432 Dec 31 01:04:27 PM PST 23 Dec 31 01:05:03 PM PST 23 9657529229 ps
T125 /workspace/coverage/default/41.sram_ctrl_executable.735436767 Dec 31 01:06:18 PM PST 23 Dec 31 01:21:42 PM PST 23 18173158468 ps
T132 /workspace/coverage/default/23.sram_ctrl_bijection.2716785070 Dec 31 01:04:56 PM PST 23 Dec 31 01:38:06 PM PST 23 61471059931 ps
T30 /workspace/coverage/default/27.sram_ctrl_ram_cfg.80573566 Dec 31 01:05:03 PM PST 23 Dec 31 01:05:10 PM PST 23 694724399 ps
T133 /workspace/coverage/default/12.sram_ctrl_multiple_keys.2601413027 Dec 31 01:04:25 PM PST 23 Dec 31 01:09:06 PM PST 23 9618445716 ps
T134 /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.923235334 Dec 31 01:05:39 PM PST 23 Dec 31 01:06:16 PM PST 23 727049873 ps
T67 /workspace/coverage/default/41.sram_ctrl_stress_pipeline.3465502229 Dec 31 01:06:02 PM PST 23 Dec 31 01:10:00 PM PST 23 16651741545 ps
T31 /workspace/coverage/default/3.sram_ctrl_ram_cfg.305839289 Dec 31 01:04:09 PM PST 23 Dec 31 01:04:17 PM PST 23 2595512598 ps
T106 /workspace/coverage/default/10.sram_ctrl_stress_pipeline.3487077754 Dec 31 01:04:20 PM PST 23 Dec 31 01:10:45 PM PST 23 5151544765 ps
T15 /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.2280279979 Dec 31 01:04:29 PM PST 23 Dec 31 01:10:50 PM PST 23 33293434089 ps
T135 /workspace/coverage/default/18.sram_ctrl_partial_access.963776621 Dec 31 01:04:42 PM PST 23 Dec 31 01:04:54 PM PST 23 1906048051 ps
T5 /workspace/coverage/default/1.sram_ctrl_lc_escalation.726997098 Dec 31 01:03:49 PM PST 23 Dec 31 01:05:44 PM PST 23 46027309710 ps
T68 /workspace/coverage/default/11.sram_ctrl_mem_partial_access.3878744346 Dec 31 01:04:28 PM PST 23 Dec 31 01:05:47 PM PST 23 4917392113 ps
T129 /workspace/coverage/default/10.sram_ctrl_executable.913063762 Dec 31 01:04:23 PM PST 23 Dec 31 01:22:59 PM PST 23 36834123919 ps
T107 /workspace/coverage/default/42.sram_ctrl_stress_pipeline.717539411 Dec 31 01:06:19 PM PST 23 Dec 31 01:12:18 PM PST 23 5107370057 ps
T69 /workspace/coverage/default/14.sram_ctrl_mem_partial_access.917000498 Dec 31 01:04:21 PM PST 23 Dec 31 01:06:52 PM PST 23 6676189674 ps
T70 /workspace/coverage/default/1.sram_ctrl_multiple_keys.297962178 Dec 31 01:04:00 PM PST 23 Dec 31 01:16:53 PM PST 23 68907432336 ps
T28 /workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.1290980409 Dec 31 01:05:44 PM PST 23 Dec 31 02:10:50 PM PST 23 2510791201 ps
T108 /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.83011887 Dec 31 01:06:20 PM PST 23 Dec 31 01:13:27 PM PST 23 6753227000 ps
T123 /workspace/coverage/default/5.sram_ctrl_regwen.2718476161 Dec 31 01:04:35 PM PST 23 Dec 31 01:11:50 PM PST 23 7880025183 ps
T136 /workspace/coverage/default/29.sram_ctrl_partial_access.3925323501 Dec 31 01:05:31 PM PST 23 Dec 31 01:05:56 PM PST 23 2999539550 ps
T19 /workspace/coverage/default/34.sram_ctrl_alert_test.1216387038 Dec 31 01:05:31 PM PST 23 Dec 31 01:05:33 PM PST 23 30160005 ps
T137 /workspace/coverage/default/25.sram_ctrl_mem_walk.2802835109 Dec 31 01:05:06 PM PST 23 Dec 31 01:09:10 PM PST 23 3943690547 ps
T138 /workspace/coverage/default/39.sram_ctrl_bijection.2401116505 Dec 31 01:05:42 PM PST 23 Dec 31 01:35:05 PM PST 23 163081670373 ps
T139 /workspace/coverage/default/8.sram_ctrl_max_throughput.1731219241 Dec 31 01:04:20 PM PST 23 Dec 31 01:07:15 PM PST 23 3160679100 ps
T140 /workspace/coverage/default/25.sram_ctrl_multiple_keys.297726748 Dec 31 01:05:06 PM PST 23 Dec 31 01:22:12 PM PST 23 14748482439 ps
T29 /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2526140797 Dec 31 12:52:09 PM PST 23 Dec 31 12:54:10 PM PST 23 14429775143 ps
T60 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.369348657 Dec 31 12:51:50 PM PST 23 Dec 31 12:52:00 PM PST 23 14998779 ps
T48 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.883674441 Dec 31 12:52:01 PM PST 23 Dec 31 12:52:13 PM PST 23 460476715 ps
T49 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1606678196 Dec 31 12:52:10 PM PST 23 Dec 31 12:52:28 PM PST 23 108663902 ps
T45 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1313361670 Dec 31 12:52:04 PM PST 23 Dec 31 12:52:13 PM PST 23 227312157 ps
T102 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3104123573 Dec 31 12:52:05 PM PST 23 Dec 31 12:52:14 PM PST 23 42171355 ps
T61 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1191887976 Dec 31 12:51:43 PM PST 23 Dec 31 12:51:57 PM PST 23 45679174 ps
T50 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.417531667 Dec 31 12:52:09 PM PST 23 Dec 31 12:52:29 PM PST 23 346952513 ps
T62 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2817362173 Dec 31 12:52:06 PM PST 23 Dec 31 12:52:18 PM PST 23 24736350 ps
T51 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.4023954558 Dec 31 12:51:54 PM PST 23 Dec 31 12:52:08 PM PST 23 1376053787 ps
T52 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.334170472 Dec 31 12:51:53 PM PST 23 Dec 31 12:52:04 PM PST 23 23871253 ps
T103 /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.548458902 Dec 31 12:52:05 PM PST 23 Dec 31 12:52:15 PM PST 23 58343727 ps
T53 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2106938536 Dec 31 12:52:02 PM PST 23 Dec 31 12:52:14 PM PST 23 1781544594 ps
T54 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1863960663 Dec 31 12:52:09 PM PST 23 Dec 31 12:52:25 PM PST 23 28196335 ps
T104 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3278071552 Dec 31 12:51:55 PM PST 23 Dec 31 12:52:04 PM PST 23 38597430 ps
T63 /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2708757564 Dec 31 12:52:02 PM PST 23 Dec 31 12:56:35 PM PST 23 20835238362 ps
T55 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3663825124 Dec 31 12:51:45 PM PST 23 Dec 31 12:52:00 PM PST 23 134236783 ps
T112 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2144364934 Dec 31 12:52:01 PM PST 23 Dec 31 12:52:10 PM PST 23 15671520 ps
T105 /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2252462819 Dec 31 12:51:52 PM PST 23 Dec 31 12:52:00 PM PST 23 127670483 ps
T64 /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.650313587 Dec 31 12:52:10 PM PST 23 Dec 31 12:53:17 PM PST 23 3733377770 ps
T46 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3150731427 Dec 31 12:52:00 PM PST 23 Dec 31 12:52:10 PM PST 23 358755407 ps
T65 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1917881828 Dec 31 12:52:07 PM PST 23 Dec 31 12:52:32 PM PST 23 342529052 ps
T66 /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2515756037 Dec 31 12:51:39 PM PST 23 Dec 31 12:53:06 PM PST 23 40956117585 ps
T47 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.203724813 Dec 31 12:51:56 PM PST 23 Dec 31 12:52:05 PM PST 23 198599042 ps
T75 /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1366349417 Dec 31 12:52:09 PM PST 23 Dec 31 12:52:24 PM PST 23 72043501 ps
T91 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.68208195 Dec 31 12:52:11 PM PST 23 Dec 31 12:52:27 PM PST 23 329149558 ps
T98 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2686221198 Dec 31 12:52:06 PM PST 23 Dec 31 12:52:24 PM PST 23 137341362 ps
T99 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3793138324 Dec 31 12:52:02 PM PST 23 Dec 31 12:52:12 PM PST 23 96966678 ps
T141 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3936326067 Dec 31 12:51:56 PM PST 23 Dec 31 12:52:10 PM PST 23 773074078 ps
T71 /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2384997939 Dec 31 12:52:08 PM PST 23 Dec 31 12:52:23 PM PST 23 36682281 ps
T113 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2208318364 Dec 31 12:52:06 PM PST 23 Dec 31 12:52:18 PM PST 23 15967458 ps
T142 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3747711637 Dec 31 12:51:49 PM PST 23 Dec 31 12:51:59 PM PST 23 25490331 ps
T143 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.345507399 Dec 31 12:51:46 PM PST 23 Dec 31 12:51:58 PM PST 23 215272842 ps
T144 /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3549482257 Dec 31 12:52:00 PM PST 23 Dec 31 12:52:08 PM PST 23 33191401 ps
T72 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2804568572 Dec 31 12:52:00 PM PST 23 Dec 31 12:52:08 PM PST 23 40170545 ps
T114 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1051879356 Dec 31 12:52:14 PM PST 23 Dec 31 12:52:30 PM PST 23 368851057 ps
T73 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3521076961 Dec 31 12:52:07 PM PST 23 Dec 31 12:52:21 PM PST 23 156225060 ps
T86 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1176572390 Dec 31 12:51:52 PM PST 23 Dec 31 12:52:02 PM PST 23 639714493 ps
T87 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3458593857 Dec 31 12:52:07 PM PST 23 Dec 31 12:52:20 PM PST 23 10839411 ps
T88 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3780801539 Dec 31 12:52:04 PM PST 23 Dec 31 12:52:13 PM PST 23 38372511 ps
T89 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2628379608 Dec 31 12:51:53 PM PST 23 Dec 31 12:52:02 PM PST 23 76554274 ps
T74 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2184622625 Dec 31 12:52:01 PM PST 23 Dec 31 12:52:10 PM PST 23 38180953 ps
T94 /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1414395303 Dec 31 12:52:14 PM PST 23 Dec 31 12:52:29 PM PST 23 31244517 ps
T58 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1882639375 Dec 31 12:52:06 PM PST 23 Dec 31 12:52:19 PM PST 23 50313376 ps
T95 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1903005138 Dec 31 12:52:05 PM PST 23 Dec 31 12:52:16 PM PST 23 37856683 ps
T59 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2457688486 Dec 31 12:51:36 PM PST 23 Dec 31 12:51:51 PM PST 23 476355793 ps
T96 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2100117365 Dec 31 12:51:48 PM PST 23 Dec 31 12:51:59 PM PST 23 70435643 ps
T76 /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1388691893 Dec 31 12:52:05 PM PST 23 Dec 31 12:54:35 PM PST 23 7530350344 ps
T145 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2595059776 Dec 31 12:52:01 PM PST 23 Dec 31 12:52:21 PM PST 23 2000820140 ps
T146 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3918557886 Dec 31 12:52:05 PM PST 23 Dec 31 12:52:20 PM PST 23 520865312 ps
T118 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3884618198 Dec 31 12:51:58 PM PST 23 Dec 31 12:52:07 PM PST 23 175187442 ps
T147 /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1860918661 Dec 31 12:51:59 PM PST 23 Dec 31 12:52:07 PM PST 23 22086100 ps
T148 /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3440197052 Dec 31 12:52:02 PM PST 23 Dec 31 12:52:10 PM PST 23 25181401 ps
T77 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1508829913 Dec 31 12:52:00 PM PST 23 Dec 31 12:52:08 PM PST 23 13119991 ps
T149 /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1970613563 Dec 31 12:51:53 PM PST 23 Dec 31 12:52:03 PM PST 23 15754294 ps
T150 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.34552757 Dec 31 12:52:02 PM PST 23 Dec 31 12:52:14 PM PST 23 339097699 ps
T151 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3138520522 Dec 31 12:51:58 PM PST 23 Dec 31 12:52:07 PM PST 23 21927382 ps
T78 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2484408166 Dec 31 12:52:05 PM PST 23 Dec 31 12:52:14 PM PST 23 37706831 ps
T152 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2149219141 Dec 31 12:52:05 PM PST 23 Dec 31 12:52:15 PM PST 23 34551098 ps
T153 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1547780631 Dec 31 12:51:59 PM PST 23 Dec 31 12:52:07 PM PST 23 12072445 ps
T122 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3568051916 Dec 31 12:52:05 PM PST 23 Dec 31 12:52:17 PM PST 23 287023758 ps
T154 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1507212416 Dec 31 12:52:10 PM PST 23 Dec 31 12:52:26 PM PST 23 91569127 ps
T116 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3864616443 Dec 31 12:52:08 PM PST 23 Dec 31 12:52:23 PM PST 23 381021771 ps
T155 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.4141812016 Dec 31 12:52:08 PM PST 23 Dec 31 12:52:24 PM PST 23 221680549 ps
T120 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1218936307 Dec 31 12:52:00 PM PST 23 Dec 31 12:52:10 PM PST 23 194193033 ps
T156 /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.348113442 Dec 31 12:51:54 PM PST 23 Dec 31 12:52:04 PM PST 23 20091537 ps
T157 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.138865500 Dec 31 12:52:07 PM PST 23 Dec 31 12:52:27 PM PST 23 1909106080 ps
T79 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1094881599 Dec 31 12:51:34 PM PST 23 Dec 31 12:51:43 PM PST 23 30654145 ps
T158 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3381838094 Dec 31 12:51:53 PM PST 23 Dec 31 12:52:13 PM PST 23 1390325780 ps
T159 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1304139466 Dec 31 12:52:15 PM PST 23 Dec 31 12:52:34 PM PST 23 1042174628 ps
T160 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3759728402 Dec 31 12:52:03 PM PST 23 Dec 31 12:52:15 PM PST 23 160397644 ps
T161 /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3807313016 Dec 31 12:52:06 PM PST 23 Dec 31 12:52:20 PM PST 23 57358123 ps
T162 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.167100802 Dec 31 12:51:59 PM PST 23 Dec 31 12:52:12 PM PST 23 703723240 ps
T163 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3317898508 Dec 31 12:52:09 PM PST 23 Dec 31 12:52:27 PM PST 23 82791191 ps
T164 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3923463508 Dec 31 12:51:53 PM PST 23 Dec 31 12:52:02 PM PST 23 30659461 ps
T119 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2387881859 Dec 31 12:52:10 PM PST 23 Dec 31 12:52:28 PM PST 23 242559192 ps
T165 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3306312811 Dec 31 12:51:40 PM PST 23 Dec 31 12:51:57 PM PST 23 122060061 ps
T90 /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.4163821741 Dec 31 12:51:57 PM PST 23 Dec 31 12:54:03 PM PST 23 7193391274 ps
T166 /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.552072265 Dec 31 12:51:53 PM PST 23 Dec 31 12:52:02 PM PST 23 22546879 ps
T92 /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3356776197 Dec 31 12:51:51 PM PST 23 Dec 31 12:54:31 PM PST 23 3987002794 ps
T167 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1863137286 Dec 31 12:52:06 PM PST 23 Dec 31 12:52:19 PM PST 23 13315751 ps
T168 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3706176020 Dec 31 12:51:59 PM PST 23 Dec 31 12:52:12 PM PST 23 368342767 ps
T117 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2979201137 Dec 31 12:52:05 PM PST 23 Dec 31 12:52:21 PM PST 23 196774055 ps
T169 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.488267104 Dec 31 12:52:05 PM PST 23 Dec 31 12:52:22 PM PST 23 1357269803 ps
T170 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2719125820 Dec 31 12:51:52 PM PST 23 Dec 31 12:52:02 PM PST 23 146783627 ps
T171 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.604444829 Dec 31 12:52:00 PM PST 23 Dec 31 12:52:12 PM PST 23 45240278 ps
T172 /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3149949480 Dec 31 12:51:59 PM PST 23 Dec 31 12:52:08 PM PST 23 96146501 ps
T173 /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.800355773 Dec 31 12:51:49 PM PST 23 Dec 31 12:51:59 PM PST 23 64527299 ps
T121 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2438514903 Dec 31 12:52:02 PM PST 23 Dec 31 12:52:11 PM PST 23 115943869 ps
T97 /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1719834383 Dec 31 12:52:06 PM PST 23 Dec 31 12:53:14 PM PST 23 13692576001 ps
T174 /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3408603734 Dec 31 12:51:53 PM PST 23 Dec 31 12:53:59 PM PST 23 28220562757 ps
T175 /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.44360554 Dec 31 12:52:04 PM PST 23 Dec 31 12:52:13 PM PST 23 23037248 ps
T176 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1248865341 Dec 31 12:52:06 PM PST 23 Dec 31 12:52:19 PM PST 23 31367655 ps
T177 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2425179912 Dec 31 12:51:58 PM PST 23 Dec 31 12:52:07 PM PST 23 38810892 ps
T178 /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3350284351 Dec 31 12:51:51 PM PST 23 Dec 31 12:52:54 PM PST 23 15438337346 ps
T179 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2095161001 Dec 31 12:52:03 PM PST 23 Dec 31 12:52:13 PM PST 23 57042916 ps
T180 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3906145155 Dec 31 12:51:59 PM PST 23 Dec 31 12:52:19 PM PST 23 536988718 ps
T181 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1019666657 Dec 31 12:51:58 PM PST 23 Dec 31 12:52:08 PM PST 23 125958043 ps
T182 /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3019660177 Dec 31 12:52:03 PM PST 23 Dec 31 12:54:15 PM PST 23 14378227194 ps
T183 /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2476570408 Dec 31 12:51:53 PM PST 23 Dec 31 12:52:02 PM PST 23 39330939 ps
T93 /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3176287454 Dec 31 12:52:13 PM PST 23 Dec 31 12:53:24 PM PST 23 15386660775 ps
T184 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2577587783 Dec 31 12:51:59 PM PST 23 Dec 31 12:52:13 PM PST 23 349857779 ps
T185 /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1749818249 Dec 31 12:52:03 PM PST 23 Dec 31 12:52:11 PM PST 23 40749630 ps
T186 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1719286949 Dec 31 12:51:53 PM PST 23 Dec 31 12:52:03 PM PST 23 42030252 ps
T187 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1494368745 Dec 31 12:52:04 PM PST 23 Dec 31 12:52:12 PM PST 23 20924250 ps
T84 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3006319626 Dec 31 12:51:59 PM PST 23 Dec 31 12:52:08 PM PST 23 27632028 ps
T188 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.249343325 Dec 31 12:52:00 PM PST 23 Dec 31 12:52:14 PM PST 23 719870266 ps
T100 /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2205501977 Dec 31 12:52:03 PM PST 23 Dec 31 12:56:46 PM PST 23 50397395031 ps
T189 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.427693786 Dec 31 12:52:06 PM PST 23 Dec 31 12:52:30 PM PST 23 696110622 ps
T190 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2131404969 Dec 31 12:52:08 PM PST 23 Dec 31 12:52:28 PM PST 23 413484357 ps
T191 /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.839703274 Dec 31 12:52:06 PM PST 23 Dec 31 12:52:19 PM PST 23 22987187 ps
T192 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1579448823 Dec 31 12:52:05 PM PST 23 Dec 31 12:52:14 PM PST 23 23432699 ps
T193 /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1522865303 Dec 31 12:52:08 PM PST 23 Dec 31 12:52:23 PM PST 23 17125786 ps
T194 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.806565908 Dec 31 12:52:05 PM PST 23 Dec 31 12:52:16 PM PST 23 285607994 ps
T195 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3771237397 Dec 31 12:52:10 PM PST 23 Dec 31 12:52:29 PM PST 23 152047451 ps
T196 /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.616611582 Dec 31 12:51:53 PM PST 23 Dec 31 12:56:14 PM PST 23 7148341017 ps
T197 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.994045914 Dec 31 12:52:06 PM PST 23 Dec 31 12:52:23 PM PST 23 34562116 ps
T198 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.579294162 Dec 31 12:52:05 PM PST 23 Dec 31 12:52:15 PM PST 23 15375671 ps
T199 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2091990901 Dec 31 12:51:52 PM PST 23 Dec 31 12:52:01 PM PST 23 36941312 ps
T101 /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1785980893 Dec 31 12:52:09 PM PST 23 Dec 31 12:56:53 PM PST 23 15923731452 ps
T200 /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1023795980 Dec 31 12:52:02 PM PST 23 Dec 31 12:52:59 PM PST 23 3819970469 ps
T201 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3690977086 Dec 31 12:52:06 PM PST 23 Dec 31 12:52:20 PM PST 23 27464589 ps
T202 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3149450531 Dec 31 12:51:56 PM PST 23 Dec 31 12:52:05 PM PST 23 664096959 ps
T203 /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3620127277 Dec 31 12:51:51 PM PST 23 Dec 31 12:54:15 PM PST 23 10835104679 ps
T204 /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.4078080866 Dec 31 12:52:07 PM PST 23 Dec 31 12:53:10 PM PST 23 8039107792 ps
T205 /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1540561112 Dec 31 12:52:07 PM PST 23 Dec 31 12:52:21 PM PST 23 19130704 ps
T206 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1242735917 Dec 31 12:51:36 PM PST 23 Dec 31 12:52:02 PM PST 23 378134794 ps
T207 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1535258184 Dec 31 12:52:04 PM PST 23 Dec 31 12:52:18 PM PST 23 893992857 ps
T208 /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2373694817 Dec 31 12:52:05 PM PST 23 Dec 31 12:54:48 PM PST 23 8596877009 ps
T209 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1133381848 Dec 31 12:52:01 PM PST 23 Dec 31 12:52:11 PM PST 23 213937165 ps
T210 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2349488447 Dec 31 12:52:12 PM PST 23 Dec 31 12:52:40 PM PST 23 1443775971 ps
T211 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2336147618 Dec 31 12:51:56 PM PST 23 Dec 31 12:52:09 PM PST 23 715757288 ps
T212 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1088790453 Dec 31 12:51:39 PM PST 23 Dec 31 12:51:53 PM PST 23 1057744859 ps
T213 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2826650064 Dec 31 12:52:09 PM PST 23 Dec 31 12:52:24 PM PST 23 15339639 ps
T214 /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1739964545 Dec 31 12:51:43 PM PST 23 Dec 31 12:53:31 PM PST 23 16462204698 ps
T80 /workspace/coverage/default/22.sram_ctrl_access_during_key_req.1109512429 Dec 31 01:04:45 PM PST 23 Dec 31 01:14:40 PM PST 23 6715250110 ps
T6 /workspace/coverage/default/27.sram_ctrl_lc_escalation.3359198427 Dec 31 01:05:32 PM PST 23 Dec 31 01:10:05 PM PST 23 44775805282 ps
T24 /workspace/coverage/default/0.sram_ctrl_regwen.2928452543 Dec 31 01:04:02 PM PST 23 Dec 31 01:17:05 PM PST 23 15575965635 ps
T81 /workspace/coverage/default/49.sram_ctrl_access_during_key_req.1376858347 Dec 31 01:06:42 PM PST 23 Dec 31 01:19:05 PM PST 23 8143128339 ps
T109 /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.2426272260 Dec 31 01:05:31 PM PST 23 Dec 31 01:10:03 PM PST 23 39569793156 ps
T215 /workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.2051202305 Dec 31 01:04:50 PM PST 23 Dec 31 02:17:41 PM PST 23 1801362191 ps
T216 /workspace/coverage/default/0.sram_ctrl_bijection.872720544 Dec 31 01:04:16 PM PST 23 Dec 31 01:38:15 PM PST 23 124181218429 ps
T217 /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.1029167873 Dec 31 01:06:18 PM PST 23 Dec 31 01:07:35 PM PST 23 2970117268 ps
T218 /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.283253743 Dec 31 01:04:21 PM PST 23 Dec 31 01:07:14 PM PST 23 817918710 ps
T20 /workspace/coverage/default/36.sram_ctrl_alert_test.337780505 Dec 31 01:05:42 PM PST 23 Dec 31 01:05:45 PM PST 23 35887996 ps
T110 /workspace/coverage/default/28.sram_ctrl_stress_pipeline.3093714297 Dec 31 01:05:03 PM PST 23 Dec 31 01:09:03 PM PST 23 3108002682 ps
T82 /workspace/coverage/default/3.sram_ctrl_mem_partial_access.197826165 Dec 31 01:03:55 PM PST 23 Dec 31 01:05:10 PM PST 23 2584997159 ps
T219 /workspace/coverage/default/32.sram_ctrl_partial_access.2656149272 Dec 31 01:05:33 PM PST 23 Dec 31 01:06:01 PM PST 23 1605869809 ps
T220 /workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.3006103750 Dec 31 01:04:59 PM PST 23 Dec 31 01:07:20 PM PST 23 783270043 ps
T7 /workspace/coverage/default/24.sram_ctrl_stress_all.3350964859 Dec 31 01:04:47 PM PST 23 Dec 31 02:29:29 PM PST 23 1179091278734 ps
T83 /workspace/coverage/default/0.sram_ctrl_access_during_key_req.1274620772 Dec 31 01:04:05 PM PST 23 Dec 31 01:16:47 PM PST 23 5154139905 ps
T221 /workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.1137780619 Dec 31 01:06:15 PM PST 23 Dec 31 02:03:33 PM PST 23 16705011195 ps
T222 /workspace/coverage/default/18.sram_ctrl_smoke.634781574 Dec 31 01:04:42 PM PST 23 Dec 31 01:04:54 PM PST 23 893950092 ps
T223 /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3988417956 Dec 31 01:06:25 PM PST 23 Dec 31 02:00:23 PM PST 23 1127975053 ps
T111 /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.1647941095 Dec 31 01:04:37 PM PST 23 Dec 31 01:13:08 PM PST 23 127886800411 ps
T25 /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.1021658953 Dec 31 01:04:21 PM PST 23 Dec 31 02:34:37 PM PST 23 11528367592 ps
T224 /workspace/coverage/default/33.sram_ctrl_bijection.3227649222 Dec 31 01:05:32 PM PST 23 Dec 31 01:23:24 PM PST 23 96294046227 ps
T225 /workspace/coverage/default/5.sram_ctrl_access_during_key_req.1393362631 Dec 31 01:03:54 PM PST 23 Dec 31 01:20:12 PM PST 23 73248839113 ps
T226 /workspace/coverage/default/33.sram_ctrl_multiple_keys.1752820122 Dec 31 01:05:40 PM PST 23 Dec 31 01:20:03 PM PST 23 59280345750 ps
T227 /workspace/coverage/default/14.sram_ctrl_partial_access.2265934626 Dec 31 01:04:33 PM PST 23 Dec 31 01:05:01 PM PST 23 2796022192 ps
T228 /workspace/coverage/default/37.sram_ctrl_bijection.3570397998 Dec 31 01:05:42 PM PST 23 Dec 31 01:18:31 PM PST 23 43290159984 ps
T128 /workspace/coverage/default/49.sram_ctrl_regwen.3618026463 Dec 31 01:06:45 PM PST 23 Dec 31 01:23:13 PM PST 23 8641795940 ps
T32 /workspace/coverage/default/47.sram_ctrl_ram_cfg.1168228752 Dec 31 01:06:44 PM PST 23 Dec 31 01:06:56 PM PST 23 345742108 ps
T229 /workspace/coverage/default/29.sram_ctrl_smoke.3193496181 Dec 31 01:05:06 PM PST 23 Dec 31 01:06:59 PM PST 23 8516554535 ps
T230 /workspace/coverage/default/15.sram_ctrl_max_throughput.1000318559 Dec 31 01:04:43 PM PST 23 Dec 31 01:05:29 PM PST 23 1471135532 ps
T231 /workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.4177224918 Dec 31 01:05:31 PM PST 23 Dec 31 02:12:21 PM PST 23 1388225501 ps
T232 /workspace/coverage/default/23.sram_ctrl_alert_test.3560949821 Dec 31 01:04:57 PM PST 23 Dec 31 01:04:59 PM PST 23 43137157 ps
T233 /workspace/coverage/default/15.sram_ctrl_bijection.3579014040 Dec 31 01:04:42 PM PST 23 Dec 31 01:47:34 PM PST 23 112712670962 ps
T234 /workspace/coverage/default/37.sram_ctrl_access_during_key_req.1548416802 Dec 31 01:05:44 PM PST 23 Dec 31 01:34:51 PM PST 23 11177889579 ps
T235 /workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.3910540943 Dec 31 01:05:05 PM PST 23 Dec 31 02:12:41 PM PST 23 2645473590 ps
T236 /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.667264996 Dec 31 01:04:18 PM PST 23 Dec 31 01:12:33 PM PST 23 31052727697 ps
T237 /workspace/coverage/default/18.sram_ctrl_multiple_keys.236369110 Dec 31 01:04:59 PM PST 23 Dec 31 01:22:03 PM PST 23 110297988556 ps
T238 /workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.2954702336 Dec 31 01:06:03 PM PST 23 Dec 31 01:29:52 PM PST 23 17569831375 ps
T239 /workspace/coverage/default/36.sram_ctrl_smoke.656948911 Dec 31 01:05:41 PM PST 23 Dec 31 01:07:29 PM PST 23 899626081 ps
T240 /workspace/coverage/default/28.sram_ctrl_access_during_key_req.1713657898 Dec 31 01:05:05 PM PST 23 Dec 31 01:17:50 PM PST 23 22334485384 ps
T241 /workspace/coverage/default/35.sram_ctrl_mem_walk.879791104 Dec 31 01:05:42 PM PST 23 Dec 31 01:10:28 PM PST 23 28111170666 ps
T242 /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.806011229 Dec 31 01:05:42 PM PST 23 Dec 31 01:10:54 PM PST 23 14388477391 ps
T243 /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.3607022907 Dec 31 01:06:45 PM PST 23 Dec 31 01:08:36 PM PST 23 3556024023 ps
T244 /workspace/coverage/default/1.sram_ctrl_alert_test.2235691826 Dec 31 01:04:27 PM PST 23 Dec 31 01:04:30 PM PST 23 12526338 ps
T245 /workspace/coverage/default/6.sram_ctrl_alert_test.2533292515 Dec 31 01:04:08 PM PST 23 Dec 31 01:04:10 PM PST 23 27351963 ps
T246 /workspace/coverage/default/6.sram_ctrl_ram_cfg.1049029085 Dec 31 01:04:22 PM PST 23 Dec 31 01:04:31 PM PST 23 2412016930 ps
T130 /workspace/coverage/default/47.sram_ctrl_executable.4006833649 Dec 31 01:06:43 PM PST 23 Dec 31 01:34:48 PM PST 23 116466407851 ps
T247 /workspace/coverage/default/25.sram_ctrl_bijection.1630761648 Dec 31 01:05:04 PM PST 23 Dec 31 01:17:29 PM PST 23 47077973094 ps
T248 /workspace/coverage/default/8.sram_ctrl_bijection.1721802412 Dec 31 01:04:46 PM PST 23 Dec 31 01:24:01 PM PST 23 72108287083 ps
T249 /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.666424208 Dec 31 01:04:10 PM PST 23 Dec 31 01:09:54 PM PST 23 5665135432 ps
T21 /workspace/coverage/default/0.sram_ctrl_sec_cm.3364453552 Dec 31 01:04:03 PM PST 23 Dec 31 01:04:05 PM PST 23 88040104 ps
T35 /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.3570082278 Dec 31 01:04:43 PM PST 23 Dec 31 01:57:00 PM PST 23 5544634786 ps
T36 /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.3092248122 Dec 31 01:06:24 PM PST 23 Dec 31 01:07:00 PM PST 23 2785262346 ps
T37 /workspace/coverage/default/43.sram_ctrl_alert_test.3609863076 Dec 31 01:06:17 PM PST 23 Dec 31 01:06:21 PM PST 23 12237216 ps
T38 /workspace/coverage/default/19.sram_ctrl_mem_partial_access.2262636952 Dec 31 01:04:54 PM PST 23 Dec 31 01:06:15 PM PST 23 2801130790 ps
T39 /workspace/coverage/default/32.sram_ctrl_alert_test.285217299 Dec 31 01:05:40 PM PST 23 Dec 31 01:05:43 PM PST 23 100363106 ps
T40 /workspace/coverage/default/34.sram_ctrl_bijection.3558505692 Dec 31 01:05:43 PM PST 23 Dec 31 01:32:06 PM PST 23 46171862275 ps
T41 /workspace/coverage/default/38.sram_ctrl_regwen.1912181753 Dec 31 01:05:43 PM PST 23 Dec 31 01:24:05 PM PST 23 3467365988 ps
T42 /workspace/coverage/default/30.sram_ctrl_stress_pipeline.2074512022 Dec 31 01:05:09 PM PST 23 Dec 31 01:12:56 PM PST 23 22317301305 ps
T43 /workspace/coverage/default/22.sram_ctrl_alert_test.215790581 Dec 31 01:04:52 PM PST 23 Dec 31 01:04:54 PM PST 23 24347747 ps
T124 /workspace/coverage/default/45.sram_ctrl_lc_escalation.332945281 Dec 31 01:06:25 PM PST 23 Dec 31 01:08:14 PM PST 23 9129971426 ps
T250 /workspace/coverage/default/19.sram_ctrl_mem_walk.2702957749 Dec 31 01:04:46 PM PST 23 Dec 31 01:09:55 PM PST 23 20675948120 ps
T251 /workspace/coverage/default/10.sram_ctrl_regwen.2437692711 Dec 31 01:04:30 PM PST 23 Dec 31 01:26:34 PM PST 23 9434844244 ps
T252 /workspace/coverage/default/39.sram_ctrl_max_throughput.907433490 Dec 31 01:05:44 PM PST 23 Dec 31 01:08:30 PM PST 23 770317766 ps
T253 /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.2924116031 Dec 31 01:05:31 PM PST 23 Dec 31 01:12:18 PM PST 23 19094222738 ps
T254 /workspace/coverage/default/6.sram_ctrl_mem_partial_access.2341098068 Dec 31 01:04:03 PM PST 23 Dec 31 01:06:23 PM PST 23 1553317229 ps
T255 /workspace/coverage/default/35.sram_ctrl_executable.4204581356 Dec 31 01:05:39 PM PST 23 Dec 31 01:36:43 PM PST 23 33671898373 ps
T256 /workspace/coverage/default/31.sram_ctrl_regwen.1808739714 Dec 31 01:05:08 PM PST 23 Dec 31 01:14:16 PM PST 23 17784951368 ps
T257 /workspace/coverage/default/12.sram_ctrl_stress_pipeline.1474515780 Dec 31 01:04:26 PM PST 23 Dec 31 01:08:33 PM PST 23 3410934698 ps
T258 /workspace/coverage/default/2.sram_ctrl_bijection.1420765910 Dec 31 01:04:33 PM PST 23 Dec 31 01:18:18 PM PST 23 12387508886 ps
T259 /workspace/coverage/default/47.sram_ctrl_stress_pipeline.1374779581 Dec 31 01:06:44 PM PST 23 Dec 31 01:12:03 PM PST 23 4339058705 ps
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