Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	115459469	1			T1	8048		T2	24370		T3	185823
triple_byte_access	2722742	1			T1	143		T2	21764		T3	3817
halfword_access	4185474	1			T1	264		T2	32657		T3	5453
byte_access	5883564	1			T1	331		T2	44068		T3	7438
zero_access	1814963	1			T1	81		T2	10985		T3	1870

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

64406310

1

T1

4424

T2

66560

T3

101973

auto[1]

65659902

1

T1

4443

T2

67284

T3

102428

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	56989654	1			T1	4020		T2	12039		T3	92687
auto[0]	triple_byte_access	1283539	1			T1	74		T2	10781		T3	1908
auto[0]	halfword_access	2028223	1			T1	141		T2	16271		T3	2742
auto[0]	byte_access	3008483	1			T1	153		T2	21989		T3	3709
auto[0]	zero_access	1096411	1			T1	36		T2	5480		T3	927
auto[1]	word_access	58469815	1			T1	4028		T2	12331		T3	93136
auto[1]	triple_byte_access	1439203	1			T1	69		T2	10983		T3	1909
auto[1]	halfword_access	2157251	1			T1	123		T2	16386		T3	2711
auto[1]	byte_access	2875081	1			T1	178		T2	22079		T3	3729
auto[1]	zero_access	718552	1			T1	45		T2	5505		T3	943