Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	15726779	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

139042354

1

T1

1994

T2

3121

T3

146318

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	76084637	1			T1	1102		T2	30922		T3	80225
values[0x0]	37783280	1			T1	528		T2	9984		T3	38865
values[0x1]	40901216	1			T1	544		T2	21409		T3	41970

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8012784	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

146756349

1

T1

2077

T2

28027

T3

153689

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	509318	1			T1	6		T2	220		T3	620
valid_sources[0x01]	540171	1			T1	10		T2	272		T3	603
valid_sources[0x02]	532554	1			T1	11		T2	239		T3	684
valid_sources[0x03]	504875	1			T1	7		T2	231		T3	615
valid_sources[0x04]	533963	1			T1	9		T2	239		T3	590
valid_sources[0x05]	498625	1			T1	12		T2	226		T3	637
valid_sources[0x06]	531809	1			T1	11		T2	233		T3	597
valid_sources[0x07]	2101431	1			T1	6		T2	267		T3	641
valid_sources[0x08]	502179	1			T1	12		T2	252		T3	663
valid_sources[0x09]	713733	1			T1	8		T2	259		T3	581
valid_sources[0x0a]	504783	1			T1	9		T2	243		T3	596
valid_sources[0x0b]	498948	1			T1	5		T2	264		T3	640
valid_sources[0x0c]	551139	1			T1	2		T2	216		T3	674
valid_sources[0x0d]	540213	1			T1	13		T2	245		T3	615
valid_sources[0x0e]	700774	1			T1	5		T2	255		T3	704
valid_sources[0x0f]	497291	1			T1	13		T2	225		T3	636
valid_sources[0x10]	713401	1			T1	9		T2	269		T3	687
valid_sources[0x11]	493405	1			T1	7		T2	246		T3	690
valid_sources[0x12]	506053	1			T1	9		T2	237		T3	634
valid_sources[0x13]	516191	1			T1	8		T2	276		T3	641
valid_sources[0x14]	488317	1			T1	17		T2	253		T3	625
valid_sources[0x15]	541953	1			T1	5		T2	215		T3	642
valid_sources[0x16]	526195	1			T1	10		T2	234		T3	616
valid_sources[0x17]	506115	1			T1	5		T2	256		T3	614
valid_sources[0x18]	516438	1			T1	7		T2	263		T3	633
valid_sources[0x19]	610409	1			T1	7		T2	259		T3	613
valid_sources[0x1a]	488726	1			T1	9		T2	286		T3	680
valid_sources[0x1b]	507650	1			T1	8		T2	193		T3	615
valid_sources[0x1c]	502095	1			T1	12		T2	244		T3	673
valid_sources[0x1d]	537616	1			T1	8		T2	244		T3	620
valid_sources[0x1e]	515332	1			T1	9		T2	230		T3	654
valid_sources[0x1f]	545314	1			T1	7		T2	227		T3	581
valid_sources[0x20]	496451	1			T1	9		T2	238		T3	603
valid_sources[0x21]	544390	1			T1	9		T2	226		T3	574
valid_sources[0x22]	1366728	1			T1	15		T2	249		T3	682
valid_sources[0x23]	512736	1			T1	7		T2	224		T3	651
valid_sources[0x24]	532913	1			T1	11		T2	252		T3	690
valid_sources[0x25]	536942	1			T1	5		T2	238		T3	657
valid_sources[0x26]	507803	1			T1	4		T2	235		T3	585
valid_sources[0x27]	1790328	1			T1	11		T2	238		T3	618
valid_sources[0x28]	502204	1			T1	7		T2	229		T3	612
valid_sources[0x29]	539539	1			T1	10		T2	234		T3	693
valid_sources[0x2a]	530188	1			T1	6		T2	229		T3	637
valid_sources[0x2b]	501996	1			T1	10		T2	264		T3	619
valid_sources[0x2c]	524474	1			T1	10		T2	237		T3	667
valid_sources[0x2d]	1534002	1			T1	7		T2	268		T3	624
valid_sources[0x2e]	537496	1			T1	8		T2	275		T3	612
valid_sources[0x2f]	506361	1			T1	14		T2	277		T3	626
valid_sources[0x30]	542696	1			T1	12		T2	256		T3	599
valid_sources[0x31]	506411	1			T1	8		T2	277		T3	693
valid_sources[0x32]	493743	1			T1	5		T2	240		T3	639
valid_sources[0x33]	541184	1			T1	8		T2	250		T3	648
valid_sources[0x34]	513465	1			T1	6		T2	252		T3	644
valid_sources[0x35]	535885	1			T1	5		T2	254		T3	599
valid_sources[0x36]	498899	1			T1	9		T2	242		T3	653
valid_sources[0x37]	528710	1			T1	6		T2	264		T3	687
valid_sources[0x38]	546331	1			T1	4		T2	256		T3	634
valid_sources[0x39]	582105	1			T1	7		T2	250		T3	611
valid_sources[0x3a]	576125	1			T1	12		T2	240		T3	641
valid_sources[0x3b]	510440	1			T1	8		T2	238		T3	645
valid_sources[0x3c]	1444167	1			T1	7		T2	249		T3	641
valid_sources[0x3d]	537680	1			T1	8		T2	266		T3	645
valid_sources[0x3e]	511893	1			T1	14		T2	283		T3	621
valid_sources[0x3f]	522451	1			T1	8		T2	217		T3	638
valid_sources[0x40]	508085	1			T1	7		T2	259		T3	654
valid_sources[0x41]	602391	1			T1	8		T2	247		T3	605
valid_sources[0x42]	492884	1			T1	7		T2	244		T3	560
valid_sources[0x43]	1314232	1			T1	6		T2	213		T3	627
valid_sources[0x44]	1691321	1			T1	6		T2	264		T3	636
valid_sources[0x45]	525709	1			T1	5		T2	213		T3	634
valid_sources[0x46]	539549	1			T1	8		T2	249		T3	615
valid_sources[0x47]	486372	1			T1	7		T2	227		T3	641
valid_sources[0x48]	511350	1			T1	8		T2	253		T3	618
valid_sources[0x49]	519136	1			T1	10		T2	259		T3	689
valid_sources[0x4a]	589089	1			T1	15		T2	224		T3	557
valid_sources[0x4b]	548848	1			T1	8		T2	225		T3	663
valid_sources[0x4c]	515428	1			T1	6		T2	251		T3	619
valid_sources[0x4d]	482909	1			T1	11		T2	281		T3	611
valid_sources[0x4e]	501884	1			T1	7		T2	257		T3	606
valid_sources[0x4f]	495775	1			T1	12		T2	256		T3	571
valid_sources[0x50]	576009	1			T1	9		T2	220		T3	601
valid_sources[0x51]	498678	1			T1	9		T2	268		T3	617
valid_sources[0x52]	503733	1			T1	7		T2	241		T3	672
valid_sources[0x53]	520383	1			T1	10		T2	248		T3	667
valid_sources[0x54]	499197	1			T1	10		T2	256		T3	637
valid_sources[0x55]	510628	1			T1	9		T2	233		T3	635
valid_sources[0x56]	500813	1			T1	10		T2	201		T3	626
valid_sources[0x57]	514748	1			T1	7		T2	256		T3	617
valid_sources[0x58]	570016	1			T1	5		T2	245		T3	559
valid_sources[0x59]	498983	1			T1	7		T2	261		T3	651
valid_sources[0x5a]	487522	1			T1	3		T2	240		T3	564
valid_sources[0x5b]	516174	1			T1	8		T2	228		T3	658
valid_sources[0x5c]	505649	1			T1	12		T2	261		T3	565
valid_sources[0x5d]	596092	1			T1	7		T2	260		T3	676
valid_sources[0x5e]	489691	1			T1	5		T2	221		T3	618
valid_sources[0x5f]	553419	1			T1	7		T2	232		T3	612
valid_sources[0x60]	505905	1			T1	9		T2	269		T3	671
valid_sources[0x61]	512195	1			T1	6		T2	239		T3	619
valid_sources[0x62]	525255	1			T1	6		T2	243		T3	651
valid_sources[0x63]	496359	1			T1	8		T2	242		T3	596
valid_sources[0x64]	511803	1			T1	8		T2	225		T3	609
valid_sources[0x65]	544849	1			T1	4		T2	207		T3	629
valid_sources[0x66]	492462	1			T1	8		T2	256		T3	664
valid_sources[0x67]	502731	1			T1	9		T2	230		T3	619
valid_sources[0x68]	490524	1			T1	5		T2	225		T3	656
valid_sources[0x69]	497434	1			T1	4		T2	227		T3	664
valid_sources[0x6a]	497716	1			T1	5		T2	263		T3	592
valid_sources[0x6b]	512384	1			T1	7		T2	301		T3	661
valid_sources[0x6c]	516436	1			T1	9		T2	243		T3	720
valid_sources[0x6d]	542908	1			T1	4		T2	210		T3	574
valid_sources[0x6e]	534940	1			T1	6		T2	228		T3	559
valid_sources[0x6f]	495955	1			T1	9		T2	267		T3	603
valid_sources[0x70]	549401	1			T1	15		T2	255		T3	624
valid_sources[0x71]	532841	1			T1	15		T2	255		T3	658
valid_sources[0x72]	579970	1			T1	6		T2	252		T3	643
valid_sources[0x73]	538857	1			T1	9		T2	236		T3	627
valid_sources[0x74]	566359	1			T1	6		T2	224		T3	621
valid_sources[0x75]	1432881	1			T1	7		T2	292		T3	609
valid_sources[0x76]	491390	1			T1	7		T2	294		T3	615
valid_sources[0x77]	492455	1			T1	8		T2	262		T3	660
valid_sources[0x78]	498256	1			T1	5		T2	250		T3	676
valid_sources[0x79]	500452	1			T1	7		T2	256		T3	634
valid_sources[0x7a]	514845	1			T1	7		T2	235		T3	721
valid_sources[0x7b]	490764	1			T1	12		T2	231		T3	548
valid_sources[0x7c]	490875	1			T1	12		T2	237		T3	621
valid_sources[0x7d]	518080	1			T1	9		T2	229		T3	658
valid_sources[0x7e]	503957	1			T1	13		T2	242		T3	669
valid_sources[0x7f]	537348	1			T1	8		T2	241		T3	572
valid_sources[0x80]	527219	1			T1	6		T2	243		T3	598

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

68176580

1

T1

1028

T2

240

T3

72795

values[0x0]

all_enables

biggest_size

35436823

1

T1

495

T2

1424

T3

36708

values[0x1]

all_enables

biggest_size

35428951

1

T1

471

T2

1457

T3

36815

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	48019393	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

132766

1

T1

11

T3

8

T4

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	48038149	1			T1	203754		T2	4689		T3	311772
values[0x0]	55522	1			T1	9		T2	1		T3	13
values[0x1]	58488	1			T1	7		T3	6		T4	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	32018863	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

16133296

1

T1

68103

T2

1569

T3

104064

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	137921	1			T1	732		T3	1194		T5	135
valid_sources[0x01]	142162	1			T1	700		T3	1155		T5	217
valid_sources[0x02]	138139	1			T1	755		T3	1186		T5	166
valid_sources[0x03]	141484	1			T1	841		T3	1426		T5	123
valid_sources[0x04]	139835	1			T1	737		T3	1531		T5	176
valid_sources[0x05]	234869	1			T1	779		T3	1161		T5	109
valid_sources[0x06]	138815	1			T1	734		T3	1280		T5	122
valid_sources[0x07]	483618	1			T1	718		T3	1286		T5	131
valid_sources[0x08]	141323	1			T1	802		T3	1254		T5	150
valid_sources[0x09]	208787	1			T1	752		T3	1124		T5	32
valid_sources[0x0a]	142016	1			T1	785		T3	1191		T5	129
valid_sources[0x0b]	137043	1			T1	867		T3	1149		T5	5
valid_sources[0x0c]	135125	1			T1	815		T3	1201		T5	103
valid_sources[0x0d]	144947	1			T1	731		T3	1193		T5	176
valid_sources[0x0e]	143956	1			T1	785		T3	1365		T5	225
valid_sources[0x0f]	143659	1			T1	874		T3	1253		T5	268
valid_sources[0x10]	151305	1			T1	886		T3	1282		T5	13
valid_sources[0x11]	137570	1			T1	722		T3	1252		T5	118
valid_sources[0x12]	137125	1			T1	739		T3	1204		T5	375
valid_sources[0x13]	238016	1			T1	791		T3	1266		T5	179
valid_sources[0x14]	139965	1			T1	789		T3	1133		T5	357
valid_sources[0x15]	142417	1			T1	831		T3	1244		T5	51
valid_sources[0x16]	138909	1			T1	870		T3	1248		T5	123
valid_sources[0x17]	368085	1			T1	739		T3	1130		T5	266
valid_sources[0x18]	137018	1			T1	756		T3	1156		T5	60
valid_sources[0x19]	139175	1			T1	807		T3	1250		T5	48
valid_sources[0x1a]	145343	1			T1	847		T3	1259		T5	146
valid_sources[0x1b]	137418	1			T1	815		T3	1346		T5	186
valid_sources[0x1c]	154003	1			T1	748		T3	1198		T5	194
valid_sources[0x1d]	233551	1			T1	810		T3	1320		T5	133
valid_sources[0x1e]	467848	1			T1	720		T3	1171		T5	63
valid_sources[0x1f]	139144	1			T1	762		T3	1348		T5	96
valid_sources[0x20]	152662	1			T1	799		T3	1273		T5	309
valid_sources[0x21]	172781	1			T1	741		T3	1428		T5	291
valid_sources[0x22]	138958	1			T1	850		T3	1292		T5	144
valid_sources[0x23]	143513	1			T1	799		T3	1215		T5	124
valid_sources[0x24]	170402	1			T1	869		T3	1105		T5	57
valid_sources[0x25]	138924	1			T1	764		T3	1365		T5	149
valid_sources[0x26]	137268	1			T1	739		T3	1215		T5	193
valid_sources[0x27]	139966	1			T1	778		T3	1235		T5	201
valid_sources[0x28]	140981	1			T1	889		T3	1234		T5	65
valid_sources[0x29]	386062	1			T1	820		T3	1167		T5	94
valid_sources[0x2a]	178636	1			T1	890		T3	1314		T5	26
valid_sources[0x2b]	146318	1			T1	828		T3	1264		T5	67
valid_sources[0x2c]	137670	1			T1	772		T3	1214		T5	368
valid_sources[0x2d]	153983	1			T1	810		T3	1150		T5	49
valid_sources[0x2e]	188863	1			T1	717		T3	1172		T5	220
valid_sources[0x2f]	136985	1			T1	735		T3	1256		T5	249
valid_sources[0x30]	159207	1			T1	812		T3	1186		T5	33
valid_sources[0x31]	349099	1			T1	735		T3	1166		T5	188
valid_sources[0x32]	302840	1			T1	809		T3	1274		T5	122
valid_sources[0x33]	138248	1			T1	786		T3	1287		T5	159
valid_sources[0x34]	174709	1			T1	836		T3	1111		T5	82
valid_sources[0x35]	169322	1			T1	710		T3	1192		T5	95
valid_sources[0x36]	136661	1			T1	829		T3	1225		T5	116
valid_sources[0x37]	135740	1			T1	789		T3	1167		T5	122
valid_sources[0x38]	145842	1			T1	778		T3	1290		T5	134
valid_sources[0x39]	140351	1			T1	723		T3	1285		T5	120
valid_sources[0x3a]	137689	1			T1	810		T3	1232		T5	186
valid_sources[0x3b]	139012	1			T1	895		T3	1106		T5	239
valid_sources[0x3c]	138769	1			T1	800		T3	1273		T5	277
valid_sources[0x3d]	622606	1			T1	792		T3	1216		T5	48
valid_sources[0x3e]	220586	1			T1	788		T3	1208		T5	84
valid_sources[0x3f]	144493	1			T1	736		T3	1124		T5	34
valid_sources[0x40]	135978	1			T1	805		T3	1238		T5	22
valid_sources[0x41]	136344	1			T1	780		T3	1235		T5	143
valid_sources[0x42]	160428	1			T1	798		T3	1185		T5	187
valid_sources[0x43]	144745	1			T1	869		T3	1230		T5	175
valid_sources[0x44]	136917	1			T1	755		T3	1219		T5	125
valid_sources[0x45]	186361	1			T1	899		T3	1408		T5	133
valid_sources[0x46]	143174	1			T1	833		T3	1343		T5	347
valid_sources[0x47]	138179	1			T1	846		T3	1163		T5	93
valid_sources[0x48]	138170	1			T1	758		T3	1394		T5	35
valid_sources[0x49]	136245	1			T1	771		T3	1219		T5	341
valid_sources[0x4a]	146274	1			T1	819		T3	1123		T5	109
valid_sources[0x4b]	170708	1			T1	900		T3	1233		T5	66
valid_sources[0x4c]	136802	1			T1	821		T3	1143		T5	45
valid_sources[0x4d]	141371	1			T1	761		T3	1250		T5	66
valid_sources[0x4e]	138934	1			T1	803		T3	1191		T5	194
valid_sources[0x4f]	140160	1			T1	891		T3	1231		T5	220
valid_sources[0x50]	135301	1			T1	735		T3	1072		T5	255
valid_sources[0x51]	139182	1			T1	753		T3	1342		T5	87
valid_sources[0x52]	140380	1			T1	825		T3	1312		T5	191
valid_sources[0x53]	140100	1			T1	890		T3	1238		T5	78
valid_sources[0x54]	137969	1			T1	818		T3	1197		T5	76
valid_sources[0x55]	139774	1			T1	745		T3	1356		T5	62
valid_sources[0x56]	1057831	1			T1	846		T3	1186		T5	30
valid_sources[0x57]	142872	1			T1	852		T3	1271		T5	131
valid_sources[0x58]	140410	1			T1	759		T3	1253		T5	94
valid_sources[0x59]	386314	1			T1	817		T3	1150		T5	133
valid_sources[0x5a]	138473	1			T1	747		T3	1164		T5	79
valid_sources[0x5b]	169992	1			T1	848		T3	1163		T5	72
valid_sources[0x5c]	163287	1			T1	795		T3	1237		T5	195
valid_sources[0x5d]	136082	1			T1	760		T3	1210		T5	351
valid_sources[0x5e]	463398	1			T1	780		T3	1192		T5	114
valid_sources[0x5f]	724354	1			T1	803		T3	1274		T5	86
valid_sources[0x60]	137423	1			T1	846		T3	1125		T5	79
valid_sources[0x61]	255652	1			T1	827		T3	1312		T5	18
valid_sources[0x62]	174512	1			T1	792		T3	1089		T5	169
valid_sources[0x63]	140101	1			T1	840		T3	1240		T5	115
valid_sources[0x64]	175817	1			T1	751		T3	1158		T5	83
valid_sources[0x65]	444095	1			T1	745		T3	1191		T6	3649
valid_sources[0x66]	155034	1			T1	794		T3	1148		T5	143
valid_sources[0x67]	237762	1			T1	860		T3	1195		T5	196
valid_sources[0x68]	170311	1			T1	877		T3	1178		T5	158
valid_sources[0x69]	139729	1			T1	869		T3	1178		T5	55
valid_sources[0x6a]	159873	1			T1	732		T3	1471		T5	180
valid_sources[0x6b]	438315	1			T1	856		T2	4690		T3	1263
valid_sources[0x6c]	143167	1			T1	823		T3	1184		T5	84
valid_sources[0x6d]	137822	1			T1	877		T3	1241		T5	77
valid_sources[0x6e]	135344	1			T1	818		T3	1245		T5	33
valid_sources[0x6f]	224195	1			T1	746		T3	1100		T5	37
valid_sources[0x70]	137867	1			T1	778		T3	1256		T5	119
valid_sources[0x71]	175686	1			T1	822		T3	1244		T6	3473
valid_sources[0x72]	170316	1			T1	790		T3	1266		T5	421
valid_sources[0x73]	140115	1			T1	806		T3	1370		T5	217
valid_sources[0x74]	538631	1			T1	866		T3	1191		T5	36
valid_sources[0x75]	171820	1			T1	803		T3	1199		T5	155
valid_sources[0x76]	174425	1			T1	780		T3	1248		T5	175
valid_sources[0x77]	136674	1			T1	826		T3	1156		T5	48
valid_sources[0x78]	138298	1			T1	848		T3	1291		T5	191
valid_sources[0x79]	142118	1			T1	784		T3	1297		T5	109
valid_sources[0x7a]	458177	1			T1	703		T3	1226		T5	46
valid_sources[0x7b]	161545	1			T1	770		T3	1126		T5	81
valid_sources[0x7c]	168546	1			T1	788		T3	1229		T5	3
valid_sources[0x7d]	207209	1			T1	762		T3	1217		T5	171
valid_sources[0x7e]	338189	1			T1	794		T3	1032		T5	30
valid_sources[0x7f]	169301	1			T1	847		T3	1185		T5	44
valid_sources[0x80]	147584	1			T1	850		T3	1335		T5	49

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

36266

1

T1

8

T17

874

T18

2

values[0x0]

all_enables

biggest_size

49101

1

T1

3

T3

5

T4

2

values[0x1]

all_enables

biggest_size

47399

1

T3

3

T5

1

T6

9