Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

15738479

1

T1

51

T2

59194

T3

14742

full_word

137159147

1

T1

633

T2

3121

T3

146318

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	152897326	1			T1	684		T2	62315		T3	161060
auto[TlIntgErrCmd]	116	1			T47	5		T48	7		T49	8
auto[TlIntgErrData]	92	1			T47	3		T48	5		T49	5
auto[TlIntgErrBoth]	92	1			T47	2		T48	8		T49	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

74105257

1

T1

349

T2

30922

T3

80225

auto[1]

78792369

1

T1

335

T2

31393

T3

80835

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7765558	1			T1	22		T2	30682		T3	7430
auto[TlIntgErrNone]	partial	auto[1]	7972643	1			T1	29		T2	28512		T3	7312
auto[TlIntgErrNone]	full_word	auto[0]	66339554	1			T1	327		T2	240		T3	72795
auto[TlIntgErrNone]	full_word	auto[1]	70819571	1			T1	306		T2	2881		T3	73523
auto[TlIntgErrCmd]	partial	auto[0]	52	1			T47	3		T48	1		T49	6
auto[TlIntgErrCmd]	partial	auto[1]	58	1			T47	2		T48	6		T49	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T116	1		T120	3		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T121	1		T120	1		-	-
auto[TlIntgErrData]	partial	auto[0]	39	1			T47	1		T48	3		T49	1
auto[TlIntgErrData]	partial	auto[1]	44	1			T47	1		T48	2		T49	4
auto[TlIntgErrData]	full_word	auto[0]	3	1			T122	1		T123	1		T124	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T47	1		T114	1		T118	1
auto[TlIntgErrBoth]	partial	auto[0]	43	1			T48	3		T49	5		T115	1
auto[TlIntgErrBoth]	partial	auto[1]	42	1			T47	2		T48	5		T49	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T49	1		T122	1		T117	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T113	1		T119	1		T125	1