Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.85	100.00	97.56	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1030157410	145151	0	0
ctrl_regwen_rd_A	1030157410	7700	0	0
exec_rd_A	1030157410	7501	0	0
exec_regwen_rd_A	1030157410	8107	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030157410	145151	0	0
T12	918310	0	0	0
T16	521679	0	0	0
T17	87878	4624	0	0
T18	74254	0	0	0
T31	16765	447	0	0
T32	29516	863	0	0
T46	0	3068	0	0
T50	0	85	0	0
T51	0	11	0	0
T52	0	924	0	0
T53	0	66	0	0
T54	0	296	0	0
T55	0	45	0	0
T58	462255	0	0	0
T59	75709	0	0	0
T60	97540	0	0	0
T61	599849	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030157410	7700	0	0
T22	925	0	0	0
T31	16765	97	0	0
T32	29516	181	0	0
T46	57067	0	0	0
T51	0	4	0	0
T52	0	71	0	0
T54	0	12	0	0
T60	97540	0	0	0
T61	599849	0	0	0
T63	0	41	0	0
T64	0	438	0	0
T67	0	9	0	0
T69	0	11	0	0
T73	0	7	0	0
T105	550426	0	0	0
T106	175674	0	0	0
T109	272785	0	0	0
T110	69544	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030157410	7501	0	0
T22	925	0	0	0
T31	16765	117	0	0
T32	29516	168	0	0
T46	57067	0	0	0
T51	0	2	0	0
T52	0	86	0	0
T54	0	31	0	0
T60	97540	0	0	0
T61	599849	0	0	0
T63	0	60	0	0
T64	0	409	0	0
T67	0	8	0	0
T69	0	1	0	0
T73	0	5	0	0
T105	550426	0	0	0
T106	175674	0	0	0
T109	272785	0	0	0
T110	69544	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030157410	8107	0	0
T22	925	0	0	0
T31	16765	87	0	0
T32	29516	169	0	0
T46	57067	0	0	0
T51	0	4	0	0
T52	0	109	0	0
T54	0	17	0	0
T60	97540	0	0	0
T61	599849	0	0	0
T63	0	44	0	0
T64	0	455	0	0
T67	0	8	0	0
T69	0	5	0	0
T73	0	4	0	0
T105	550426	0	0	0
T106	175674	0	0	0
T109	272785	0	0	0
T110	69544	0	0	0