Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

11226280

1

T1

3119

T3

6189

T4

11434

full_word

98871421

1

T1

3089

T2

327680

T3

61147

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	110097391	1			T1	6208		T2	327680		T3	67336
auto[TlIntgErrCmd]	114	1			T34	8		T35	7		T36	8
auto[TlIntgErrData]	110	1			T34	6		T35	9		T36	8
auto[TlIntgErrBoth]	86	1			T34	6		T35	4		T36	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

53166388

1

T1

1406

T2

163840

T3

33642

auto[1]

56931313

1

T1

4802

T2

163840

T3

33694

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrBoth]]	[full_word]	[auto[1]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	5517246	1			T1	625		T3	3118		T4	5685
auto[TlIntgErrNone]	partial	auto[1]	5708752	1			T1	2494		T3	3071		T4	5749
auto[TlIntgErrNone]	full_word	auto[0]	47649006	1			T1	781		T2	163840		T3	30524
auto[TlIntgErrNone]	full_word	auto[1]	51222387	1			T1	2308		T2	163840		T3	30623
auto[TlIntgErrCmd]	partial	auto[0]	41	1			T34	3		T35	4		T36	3
auto[TlIntgErrCmd]	partial	auto[1]	60	1			T34	5		T35	2		T36	4
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T36	1		T105	1		T106	1
auto[TlIntgErrCmd]	full_word	auto[1]	9	1			T35	1		T107	2		T105	2
auto[TlIntgErrData]	partial	auto[0]	50	1			T34	4		T35	2		T36	4
auto[TlIntgErrData]	partial	auto[1]	49	1			T34	1		T35	5		T36	2
auto[TlIntgErrData]	full_word	auto[0]	7	1			T35	1		T36	1		T108	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T34	1		T35	1		T36	1
auto[TlIntgErrBoth]	partial	auto[0]	30	1			T34	3		T35	1		T36	1
auto[TlIntgErrBoth]	partial	auto[1]	52	1			T34	3		T35	2		T36	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T35	1		T105	1		T109	1