Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	672939	1			T4	3562		T29	513		T14	11
auto[1]	7182011	1			T3	861		T4	2423		T9	11792
auto[2]	514754	1			T4	2375		T29	337		T14	3
auto[3]	7014665	1			T3	824		T4	1297		T9	11467

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	9358540	1			T3	1192		T4	7456		T9	19253
auto[1]	1418607	1			T3	235		T4	876		T9	1913
auto[2]	1438580	1			T3	227		T4	1179		T9	1890
auto[3]	3168642	1			T3	31		T4	146		T9	203

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6395079

1

T3

1685

T4

9656

T9

23258

auto[1]

8989290

1

T4

1

T9

1

T10

2

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	253437	1			T4	2963		T29	414		T14	10
auto[0]	auto[0]	auto[1]	26529	1			T4	288		T29	54		T6	1
auto[0]	auto[0]	auto[2]	26568	1			T4	283		T29	44		T6	2
auto[0]	auto[0]	auto[3]	74882	1			T4	28		T29	1		T14	1
auto[0]	auto[1]	auto[0]	1993090	1			T3	608		T4	1858		T9	9768
auto[0]	auto[1]	auto[1]	220249	1			T3	180		T4	334		T9	971
auto[0]	auto[1]	auto[2]	238317	1			T3	56		T4	198		T9	948
auto[0]	auto[1]	auto[3]	464949	1			T3	17		T4	32		T9	104
auto[0]	auto[2]	auto[0]	187830	1			T4	1846		T29	273		T14	2
auto[0]	auto[2]	auto[1]	24552	1			T4	171		T29	22		T14	1
auto[0]	auto[2]	auto[2]	19109	1			T4	318		T29	41		T6	2
auto[0]	auto[2]	auto[3]	54510	1			T4	40		T29	1		T54	472
auto[0]	auto[3]	auto[0]	1918078	1			T3	584		T4	788		T9	9484
auto[0]	auto[3]	auto[1]	226649	1			T3	55		T4	83		T9	942
auto[0]	auto[3]	auto[2]	245323	1			T3	171		T4	380		T9	942
auto[0]	auto[3]	auto[3]	421007	1			T3	14		T4	46		T9	99
auto[1]	auto[0]	auto[0]	9561	1			T55	628		T99	441		T118	724
auto[1]	auto[0]	auto[1]	43430	1			T54	1		T55	2831		T99	1814
auto[1]	auto[0]	auto[2]	43674	1			T55	2804		T99	1824		T118	3359
auto[1]	auto[0]	auto[3]	194858	1			T55	12931		T57	2		T99	7884
auto[1]	auto[1]	auto[0]	2495449	1			T4	1		T9	1		T10	2
auto[1]	auto[1]	auto[1]	437769	1			T13	10219		T30	8966		T89	6155
auto[1]	auto[1]	auto[2]	406203	1			T13	10610		T30	8990		T89	6175
auto[1]	auto[1]	auto[3]	925985	1			T13	1056		T30	858		T89	628
auto[1]	auto[2]	auto[0]	8738	1			T55	612		T99	371		T118	683
auto[1]	auto[2]	auto[1]	38767	1			T55	2633		T99	1645		T118	3095
auto[1]	auto[2]	auto[2]	32989	1			T55	1928		T99	1173		T118	2834
auto[1]	auto[2]	auto[3]	148259	1			T55	8647		T99	5351		T118	12365
auto[1]	auto[3]	auto[0]	2492357	1			T13	105453		T30	89850		T89	61747
auto[1]	auto[3]	auto[1]	400662	1			T13	10464		T30	9023		T89	6103
auto[1]	auto[3]	auto[2]	426397	1			T13	10462		T30	9059		T89	6130
auto[1]	auto[3]	auto[3]	884192	1			T13	1053		T30	959		T89	603