Unified Coverage Report :: Module :: prim_onehot_check

Module : prim_onehot_check

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.89			88.89

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_onehot_check_0/rtl/prim_onehot_check.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg_regs.u_prim_reg_we_check.u_prim_onehot_check	88.89			88.89

---

Module Instance : tb.dut.u_reg_regs.u_prim_reg_we_check.u_prim_onehot_check

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.89			88.89

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.89			88.89

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_reg_we_check

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : prim_onehot_check

	Total	Covered	Percent
Totals	5	4	80.00
Total Bits	18	16	88.89
Total Bits 0->1	9	8	88.89
Total Bits 1->0	9	8	88.89

Ports	5	4	80.00
Port Bits	18	16	88.89
Port Bits 0->1	9	8	88.89
Port Bits 1->0	9	8	88.89

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T14,T5	Yes	T1,T2,T3	INPUT
oh_i[0]	Yes	Yes	*T8,*T15,*T16	Yes	T8,T15,T16	INPUT
oh_i[1]	Unreachable	Unreachable		Unreachable		INPUT
oh_i[5:2]	Yes	Yes	T12,T17,T18	Yes	T12,T17,T18	INPUT
addr_i[2:0]	Unreachable	Unreachable		Unreachable		INPUT
en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
err_o	No	No		No		OUTPUT

*Tests covering at least one bit in the range