Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

15752867

1

T1

15625

T2

4047

T3

53750

full_word

120406482

1

T1

158246

T2

912

T3

539167

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	136159039	1			T1	173871		T2	4959		T3	592917
auto[TlIntgErrCmd]	107	1			T28	7		T43	6		T58	8
auto[TlIntgErrData]	99	1			T28	6		T43	6		T58	6
auto[TlIntgErrBoth]	104	1			T28	7		T43	8		T58	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

65839470

1

T1

87342

T2

2494

T3

266166

auto[1]

70319879

1

T1

86529

T2

2465

T3

326751

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7774378	1			T1	7773		T2	2055		T3	24162
auto[TlIntgErrNone]	partial	auto[1]	7978200	1			T1	7852		T2	1992		T3	29588
auto[TlIntgErrNone]	full_word	auto[0]	58064951	1			T1	79569		T2	439		T3	242004
auto[TlIntgErrNone]	full_word	auto[1]	62341510	1			T1	78677		T2	473		T3	297163
auto[TlIntgErrCmd]	partial	auto[0]	48	1			T28	6		T43	2		T58	3
auto[TlIntgErrCmd]	partial	auto[1]	48	1			T28	1		T43	3		T58	5
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T104	1		T105	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	9	1			T43	1		T49	1		T50	1
auto[TlIntgErrData]	partial	auto[0]	48	1			T28	3		T43	3		T58	3
auto[TlIntgErrData]	partial	auto[1]	45	1			T28	1		T43	3		T58	3
auto[TlIntgErrData]	full_word	auto[0]	2	1			T104	1		T106	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	4	1			T28	2		T102	1		T104	1
auto[TlIntgErrBoth]	partial	auto[0]	39	1			T28	4		T43	3		T58	2
auto[TlIntgErrBoth]	partial	auto[1]	61	1			T28	2		T43	5		T58	4
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T28	1		T104	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T102	1		T107	1		-	-