Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	845121	1			T2	653		T3	12908		T11	8164
auto[1]	10142437	1			T1	73533		T2	535		T3	8379
auto[2]	656503	1			T2	448		T3	7579		T11	5325
auto[3]	9960693	1			T1	72743		T2	336		T3	3986

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	12862170	1			T1	121220		T2	49		T3	25573
auto[1]	2044129	1			T1	11903		T2	266		T3	3040
auto[2]	2066703	1			T1	11925		T2	222		T3	3774
auto[3]	4631752	1			T1	1228		T2	1435		T3	465

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7976812

1

T2

1972

T3

32852

T7

790

auto[1]

13627942

1

T1

146276

T8

140965

T10

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	296611	1			T2	27		T3	10713		T11	6766
auto[0]	auto[0]	auto[1]	31291	1			T2	82		T3	1079		T11	666
auto[0]	auto[0]	auto[2]	31509	1			T2	91		T3	1021		T11	672
auto[0]	auto[0]	auto[3]	103985	1			T2	453		T3	95		T11	60
auto[0]	auto[1]	auto[0]	2592955	1			T2	3		T3	6495		T7	7
auto[0]	auto[1]	auto[1]	282830	1			T2	79		T3	1134		T7	48
auto[0]	auto[1]	auto[2]	294139	1			T2	15		T3	617		T7	21
auto[0]	auto[1]	auto[3]	474625	1			T2	438		T3	133		T7	318
auto[0]	auto[2]	auto[0]	220190	1			T2	17		T3	5886		T11	4122
auto[0]	auto[2]	auto[1]	30438	1			T2	93		T3	590		T11	415
auto[0]	auto[2]	auto[2]	21226	1			T2	49		T3	988		T11	706
auto[0]	auto[2]	auto[3]	72456	1			T2	289		T3	115		T11	82
auto[0]	auto[3]	auto[0]	2516571	1			T2	2		T3	2479		T7	8
auto[0]	auto[3]	auto[1]	281443	1			T2	12		T3	237		T7	18
auto[0]	auto[3]	auto[2]	305008	1			T2	67		T3	1148		T7	73
auto[0]	auto[3]	auto[3]	421535	1			T2	255		T3	122		T7	297
auto[1]	auto[0]	auto[0]	12489	1			T118	819		T121	1		T119	309
auto[1]	auto[0]	auto[1]	56584	1			T118	3676		T119	1479		T120	1839
auto[1]	auto[0]	auto[2]	56747	1			T118	3660		T119	1498		T120	1931
auto[1]	auto[0]	auto[3]	255905	1			T118	16586		T119	6909		T120	8555
auto[1]	auto[1]	auto[0]	3605830	1			T1	61058		T8	58106		T41	57312
auto[1]	auto[1]	auto[1]	678914	1			T1	5939		T8	5826		T41	5650
auto[1]	auto[1]	auto[2]	644089	1			T1	5926		T8	5905		T41	5799
auto[1]	auto[1]	auto[3]	1569055	1			T1	610		T8	569		T41	569
auto[1]	auto[2]	auto[0]	10342	1			T118	486		T119	209		T120	270
auto[1]	auto[2]	auto[1]	47815	1			T13	1		T118	2237		T119	884
auto[1]	auto[2]	auto[2]	45897	1			T118	3888		T119	1414		T120	2055
auto[1]	auto[2]	auto[3]	208139	1			T118	17987		T119	6466		T120	9202
auto[1]	auto[3]	auto[0]	3607182	1			T1	60162		T8	58218		T10	1
auto[1]	auto[3]	auto[1]	634814	1			T1	5964		T8	5901		T41	5726
auto[1]	auto[3]	auto[2]	668088	1			T1	5999		T8	5861		T15	1
auto[1]	auto[3]	auto[3]	1526052	1			T1	618		T8	579		T41	588