Unified Coverage Report :: Module :: prim_fifo_sync_cnt

Module : prim_fifo_sync_cnt

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_tlul_adapter_sram.u_sram_byte.gen_integ_handling.u_sync_fifo.gen_normal_fifo.u_fifo_cnt	100.00	100.00				100.00
tb.dut.u_tlul_adapter_sram.u_sram_byte.gen_integ_handling.u_sync_fifo_a_size.gen_normal_fifo.u_fifo_cnt	100.00	100.00				100.00
tb.dut.u_tlul_adapter_sram.u_reqfifo.gen_normal_fifo.u_fifo_cnt	100.00	100.00				100.00
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt	100.00	100.00				100.00
tb.dut.u_tlul_adapter_sram.u_rspfifo.gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00

---

Module Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte.gen_integ_handling.u_sync_fifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	gen_integ_handling.u_sync_fifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte.gen_integ_handling.u_sync_fifo_a_size.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	gen_integ_handling.u_sync_fifo_a_size

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_tlul_adapter_sram.u_reqfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reqfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_tlul_adapter_sram.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_sramreqfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_rspfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_secure_ptrs.u_rptr	100.00			100.00
gen_secure_ptrs.u_wptr	100.00			100.00

Line Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=1,Width=2,Secure=0 + Depth=2,Width=2,Secure=0 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_tlul_adapter_sram.u_sram_byte.gen_integ_handling.u_sync_fifo.gen_normal_fifo.u_fifo_cnt

SCORE	LINE
100.00	100.00

tb.dut.u_tlul_adapter_sram.u_sram_byte.gen_integ_handling.u_sync_fifo_a_size.gen_normal_fifo.u_fifo_cnt

SCORE	LINE
100.00	100.00

tb.dut.u_tlul_adapter_sram.u_reqfifo.gen_normal_fifo.u_fifo_cnt

SCORE	LINE
100.00	100.00

tb.dut.u_tlul_adapter_sram.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	74	7	7	100.00
ALWAYS	86	7	7	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
74	1	1
75	1	1
76	1	1
77		unreachable
78	1	1
79	1	1
80	1	1
81	1	1
			MISSING_ELSE
86	1	1
87	1	1
88	1	1
89		unreachable
90	1	1
91	1	1
92	1	1
93	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=2,Width=2,Secure=1 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_tlul_adapter_sram.u_rspfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
CONT_ASSIGN	70	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
70	1	1

---

Cond Coverage for Module : prim_fifo_sync_cnt

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       70
 EXPRESSION (gen_secure_ptrs.wptr_err | gen_secure_ptrs.rptr_err)
             ------------1-----------   ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T23,T24
1	0	Covered	T6,T23,T24

---

Branch Coverage for Module : prim_fifo_sync_cnt

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	74	4	4	100.00
IF	86	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	74	if ((!rst_ni))
-2-:	76	if (clr_i)
-3-:	78	if (wptr_wrap)
-4-:	80	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Covered	T1,T2,T3
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	86	if ((!rst_ni))
-2-:	88	if (clr_i)
-3-:	90	if (rptr_wrap)
-4-:	92	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Covered	T1,T2,T3
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte.gen_integ_handling.u_sync_fifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	74	6	6	100.00
ALWAYS	86	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
74	1	1
75	1	1
76	1	1
77		unreachable
78	1	1
79	1	1
80	1	1
81		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
86	1	1
87	1	1
88	1	1
89		unreachable
90	1	1
91	1	1
92	1	1
93		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte.gen_integ_handling.u_sync_fifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	74	3	3	100.00
IF	86	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	74	if ((!rst_ni))
-2-:	76	if (clr_i)
-3-:	78	if (wptr_wrap)
-4-:	80	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Excluded		VC_COV_UNR
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	86	if ((!rst_ni))
-2-:	88	if (clr_i)
-3-:	90	if (rptr_wrap)
-4-:	92	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Excluded		VC_COV_UNR
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte.gen_integ_handling.u_sync_fifo_a_size.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	74	7	7	100.00
ALWAYS	86	7	7	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
74	1	1
75	1	1
76	1	1
77		unreachable
78	1	1
79	1	1
80	1	1
81	1	1
			MISSING_ELSE
86	1	1
87	1	1
88	1	1
89		unreachable
90	1	1
91	1	1
92	1	1
93	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte.gen_integ_handling.u_sync_fifo_a_size.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	74	4	4	100.00
IF	86	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	74	if ((!rst_ni))
-2-:	76	if (clr_i)
-3-:	78	if (wptr_wrap)
-4-:	80	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Covered	T1,T2,T3
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	86	if ((!rst_ni))
-2-:	88	if (clr_i)
-3-:	90	if (rptr_wrap)
-4-:	92	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Covered	T1,T2,T3
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_reqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	74	7	7	100.00
ALWAYS	86	7	7	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
74	1	1
75	1	1
76	1	1
77		unreachable
78	1	1
79	1	1
80	1	1
81	1	1
			MISSING_ELSE
86	1	1
87	1	1
88	1	1
89		unreachable
90	1	1
91	1	1
92	1	1
93	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_reqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	74	4	4	100.00
IF	86	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	74	if ((!rst_ni))
-2-:	76	if (clr_i)
-3-:	78	if (wptr_wrap)
-4-:	80	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Covered	T1,T2,T3
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	86	if ((!rst_ni))
-2-:	88	if (clr_i)
-3-:	90	if (rptr_wrap)
-4-:	92	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Covered	T1,T2,T3
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	74	7	7	100.00
ALWAYS	86	7	7	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
74	1	1
75	1	1
76	1	1
77		unreachable
78	1	1
79	1	1
80	1	1
81	1	1
			MISSING_ELSE
86	1	1
87	1	1
88	1	1
89		unreachable
90	1	1
91	1	1
92	1	1
93	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	74	4	4	100.00
IF	86	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	74	if ((!rst_ni))
-2-:	76	if (clr_i)
-3-:	78	if (wptr_wrap)
-4-:	80	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Covered	T1,T2,T3
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	86	if ((!rst_ni))
-2-:	88	if (clr_i)
-3-:	90	if (rptr_wrap)
-4-:	92	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Covered	T1,T2,T3
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
CONT_ASSIGN	70	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
70	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo.gen_normal_fifo.u_fifo_cnt

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       70
 EXPRESSION (gen_secure_ptrs.wptr_err | gen_secure_ptrs.rptr_err)
             ------------1-----------   ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T23,T24
1	0	Covered	T6,T23,T24