Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.85	100.00	97.56	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	915500288	152878	0	0
ctrl_regwen_rd_A	915500288	4916	0	0
exec_rd_A	915500288	4695	0	0
exec_regwen_rd_A	915500288	4974	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915500288	152878	0	0
T16	128268	5751	0	0
T20	1245	0	0	0
T28	24909	7	0	0
T29	35240	45	0	0
T30	4995	207	0	0
T41	325205	0	0	0
T42	0	97	0	0
T43	0	5	0	0
T44	0	25	0	0
T45	0	27	0	0
T46	0	464	0	0
T54	234226	0	0	0
T55	304969	0	0	0
T56	550671	0	0	0
T57	497306	0	0	0
T58	0	1	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915500288	4916	0	0
T28	24909	83	0	0
T29	35240	0	0	0
T42	34934	0	0	0
T43	15504	52	0	0
T44	34793	6	0	0
T45	34706	27	0	0
T46	0	86	0	0
T47	0	11	0	0
T60	1986	40	0	0
T64	2261	0	0	0
T65	950	0	0	0
T70	0	6	0	0
T90	2086	20	0	0
T98	0	11	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915500288	4695	0	0
T28	24909	78	0	0
T29	35240	0	0	0
T42	34934	0	0	0
T43	15504	65	0	0
T44	34793	34	0	0
T45	34706	32	0	0
T46	0	63	0	0
T47	0	4	0	0
T60	1986	34	0	0
T64	2261	0	0	0
T65	950	0	0	0
T70	0	7	0	0
T90	2086	23	0	0
T98	0	29	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915500288	4974	0	0
T28	24909	104	0	0
T29	35240	0	0	0
T42	34934	0	0	0
T43	15504	40	0	0
T44	34793	14	0	0
T45	34706	11	0	0
T46	0	61	0	0
T47	0	26	0	0
T60	1986	15	0	0
T64	2261	0	0	0
T65	950	0	0	0
T70	0	6	0	0
T90	2086	29	0	0
T98	0	37	0	0