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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.67 100.00 98.27 100.00 100.00 99.71 99.70 100.00


Total test records in report: 970
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T752 /workspace/coverage/default/39.sram_ctrl_stress_all.664122932 Jan 10 01:28:12 PM PST 24 Jan 10 01:58:15 PM PST 24 162379764842 ps
T753 /workspace/coverage/default/44.sram_ctrl_smoke.670312515 Jan 10 01:28:18 PM PST 24 Jan 10 01:29:20 PM PST 24 1443116016 ps
T754 /workspace/coverage/default/20.sram_ctrl_multiple_keys.4002076657 Jan 10 01:26:56 PM PST 24 Jan 10 01:43:23 PM PST 24 42652346129 ps
T755 /workspace/coverage/default/21.sram_ctrl_mem_partial_access.2464067506 Jan 10 01:26:58 PM PST 24 Jan 10 01:28:21 PM PST 24 3519120713 ps
T756 /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.644612931 Jan 10 01:26:58 PM PST 24 Jan 10 01:28:08 PM PST 24 2091827337 ps
T757 /workspace/coverage/default/30.sram_ctrl_ram_cfg.4279241667 Jan 10 01:28:17 PM PST 24 Jan 10 01:29:19 PM PST 24 353196514 ps
T758 /workspace/coverage/default/1.sram_ctrl_mem_partial_access.2681133792 Jan 10 01:25:56 PM PST 24 Jan 10 01:28:27 PM PST 24 31264334364 ps
T759 /workspace/coverage/default/38.sram_ctrl_mem_partial_access.3222746826 Jan 10 01:28:20 PM PST 24 Jan 10 01:31:28 PM PST 24 5043270338 ps
T760 /workspace/coverage/default/10.sram_ctrl_multiple_keys.1369286121 Jan 10 01:26:30 PM PST 24 Jan 10 01:32:51 PM PST 24 4215467199 ps
T761 /workspace/coverage/default/30.sram_ctrl_multiple_keys.1362509709 Jan 10 01:27:55 PM PST 24 Jan 10 01:39:43 PM PST 24 4455205180 ps
T762 /workspace/coverage/default/15.sram_ctrl_stress_pipeline.2334245868 Jan 10 01:26:55 PM PST 24 Jan 10 01:33:54 PM PST 24 10728312420 ps
T763 /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.1609755944 Jan 10 01:28:14 PM PST 24 Jan 10 02:34:06 PM PST 24 2647829089 ps
T764 /workspace/coverage/default/21.sram_ctrl_multiple_keys.934207460 Jan 10 01:27:01 PM PST 24 Jan 10 01:43:45 PM PST 24 164271888892 ps
T765 /workspace/coverage/default/34.sram_ctrl_lc_escalation.1070652111 Jan 10 01:28:19 PM PST 24 Jan 10 01:32:19 PM PST 24 36075155456 ps
T766 /workspace/coverage/default/48.sram_ctrl_executable.2304971775 Jan 10 01:30:44 PM PST 24 Jan 10 01:39:33 PM PST 24 4689245333 ps
T767 /workspace/coverage/default/48.sram_ctrl_partial_access.1184078715 Jan 10 01:30:42 PM PST 24 Jan 10 01:31:08 PM PST 24 2788703730 ps
T768 /workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.988181207 Jan 10 01:27:25 PM PST 24 Jan 10 02:44:39 PM PST 24 896360955 ps
T769 /workspace/coverage/default/39.sram_ctrl_bijection.3507941429 Jan 10 01:28:52 PM PST 24 Jan 10 02:04:17 PM PST 24 93108470995 ps
T770 /workspace/coverage/default/40.sram_ctrl_ram_cfg.2046112153 Jan 10 01:28:13 PM PST 24 Jan 10 01:29:10 PM PST 24 1553544639 ps
T771 /workspace/coverage/default/22.sram_ctrl_bijection.2770147905 Jan 10 01:26:55 PM PST 24 Jan 10 01:47:26 PM PST 24 316808033230 ps
T772 /workspace/coverage/default/3.sram_ctrl_bijection.2639799854 Jan 10 01:26:09 PM PST 24 Jan 10 02:07:58 PM PST 24 579749270074 ps
T773 /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3901821450 Jan 10 01:26:31 PM PST 24 Jan 10 02:02:16 PM PST 24 1220750717 ps
T774 /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.1227713189 Jan 10 01:27:45 PM PST 24 Jan 10 01:30:44 PM PST 24 816997306 ps
T775 /workspace/coverage/default/25.sram_ctrl_stress_all.141549877 Jan 10 01:26:54 PM PST 24 Jan 10 02:16:55 PM PST 24 262596017577 ps
T776 /workspace/coverage/default/13.sram_ctrl_max_throughput.2776109190 Jan 10 01:26:32 PM PST 24 Jan 10 01:27:42 PM PST 24 758329797 ps
T777 /workspace/coverage/default/6.sram_ctrl_regwen.948510193 Jan 10 01:26:35 PM PST 24 Jan 10 01:39:41 PM PST 24 24568280749 ps
T778 /workspace/coverage/default/21.sram_ctrl_lc_escalation.2685751780 Jan 10 01:27:10 PM PST 24 Jan 10 01:32:40 PM PST 24 19414848433 ps
T779 /workspace/coverage/default/47.sram_ctrl_stress_pipeline.2004186627 Jan 10 01:30:43 PM PST 24 Jan 10 01:35:33 PM PST 24 14864051465 ps
T780 /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.1907517202 Jan 10 01:26:47 PM PST 24 Jan 10 01:27:36 PM PST 24 700001102 ps
T781 /workspace/coverage/default/34.sram_ctrl_mem_walk.311457370 Jan 10 01:27:29 PM PST 24 Jan 10 01:29:46 PM PST 24 2083489603 ps
T782 /workspace/coverage/default/38.sram_ctrl_alert_test.1503604782 Jan 10 01:28:44 PM PST 24 Jan 10 01:29:17 PM PST 24 36212078 ps
T783 /workspace/coverage/default/43.sram_ctrl_mem_walk.2908960895 Jan 10 01:28:34 PM PST 24 Jan 10 01:33:47 PM PST 24 13757222651 ps
T784 /workspace/coverage/default/5.sram_ctrl_stress_pipeline.4018727553 Jan 10 01:26:29 PM PST 24 Jan 10 01:29:29 PM PST 24 3092205765 ps
T785 /workspace/coverage/default/44.sram_ctrl_ram_cfg.1933294374 Jan 10 01:28:19 PM PST 24 Jan 10 01:29:19 PM PST 24 1289647823 ps
T786 /workspace/coverage/default/7.sram_ctrl_max_throughput.2030229319 Jan 10 01:26:48 PM PST 24 Jan 10 01:27:47 PM PST 24 4413852792 ps
T787 /workspace/coverage/default/9.sram_ctrl_alert_test.890020247 Jan 10 01:26:41 PM PST 24 Jan 10 01:26:57 PM PST 24 46898991 ps
T788 /workspace/coverage/default/19.sram_ctrl_access_during_key_req.1560380262 Jan 10 01:26:57 PM PST 24 Jan 10 01:39:43 PM PST 24 44625823501 ps
T789 /workspace/coverage/default/17.sram_ctrl_ram_cfg.2197698632 Jan 10 01:27:11 PM PST 24 Jan 10 01:27:29 PM PST 24 1530818444 ps
T790 /workspace/coverage/default/40.sram_ctrl_mem_walk.3725887525 Jan 10 01:28:17 PM PST 24 Jan 10 01:34:47 PM PST 24 86154543591 ps
T791 /workspace/coverage/default/11.sram_ctrl_max_throughput.3425141943 Jan 10 01:26:42 PM PST 24 Jan 10 01:29:17 PM PST 24 778116048 ps
T792 /workspace/coverage/default/37.sram_ctrl_mem_walk.2335381111 Jan 10 01:28:17 PM PST 24 Jan 10 01:31:26 PM PST 24 7166863689 ps
T793 /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.4218954054 Jan 10 01:26:20 PM PST 24 Jan 10 02:47:34 PM PST 24 2352298125 ps
T794 /workspace/coverage/default/18.sram_ctrl_max_throughput.3261767193 Jan 10 01:26:58 PM PST 24 Jan 10 01:28:22 PM PST 24 1429834031 ps
T795 /workspace/coverage/default/7.sram_ctrl_multiple_keys.3948868132 Jan 10 01:26:43 PM PST 24 Jan 10 01:37:26 PM PST 24 42181219336 ps
T796 /workspace/coverage/default/23.sram_ctrl_partial_access.4287342958 Jan 10 01:26:58 PM PST 24 Jan 10 01:27:56 PM PST 24 1043047646 ps
T797 /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.3552329549 Jan 10 01:28:14 PM PST 24 Jan 10 01:29:47 PM PST 24 745108539 ps
T798 /workspace/coverage/default/0.sram_ctrl_stress_pipeline.2582416616 Jan 10 01:26:07 PM PST 24 Jan 10 01:28:47 PM PST 24 4705781198 ps
T799 /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.3317428344 Jan 10 01:26:56 PM PST 24 Jan 10 02:01:55 PM PST 24 3235494178 ps
T800 /workspace/coverage/default/8.sram_ctrl_multiple_keys.1525583476 Jan 10 01:26:32 PM PST 24 Jan 10 01:42:20 PM PST 24 14120952766 ps
T801 /workspace/coverage/default/9.sram_ctrl_stress_pipeline.3158269088 Jan 10 01:26:22 PM PST 24 Jan 10 01:31:48 PM PST 24 17044232164 ps
T802 /workspace/coverage/default/37.sram_ctrl_ram_cfg.1746924511 Jan 10 01:28:18 PM PST 24 Jan 10 01:29:24 PM PST 24 2391591834 ps
T803 /workspace/coverage/default/20.sram_ctrl_partial_access.1920895337 Jan 10 01:26:53 PM PST 24 Jan 10 01:29:12 PM PST 24 1798319062 ps
T804 /workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.4289782326 Jan 10 01:27:41 PM PST 24 Jan 10 02:25:54 PM PST 24 1137237398 ps
T805 /workspace/coverage/default/0.sram_ctrl_mem_walk.1140753870 Jan 10 01:26:01 PM PST 24 Jan 10 01:28:18 PM PST 24 8240944213 ps
T806 /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.1284389762 Jan 10 01:27:41 PM PST 24 Jan 10 01:34:32 PM PST 24 52056382701 ps
T807 /workspace/coverage/default/43.sram_ctrl_alert_test.2357114023 Jan 10 01:28:13 PM PST 24 Jan 10 01:29:05 PM PST 24 13029675 ps
T808 /workspace/coverage/default/6.sram_ctrl_smoke.3856496586 Jan 10 01:26:33 PM PST 24 Jan 10 01:27:28 PM PST 24 5417995991 ps
T809 /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.2358813322 Jan 10 01:26:59 PM PST 24 Jan 10 01:33:52 PM PST 24 6670726148 ps
T810 /workspace/coverage/default/9.sram_ctrl_access_during_key_req.2926757477 Jan 10 01:26:37 PM PST 24 Jan 10 01:28:41 PM PST 24 7208731060 ps
T811 /workspace/coverage/default/12.sram_ctrl_ram_cfg.796273751 Jan 10 01:27:00 PM PST 24 Jan 10 01:27:18 PM PST 24 362966428 ps
T812 /workspace/coverage/default/6.sram_ctrl_access_during_key_req.341895051 Jan 10 01:26:30 PM PST 24 Jan 10 01:46:12 PM PST 24 31058888990 ps
T813 /workspace/coverage/default/13.sram_ctrl_access_during_key_req.4184349043 Jan 10 01:26:54 PM PST 24 Jan 10 01:44:35 PM PST 24 45606440370 ps
T814 /workspace/coverage/default/10.sram_ctrl_access_during_key_req.2997676520 Jan 10 01:26:33 PM PST 24 Jan 10 01:36:01 PM PST 24 7675245037 ps
T815 /workspace/coverage/default/5.sram_ctrl_alert_test.2369161571 Jan 10 01:26:36 PM PST 24 Jan 10 01:26:52 PM PST 24 44517538 ps
T816 /workspace/coverage/default/47.sram_ctrl_mem_walk.915028102 Jan 10 01:30:43 PM PST 24 Jan 10 01:33:19 PM PST 24 35847089788 ps
T817 /workspace/coverage/default/2.sram_ctrl_smoke.1669359524 Jan 10 01:26:07 PM PST 24 Jan 10 01:26:36 PM PST 24 361704153 ps
T818 /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.241986086 Jan 10 01:27:42 PM PST 24 Jan 10 02:48:21 PM PST 24 4921585222 ps
T819 /workspace/coverage/default/10.sram_ctrl_partial_access.1775282230 Jan 10 01:26:25 PM PST 24 Jan 10 01:27:32 PM PST 24 811340999 ps
T820 /workspace/coverage/default/42.sram_ctrl_stress_all.2548379005 Jan 10 01:28:18 PM PST 24 Jan 10 02:20:03 PM PST 24 778873462067 ps
T821 /workspace/coverage/default/7.sram_ctrl_lc_escalation.2940569686 Jan 10 01:26:55 PM PST 24 Jan 10 01:28:47 PM PST 24 10043251386 ps
T822 /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.1333285430 Jan 10 01:26:31 PM PST 24 Jan 10 01:34:55 PM PST 24 168054987640 ps
T823 /workspace/coverage/default/43.sram_ctrl_executable.1363000232 Jan 10 01:28:21 PM PST 24 Jan 10 01:36:18 PM PST 24 2599449895 ps
T824 /workspace/coverage/default/20.sram_ctrl_stress_pipeline.1172420620 Jan 10 01:26:56 PM PST 24 Jan 10 01:29:57 PM PST 24 38012642603 ps
T825 /workspace/coverage/default/37.sram_ctrl_stress_pipeline.3102392845 Jan 10 01:28:09 PM PST 24 Jan 10 01:34:53 PM PST 24 20273185132 ps
T826 /workspace/coverage/default/1.sram_ctrl_bijection.1899549816 Jan 10 01:26:05 PM PST 24 Jan 10 01:43:43 PM PST 24 59023341328 ps
T827 /workspace/coverage/default/4.sram_ctrl_max_throughput.1899384425 Jan 10 01:26:34 PM PST 24 Jan 10 01:27:50 PM PST 24 755500279 ps
T828 /workspace/coverage/default/36.sram_ctrl_mem_walk.2951680034 Jan 10 01:27:54 PM PST 24 Jan 10 01:31:24 PM PST 24 28778985454 ps
T829 /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.2281795465 Jan 10 01:28:01 PM PST 24 Jan 10 01:36:02 PM PST 24 26824657970 ps
T830 /workspace/coverage/default/34.sram_ctrl_partial_access.2997142526 Jan 10 01:28:19 PM PST 24 Jan 10 01:29:24 PM PST 24 1190704599 ps
T831 /workspace/coverage/default/14.sram_ctrl_multiple_keys.1039352499 Jan 10 01:26:48 PM PST 24 Jan 10 01:45:49 PM PST 24 15859340789 ps
T832 /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.241418521 Jan 10 01:28:56 PM PST 24 Jan 10 01:31:26 PM PST 24 826118513 ps
T833 /workspace/coverage/default/36.sram_ctrl_mem_partial_access.572756380 Jan 10 01:27:54 PM PST 24 Jan 10 01:31:00 PM PST 24 6442052670 ps
T834 /workspace/coverage/default/41.sram_ctrl_bijection.4072966788 Jan 10 01:28:01 PM PST 24 Jan 10 02:06:43 PM PST 24 132503631347 ps
T835 /workspace/coverage/default/42.sram_ctrl_smoke.1876476084 Jan 10 01:27:59 PM PST 24 Jan 10 01:29:22 PM PST 24 1592128041 ps
T836 /workspace/coverage/default/13.sram_ctrl_partial_access.1657533387 Jan 10 01:26:34 PM PST 24 Jan 10 01:27:18 PM PST 24 1620710728 ps
T837 /workspace/coverage/default/19.sram_ctrl_partial_access.552975761 Jan 10 01:26:59 PM PST 24 Jan 10 01:27:26 PM PST 24 1344549108 ps
T838 /workspace/coverage/default/30.sram_ctrl_mem_partial_access.2928447601 Jan 10 01:28:07 PM PST 24 Jan 10 01:30:22 PM PST 24 7870771556 ps
T839 /workspace/coverage/default/45.sram_ctrl_bijection.2357168239 Jan 10 01:28:18 PM PST 24 Jan 10 01:40:57 PM PST 24 21745294971 ps
T840 /workspace/coverage/default/22.sram_ctrl_multiple_keys.1461406747 Jan 10 01:27:02 PM PST 24 Jan 10 01:41:45 PM PST 24 37549790404 ps
T841 /workspace/coverage/default/37.sram_ctrl_max_throughput.3971751874 Jan 10 01:28:15 PM PST 24 Jan 10 01:30:18 PM PST 24 7358017880 ps
T842 /workspace/coverage/default/41.sram_ctrl_stress_pipeline.591051384 Jan 10 01:28:17 PM PST 24 Jan 10 01:35:58 PM PST 24 61784313947 ps
T843 /workspace/coverage/default/14.sram_ctrl_ram_cfg.559747433 Jan 10 01:26:56 PM PST 24 Jan 10 01:27:22 PM PST 24 713616515 ps
T844 /workspace/coverage/default/9.sram_ctrl_regwen.1807168636 Jan 10 01:26:35 PM PST 24 Jan 10 01:34:13 PM PST 24 2382805543 ps
T845 /workspace/coverage/default/23.sram_ctrl_mem_partial_access.1613137867 Jan 10 01:27:10 PM PST 24 Jan 10 01:29:40 PM PST 24 5941665525 ps
T846 /workspace/coverage/default/25.sram_ctrl_alert_test.3663581357 Jan 10 01:27:07 PM PST 24 Jan 10 01:27:16 PM PST 24 20228527 ps
T847 /workspace/coverage/default/19.sram_ctrl_alert_test.2827742383 Jan 10 01:26:52 PM PST 24 Jan 10 01:27:05 PM PST 24 14581287 ps
T848 /workspace/coverage/default/38.sram_ctrl_bijection.3202441648 Jan 10 01:28:57 PM PST 24 Jan 10 01:38:29 PM PST 24 24271628205 ps
T849 /workspace/coverage/default/12.sram_ctrl_alert_test.1354458125 Jan 10 01:26:33 PM PST 24 Jan 10 01:26:47 PM PST 24 28417199 ps
T850 /workspace/coverage/default/20.sram_ctrl_lc_escalation.2827475718 Jan 10 01:27:09 PM PST 24 Jan 10 01:29:20 PM PST 24 39877468648 ps
T851 /workspace/coverage/default/20.sram_ctrl_access_during_key_req.3544754105 Jan 10 01:26:50 PM PST 24 Jan 10 01:44:22 PM PST 24 17818734083 ps
T852 /workspace/coverage/default/41.sram_ctrl_lc_escalation.2493061824 Jan 10 01:28:17 PM PST 24 Jan 10 01:30:12 PM PST 24 25830646154 ps
T853 /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.2416509491 Jan 10 01:26:34 PM PST 24 Jan 10 01:29:18 PM PST 24 4602700854 ps
T854 /workspace/coverage/default/32.sram_ctrl_max_throughput.2565839736 Jan 10 01:27:34 PM PST 24 Jan 10 01:30:11 PM PST 24 836396588 ps
T855 /workspace/coverage/default/20.sram_ctrl_regwen.925768766 Jan 10 01:26:57 PM PST 24 Jan 10 01:35:56 PM PST 24 8425855389 ps
T856 /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.1117017383 Jan 10 01:26:34 PM PST 24 Jan 10 01:32:44 PM PST 24 11370788146 ps
T857 /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.3906274264 Jan 10 01:26:08 PM PST 24 Jan 10 01:36:22 PM PST 24 57992404414 ps
T858 /workspace/coverage/default/24.sram_ctrl_smoke.1144564001 Jan 10 01:27:00 PM PST 24 Jan 10 01:27:39 PM PST 24 380021060 ps
T859 /workspace/coverage/default/27.sram_ctrl_smoke.1240034097 Jan 10 01:27:30 PM PST 24 Jan 10 01:29:28 PM PST 24 2195456475 ps
T860 /workspace/coverage/default/12.sram_ctrl_bijection.198001683 Jan 10 01:26:57 PM PST 24 Jan 10 01:46:16 PM PST 24 17385647344 ps
T861 /workspace/coverage/default/21.sram_ctrl_access_during_key_req.4222487003 Jan 10 01:27:01 PM PST 24 Jan 10 01:29:44 PM PST 24 4117484700 ps
T862 /workspace/coverage/default/46.sram_ctrl_mem_walk.2700813670 Jan 10 01:28:22 PM PST 24 Jan 10 01:31:50 PM PST 24 35833082613 ps
T863 /workspace/coverage/default/14.sram_ctrl_stress_pipeline.2260200144 Jan 10 01:26:57 PM PST 24 Jan 10 01:32:13 PM PST 24 17807320917 ps
T864 /workspace/coverage/default/46.sram_ctrl_lc_escalation.2981538695 Jan 10 01:28:42 PM PST 24 Jan 10 01:29:43 PM PST 24 2290453226 ps
T865 /workspace/coverage/default/15.sram_ctrl_multiple_keys.338319803 Jan 10 01:26:52 PM PST 24 Jan 10 01:32:27 PM PST 24 3387041772 ps
T866 /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.4152120460 Jan 10 01:29:01 PM PST 24 Jan 10 01:31:41 PM PST 24 3087348535 ps
T867 /workspace/coverage/default/1.sram_ctrl_smoke.732700841 Jan 10 01:26:15 PM PST 24 Jan 10 01:27:59 PM PST 24 5054565925 ps
T868 /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.1203610046 Jan 10 01:25:53 PM PST 24 Jan 10 01:41:28 PM PST 24 186944678 ps
T869 /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.321599353 Jan 10 01:31:04 PM PST 24 Jan 10 01:51:36 PM PST 24 518550953 ps
T870 /workspace/coverage/default/7.sram_ctrl_mem_partial_access.792872457 Jan 10 01:26:38 PM PST 24 Jan 10 01:28:14 PM PST 24 2698620096 ps
T871 /workspace/coverage/default/30.sram_ctrl_executable.4122165611 Jan 10 01:27:46 PM PST 24 Jan 10 01:42:24 PM PST 24 17589293470 ps
T872 /workspace/coverage/default/46.sram_ctrl_smoke.3219056332 Jan 10 01:28:20 PM PST 24 Jan 10 01:29:32 PM PST 24 4052056933 ps
T873 /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.214571261 Jan 10 01:31:00 PM PST 24 Jan 10 02:10:51 PM PST 24 4406147562 ps
T874 /workspace/coverage/default/43.sram_ctrl_partial_access.2074882346 Jan 10 01:28:18 PM PST 24 Jan 10 01:29:39 PM PST 24 1649226835 ps
T875 /workspace/coverage/default/12.sram_ctrl_mem_walk.309263168 Jan 10 01:26:58 PM PST 24 Jan 10 01:29:11 PM PST 24 8226557593 ps
T876 /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.941660172 Jan 10 01:28:16 PM PST 24 Jan 10 01:36:33 PM PST 24 267399145346 ps
T877 /workspace/coverage/default/29.sram_ctrl_multiple_keys.885795490 Jan 10 01:28:34 PM PST 24 Jan 10 01:41:08 PM PST 24 16572080415 ps
T878 /workspace/coverage/default/10.sram_ctrl_smoke.2491698497 Jan 10 01:26:30 PM PST 24 Jan 10 01:29:10 PM PST 24 11270627014 ps
T879 /workspace/coverage/default/37.sram_ctrl_access_during_key_req.3954801666 Jan 10 01:28:17 PM PST 24 Jan 10 01:36:17 PM PST 24 3902888272 ps
T880 /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.1596065353 Jan 10 01:30:45 PM PST 24 Jan 10 01:33:09 PM PST 24 3218563835 ps
T881 /workspace/coverage/default/29.sram_ctrl_mem_walk.1709990213 Jan 10 01:27:46 PM PST 24 Jan 10 01:30:56 PM PST 24 4699915666 ps
T882 /workspace/coverage/default/22.sram_ctrl_alert_test.328216909 Jan 10 01:27:04 PM PST 24 Jan 10 01:27:15 PM PST 24 19768354 ps
T883 /workspace/coverage/default/47.sram_ctrl_stress_all.4094124573 Jan 10 01:30:41 PM PST 24 Jan 10 03:07:29 PM PST 24 388845942076 ps
T884 /workspace/coverage/default/27.sram_ctrl_stress_pipeline.3025468870 Jan 10 01:27:41 PM PST 24 Jan 10 01:33:38 PM PST 24 16377087410 ps
T885 /workspace/coverage/default/22.sram_ctrl_partial_access.453166010 Jan 10 01:26:55 PM PST 24 Jan 10 01:27:15 PM PST 24 535082838 ps
T886 /workspace/coverage/default/38.sram_ctrl_access_during_key_req.1897639766 Jan 10 01:29:01 PM PST 24 Jan 10 01:48:17 PM PST 24 74126684616 ps
T887 /workspace/coverage/default/23.sram_ctrl_stress_pipeline.2721031008 Jan 10 01:27:16 PM PST 24 Jan 10 01:31:46 PM PST 24 43177682955 ps
T888 /workspace/coverage/default/27.sram_ctrl_access_during_key_req.3457523967 Jan 10 01:28:13 PM PST 24 Jan 10 01:57:26 PM PST 24 53731903661 ps
T889 /workspace/coverage/default/47.sram_ctrl_multiple_keys.878153429 Jan 10 01:28:46 PM PST 24 Jan 10 01:33:27 PM PST 24 78866169907 ps
T890 /workspace/coverage/default/28.sram_ctrl_bijection.3236133563 Jan 10 01:28:10 PM PST 24 Jan 10 01:58:03 PM PST 24 288132183998 ps
T891 /workspace/coverage/default/0.sram_ctrl_stress_all.1874975963 Jan 10 01:26:14 PM PST 24 Jan 10 01:41:15 PM PST 24 20615358278 ps
T892 /workspace/coverage/default/22.sram_ctrl_mem_partial_access.397585035 Jan 10 01:27:05 PM PST 24 Jan 10 01:29:29 PM PST 24 3142332549 ps
T893 /workspace/coverage/default/49.sram_ctrl_mem_walk.2160696703 Jan 10 01:31:03 PM PST 24 Jan 10 01:35:22 PM PST 24 32824311886 ps
T894 /workspace/coverage/default/23.sram_ctrl_mem_walk.1608350102 Jan 10 01:26:58 PM PST 24 Jan 10 01:31:36 PM PST 24 13933963104 ps
T895 /workspace/coverage/default/41.sram_ctrl_partial_access.2462134368 Jan 10 01:28:14 PM PST 24 Jan 10 01:29:27 PM PST 24 767227677 ps
T896 /workspace/coverage/default/5.sram_ctrl_mem_partial_access.4140206340 Jan 10 01:26:27 PM PST 24 Jan 10 01:27:57 PM PST 24 4673273655 ps
T897 /workspace/coverage/default/45.sram_ctrl_partial_access.3796382768 Jan 10 01:28:37 PM PST 24 Jan 10 01:30:28 PM PST 24 1269711651 ps
T898 /workspace/coverage/default/14.sram_ctrl_mem_walk.877186458 Jan 10 01:26:56 PM PST 24 Jan 10 01:32:20 PM PST 24 41313843676 ps
T899 /workspace/coverage/default/2.sram_ctrl_stress_all.1981561586 Jan 10 01:25:56 PM PST 24 Jan 10 02:28:19 PM PST 24 134615025507 ps
T900 /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.478915772 Jan 10 01:27:44 PM PST 24 Jan 10 01:36:02 PM PST 24 32358503803 ps
T901 /workspace/coverage/default/25.sram_ctrl_regwen.4198478868 Jan 10 01:27:01 PM PST 24 Jan 10 01:42:46 PM PST 24 152211615816 ps
T902 /workspace/coverage/default/7.sram_ctrl_bijection.1491353660 Jan 10 01:26:42 PM PST 24 Jan 10 01:42:24 PM PST 24 34491089547 ps
T903 /workspace/coverage/default/33.sram_ctrl_max_throughput.729543179 Jan 10 01:27:58 PM PST 24 Jan 10 01:29:24 PM PST 24 3710853787 ps
T904 /workspace/coverage/default/42.sram_ctrl_mem_partial_access.397937169 Jan 10 01:28:17 PM PST 24 Jan 10 01:31:16 PM PST 24 1569230908 ps
T905 /workspace/coverage/default/3.sram_ctrl_mem_walk.1350958249 Jan 10 01:26:26 PM PST 24 Jan 10 01:28:43 PM PST 24 2058202756 ps
T906 /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3172723502 Jan 10 01:28:53 PM PST 24 Jan 10 02:14:52 PM PST 24 228917922 ps
T907 /workspace/coverage/default/46.sram_ctrl_max_throughput.3428941748 Jan 10 01:28:43 PM PST 24 Jan 10 01:31:20 PM PST 24 801672252 ps
T908 /workspace/coverage/default/41.sram_ctrl_multiple_keys.2457375626 Jan 10 01:28:00 PM PST 24 Jan 10 01:45:28 PM PST 24 11932589216 ps
T909 /workspace/coverage/default/18.sram_ctrl_ram_cfg.8802975 Jan 10 01:26:58 PM PST 24 Jan 10 01:27:16 PM PST 24 1532037520 ps
T910 /workspace/coverage/default/31.sram_ctrl_stress_pipeline.3322732783 Jan 10 01:28:52 PM PST 24 Jan 10 01:31:49 PM PST 24 9411401523 ps
T911 /workspace/coverage/default/48.sram_ctrl_mem_partial_access.4284403857 Jan 10 01:30:45 PM PST 24 Jan 10 01:33:21 PM PST 24 16846313798 ps
T912 /workspace/coverage/default/19.sram_ctrl_ram_cfg.1411485654 Jan 10 01:26:50 PM PST 24 Jan 10 01:27:17 PM PST 24 695844136 ps
T913 /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.2971622713 Jan 10 01:26:57 PM PST 24 Jan 10 01:36:40 PM PST 24 11653948668 ps
T914 /workspace/coverage/default/35.sram_ctrl_regwen.218450923 Jan 10 01:28:00 PM PST 24 Jan 10 01:29:40 PM PST 24 2316852903 ps
T915 /workspace/coverage/default/30.sram_ctrl_max_throughput.852632216 Jan 10 01:28:11 PM PST 24 Jan 10 01:29:46 PM PST 24 3047970225 ps
T916 /workspace/coverage/default/15.sram_ctrl_ram_cfg.2092070298 Jan 10 01:26:57 PM PST 24 Jan 10 01:27:15 PM PST 24 754439295 ps
T917 /workspace/coverage/default/33.sram_ctrl_lc_escalation.3263150217 Jan 10 01:27:59 PM PST 24 Jan 10 01:29:47 PM PST 24 5643780246 ps
T918 /workspace/coverage/default/12.sram_ctrl_regwen.825772745 Jan 10 01:26:56 PM PST 24 Jan 10 01:32:37 PM PST 24 5336930480 ps
T919 /workspace/coverage/default/19.sram_ctrl_regwen.943130199 Jan 10 01:26:57 PM PST 24 Jan 10 01:32:25 PM PST 24 26454881453 ps
T920 /workspace/coverage/default/13.sram_ctrl_lc_escalation.1211110441 Jan 10 01:26:52 PM PST 24 Jan 10 01:30:14 PM PST 24 8613752661 ps
T921 /workspace/coverage/default/10.sram_ctrl_max_throughput.1073217547 Jan 10 01:26:29 PM PST 24 Jan 10 01:28:29 PM PST 24 779805175 ps
T922 /workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.2135190832 Jan 10 01:28:17 PM PST 24 Jan 10 02:55:03 PM PST 24 574521434 ps
T923 /workspace/coverage/default/11.sram_ctrl_mem_walk.92528818 Jan 10 01:26:48 PM PST 24 Jan 10 01:29:26 PM PST 24 7037557940 ps
T924 /workspace/coverage/default/1.sram_ctrl_lc_escalation.1757750115 Jan 10 01:26:04 PM PST 24 Jan 10 01:27:05 PM PST 24 20382866966 ps
T925 /workspace/coverage/default/37.sram_ctrl_lc_escalation.3791495366 Jan 10 01:28:17 PM PST 24 Jan 10 01:30:14 PM PST 24 20934295381 ps
T926 /workspace/coverage/default/23.sram_ctrl_regwen.2967930115 Jan 10 01:27:07 PM PST 24 Jan 10 01:40:34 PM PST 24 8767243696 ps
T927 /workspace/coverage/default/44.sram_ctrl_mem_partial_access.4109514757 Jan 10 01:28:17 PM PST 24 Jan 10 01:31:48 PM PST 24 9526632061 ps
T928 /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.2388609574 Jan 10 01:26:50 PM PST 24 Jan 10 01:29:44 PM PST 24 811486540 ps
T929 /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.142545906 Jan 10 01:28:56 PM PST 24 Jan 10 01:36:03 PM PST 24 25916214362 ps
T930 /workspace/coverage/default/49.sram_ctrl_multiple_keys.1481080848 Jan 10 01:31:01 PM PST 24 Jan 10 01:44:55 PM PST 24 40886636075 ps
T931 /workspace/coverage/default/36.sram_ctrl_stress_pipeline.3491545234 Jan 10 01:27:45 PM PST 24 Jan 10 01:33:30 PM PST 24 6451869153 ps
T932 /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.1873227776 Jan 10 01:28:21 PM PST 24 Jan 10 01:38:10 PM PST 24 16378747233 ps
T933 /workspace/coverage/default/27.sram_ctrl_max_throughput.847684472 Jan 10 01:27:57 PM PST 24 Jan 10 01:29:24 PM PST 24 722205614 ps
T934 /workspace/coverage/default/4.sram_ctrl_multiple_keys.1363433748 Jan 10 01:26:32 PM PST 24 Jan 10 01:49:06 PM PST 24 16499414273 ps
T935 /workspace/coverage/default/9.sram_ctrl_max_throughput.957847992 Jan 10 01:26:34 PM PST 24 Jan 10 01:27:49 PM PST 24 3050474481 ps
T936 /workspace/coverage/default/14.sram_ctrl_stress_all.1289517403 Jan 10 01:26:48 PM PST 24 Jan 10 02:19:31 PM PST 24 142863877793 ps
T937 /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.3862719764 Jan 10 01:27:57 PM PST 24 Jan 10 01:31:20 PM PST 24 3126897578 ps
T938 /workspace/coverage/default/41.sram_ctrl_mem_partial_access.973205116 Jan 10 01:28:01 PM PST 24 Jan 10 01:30:18 PM PST 24 3762363598 ps
T939 /workspace/coverage/default/40.sram_ctrl_access_during_key_req.890984131 Jan 10 01:27:59 PM PST 24 Jan 10 01:50:13 PM PST 24 6089203625 ps
T940 /workspace/coverage/default/3.sram_ctrl_ram_cfg.3949859683 Jan 10 01:26:21 PM PST 24 Jan 10 01:26:44 PM PST 24 345899847 ps
T941 /workspace/coverage/default/1.sram_ctrl_alert_test.2177624103 Jan 10 01:25:59 PM PST 24 Jan 10 01:26:15 PM PST 24 13343296 ps
T942 /workspace/coverage/default/45.sram_ctrl_smoke.1479747973 Jan 10 01:28:14 PM PST 24 Jan 10 01:29:21 PM PST 24 710066301 ps
T943 /workspace/coverage/default/33.sram_ctrl_stress_pipeline.1143933210 Jan 10 01:28:10 PM PST 24 Jan 10 01:35:09 PM PST 24 4238944503 ps
T944 /workspace/coverage/default/28.sram_ctrl_stress_pipeline.520775816 Jan 10 01:28:12 PM PST 24 Jan 10 01:33:29 PM PST 24 3546674528 ps
T945 /workspace/coverage/default/0.sram_ctrl_access_during_key_req.1115673068 Jan 10 01:26:11 PM PST 24 Jan 10 01:40:25 PM PST 24 24964278806 ps
T35 /workspace/coverage/default/2.sram_ctrl_sec_cm.2823965608 Jan 10 01:26:08 PM PST 24 Jan 10 01:26:34 PM PST 24 566132329 ps
T946 /workspace/coverage/default/3.sram_ctrl_partial_access.3182680483 Jan 10 01:26:12 PM PST 24 Jan 10 01:26:56 PM PST 24 789930383 ps
T947 /workspace/coverage/default/3.sram_ctrl_smoke.3759481848 Jan 10 01:26:06 PM PST 24 Jan 10 01:27:04 PM PST 24 3708561256 ps
T948 /workspace/coverage/default/48.sram_ctrl_alert_test.2888400549 Jan 10 01:31:00 PM PST 24 Jan 10 01:31:02 PM PST 24 24281265 ps
T949 /workspace/coverage/default/43.sram_ctrl_smoke.3337926996 Jan 10 01:28:17 PM PST 24 Jan 10 01:29:27 PM PST 24 1121346374 ps
T950 /workspace/coverage/default/41.sram_ctrl_alert_test.420595367 Jan 10 01:28:16 PM PST 24 Jan 10 01:29:06 PM PST 24 26141382 ps
T951 /workspace/coverage/default/42.sram_ctrl_max_throughput.558433406 Jan 10 01:28:13 PM PST 24 Jan 10 01:31:56 PM PST 24 906953207 ps
T952 /workspace/coverage/default/27.sram_ctrl_ram_cfg.359970930 Jan 10 01:28:00 PM PST 24 Jan 10 01:29:19 PM PST 24 1350649188 ps
T953 /workspace/coverage/default/28.sram_ctrl_mem_partial_access.3019316706 Jan 10 01:28:19 PM PST 24 Jan 10 01:30:22 PM PST 24 2569138645 ps
T954 /workspace/coverage/default/36.sram_ctrl_partial_access.331365783 Jan 10 01:27:58 PM PST 24 Jan 10 01:31:29 PM PST 24 2851102120 ps
T955 /workspace/coverage/default/47.sram_ctrl_mem_partial_access.3890530624 Jan 10 01:30:43 PM PST 24 Jan 10 01:33:26 PM PST 24 4609997553 ps
T956 /workspace/coverage/default/24.sram_ctrl_stress_pipeline.1205886463 Jan 10 01:26:58 PM PST 24 Jan 10 01:31:59 PM PST 24 3818935092 ps
T957 /workspace/coverage/default/26.sram_ctrl_partial_access.1215186613 Jan 10 01:27:07 PM PST 24 Jan 10 01:27:42 PM PST 24 693940393 ps
T958 /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.3307103193 Jan 10 01:28:53 PM PST 24 Jan 10 01:36:48 PM PST 24 6983994010 ps
T959 /workspace/coverage/default/16.sram_ctrl_bijection.3386074921 Jan 10 01:26:52 PM PST 24 Jan 10 01:57:07 PM PST 24 46043319676 ps
T960 /workspace/coverage/default/30.sram_ctrl_partial_access.1328032215 Jan 10 01:27:47 PM PST 24 Jan 10 01:29:25 PM PST 24 2842912186 ps
T961 /workspace/coverage/default/22.sram_ctrl_mem_walk.311161680 Jan 10 01:26:55 PM PST 24 Jan 10 01:29:10 PM PST 24 8231858572 ps
T962 /workspace/coverage/default/37.sram_ctrl_bijection.3404178678 Jan 10 01:27:58 PM PST 24 Jan 10 01:38:24 PM PST 24 8637537622 ps
T963 /workspace/coverage/default/34.sram_ctrl_mem_partial_access.2808435721 Jan 10 01:27:47 PM PST 24 Jan 10 01:31:20 PM PST 24 7679822054 ps
T964 /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.3828541883 Jan 10 01:28:57 PM PST 24 Jan 10 01:36:00 PM PST 24 56102791101 ps
T965 /workspace/coverage/default/28.sram_ctrl_stress_all.4120528210 Jan 10 01:28:20 PM PST 24 Jan 10 02:38:19 PM PST 24 1563740495405 ps
T966 /workspace/coverage/default/4.sram_ctrl_mem_walk.2274407911 Jan 10 01:26:36 PM PST 24 Jan 10 01:29:50 PM PST 24 178806540575 ps
T967 /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.597962044 Jan 10 01:26:57 PM PST 24 Jan 10 01:27:55 PM PST 24 734372009 ps
T968 /workspace/coverage/default/34.sram_ctrl_stress_pipeline.1783491534 Jan 10 01:28:18 PM PST 24 Jan 10 01:35:22 PM PST 24 29516476030 ps
T969 /workspace/coverage/default/48.sram_ctrl_stress_all.1953927979 Jan 10 01:31:01 PM PST 24 Jan 10 03:00:27 PM PST 24 192737709186 ps
T970 /workspace/coverage/default/47.sram_ctrl_regwen.404571054 Jan 10 01:30:42 PM PST 24 Jan 10 01:44:01 PM PST 24 16906401534 ps

Test location /workspace/coverage/default/41.sram_ctrl_stress_all.1968982965
Short name T3
Test name
Test status
Simulation time 322520915826 ps
CPU time 4742.03 seconds
Started Jan 10 01:27:59 PM PST 24
Finished Jan 10 02:47:59 PM PST 24
Peak memory 383236 kb
Host smart-d5d294b2-f821-47fc-a9b9-5b095a5486e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968982965 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 41.sram_ctrl_stress_all.1968982965
Directory /workspace/41.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.3871892899
Short name T16
Test name
Test status
Simulation time 1295658906 ps
CPU time 5156.05 seconds
Started Jan 10 01:26:57 PM PST 24
Finished Jan 10 02:53:05 PM PST 24
Peak memory 450648 kb
Host smart-562493d2-ade1-475d-9409-f35242f444ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3871892899 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all_with_rand_reset.3871892899
Directory /workspace/15.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3401869283
Short name T28
Test name
Test status
Simulation time 259505338 ps
CPU time 2.34 seconds
Started Jan 10 12:53:07 PM PST 24
Finished Jan 10 12:54:19 PM PST 24
Peak memory 202456 kb
Host smart-7b6e5127-22d1-4ba4-bb7a-aa9d27f0e41d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401869283 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 13.sram_ctrl_tl_intg_err.3401869283
Directory /workspace/13.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.sram_ctrl_sec_cm.847405575
Short name T6
Test name
Test status
Simulation time 322687788 ps
CPU time 1.8 seconds
Started Jan 10 01:25:58 PM PST 24
Finished Jan 10 01:26:15 PM PST 24
Peak memory 223832 kb
Host smart-52e4ddeb-caf5-451d-a896-8fc26661554f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847405575 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.sram_ctrl_sec_cm.847405575
Directory /workspace/1.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.4172093042
Short name T118
Test name
Test status
Simulation time 29330942689 ps
CPU time 726.95 seconds
Started Jan 10 01:27:16 PM PST 24
Finished Jan 10 01:39:25 PM PST 24
Peak memory 202076 kb
Host smart-9cac8769-7a8b-4903-9a3c-10896ac421de
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172093042 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 18.sram_ctrl_partial_access_b2b.4172093042
Directory /workspace/18.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.2917262191
Short name T93
Test name
Test status
Simulation time 63684879458 ps
CPU time 473.15 seconds
Started Jan 10 01:26:04 PM PST 24
Finished Jan 10 01:34:15 PM PST 24
Peak memory 202164 kb
Host smart-bf17d34b-c467-4200-813d-249ceea613d5
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917262191 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 1.sram_ctrl_partial_access_b2b.2917262191
Directory /workspace/1.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/33.sram_ctrl_stress_all.1118370678
Short name T114
Test name
Test status
Simulation time 338781210816 ps
CPU time 6040.55 seconds
Started Jan 10 01:28:16 PM PST 24
Finished Jan 10 03:09:47 PM PST 24
Peak memory 377140 kb
Host smart-fb1fee00-a1bc-40fe-9cab-73827684af5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118370678 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 33.sram_ctrl_stress_all.1118370678
Directory /workspace/33.sram_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1155483559
Short name T67
Test name
Test status
Simulation time 14656444535 ps
CPU time 270.66 seconds
Started Jan 10 12:53:07 PM PST 24
Finished Jan 10 12:58:49 PM PST 24
Peak memory 202524 kb
Host smart-c56acca6-26fa-4496-b51a-28cc8078cafa
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155483559 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 7.sram_ctrl_passthru_mem_tl_intg_err.1155483559
Directory /workspace/7.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/15.sram_ctrl_access_during_key_req.18562150
Short name T18
Test name
Test status
Simulation time 8333678065 ps
CPU time 1069.3 seconds
Started Jan 10 01:26:48 PM PST 24
Finished Jan 10 01:44:51 PM PST 24
Peak memory 372116 kb
Host smart-ce6ddaec-b29f-4626-9c74-8ca7f52cd22a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18562150 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 15.sram_ctrl_access_during_key_req.18562150
Directory /workspace/15.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/11.sram_ctrl_ram_cfg.3602040154
Short name T32
Test name
Test status
Simulation time 1707380145 ps
CPU time 5.57 seconds
Started Jan 10 01:26:46 PM PST 24
Finished Jan 10 01:27:06 PM PST 24
Peak memory 202372 kb
Host smart-bd84b46f-c012-4191-833b-ed72841ac58c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602040154 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.3602040154
Directory /workspace/11.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1200388279
Short name T173
Test name
Test status
Simulation time 546687069 ps
CPU time 2.39 seconds
Started Jan 10 12:54:49 PM PST 24
Finished Jan 10 12:55:58 PM PST 24
Peak memory 201008 kb
Host smart-b05a60ae-32f0-4067-b48c-7ebd493125f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200388279 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 4.sram_ctrl_tl_intg_err.1200388279
Directory /workspace/4.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/29.sram_ctrl_stress_all.1487145275
Short name T115
Test name
Test status
Simulation time 209596193353 ps
CPU time 3808.03 seconds
Started Jan 10 01:27:25 PM PST 24
Finished Jan 10 02:30:55 PM PST 24
Peak memory 372720 kb
Host smart-412d6972-e51f-482c-8de3-4169fb25c555
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487145275 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 29.sram_ctrl_stress_all.1487145275
Directory /workspace/29.sram_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1993039499
Short name T104
Test name
Test status
Simulation time 873946305 ps
CPU time 2.21 seconds
Started Jan 10 12:52:58 PM PST 24
Finished Jan 10 12:54:12 PM PST 24
Peak memory 202352 kb
Host smart-c6fe59f9-64c0-441e-aac3-73ca046757e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993039499 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 10.sram_ctrl_tl_intg_err.1993039499
Directory /workspace/10.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.sram_ctrl_regwen.3922907652
Short name T15
Test name
Test status
Simulation time 8603628442 ps
CPU time 58.31 seconds
Started Jan 10 01:26:01 PM PST 24
Finished Jan 10 01:27:15 PM PST 24
Peak memory 300268 kb
Host smart-e26d0063-6662-4acb-b708-c22627c92336
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922907652 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.3922907652
Directory /workspace/1.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/16.sram_ctrl_alert_test.4114299754
Short name T218
Test name
Test status
Simulation time 16756361 ps
CPU time 0.66 seconds
Started Jan 10 01:26:58 PM PST 24
Finished Jan 10 01:27:11 PM PST 24
Peak memory 201400 kb
Host smart-77f3c0e6-1111-491c-b806-ef29e353cd53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114299754 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.sram_ctrl_alert_test.4114299754
Directory /workspace/16.sram_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2367991379
Short name T102
Test name
Test status
Simulation time 628988264 ps
CPU time 2.23 seconds
Started Jan 10 12:53:16 PM PST 24
Finished Jan 10 12:54:31 PM PST 24
Peak memory 202304 kb
Host smart-025eca33-a19b-4b10-979a-f28aa3c3edf7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367991379 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 18.sram_ctrl_tl_intg_err.2367991379
Directory /workspace/18.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.sram_ctrl_lc_escalation.184155467
Short name T254
Test name
Test status
Simulation time 11856422745 ps
CPU time 256 seconds
Started Jan 10 01:26:25 PM PST 24
Finished Jan 10 01:30:56 PM PST 24
Peak memory 210412 kb
Host smart-9bd6216c-b736-44a2-9982-f8d036d6d968
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184155467 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_esc
alation.184155467
Directory /workspace/10.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.215683586
Short name T188
Test name
Test status
Simulation time 29103198 ps
CPU time 0.67 seconds
Started Jan 10 12:52:52 PM PST 24
Finished Jan 10 12:54:04 PM PST 24
Peak memory 202092 kb
Host smart-11762fa9-93f0-4378-9c65-7e4bb435bffa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215683586 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.sram_ctrl_csr_aliasing.215683586
Directory /workspace/0.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1673582939
Short name T171
Test name
Test status
Simulation time 41340673 ps
CPU time 1.85 seconds
Started Jan 10 12:53:00 PM PST 24
Finished Jan 10 12:54:13 PM PST 24
Peak memory 202048 kb
Host smart-fb92f35a-b6e7-4467-9c23-a48935be052c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673582939 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.sram_ctrl_csr_bit_bash.1673582939
Directory /workspace/0.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3246300983
Short name T70
Test name
Test status
Simulation time 33593387 ps
CPU time 0.62 seconds
Started Jan 10 12:53:05 PM PST 24
Finished Jan 10 12:54:20 PM PST 24
Peak memory 201304 kb
Host smart-cf1dd252-c145-4963-80e1-b9bef1afce70
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246300983 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.sram_ctrl_csr_hw_reset.3246300983
Directory /workspace/0.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1975025750
Short name T98
Test name
Test status
Simulation time 385342342 ps
CPU time 5.13 seconds
Started Jan 10 12:52:59 PM PST 24
Finished Jan 10 12:54:16 PM PST 24
Peak memory 210612 kb
Host smart-da879043-e820-4a99-9a85-ba7fe2ab7584
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975025750 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_mem_rw_with_rand_reset.1975025750
Directory /workspace/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2109292550
Short name T180
Test name
Test status
Simulation time 11967313 ps
CPU time 0.63 seconds
Started Jan 10 12:53:03 PM PST 24
Finished Jan 10 12:54:16 PM PST 24
Peak memory 201100 kb
Host smart-348eeed6-e51c-4ddb-b688-86d95edeb09f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109292550 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 0.sram_ctrl_csr_rw.2109292550
Directory /workspace/0.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.359111059
Short name T61
Test name
Test status
Simulation time 28157482617 ps
CPU time 271.65 seconds
Started Jan 10 12:52:52 PM PST 24
Finished Jan 10 12:58:43 PM PST 24
Peak memory 210648 kb
Host smart-c643d4ef-37b7-4626-9ec9-bd059f714316
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359111059 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.sram_ctrl_passthru_mem_tl_intg_err.359111059
Directory /workspace/0.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3518007249
Short name T148
Test name
Test status
Simulation time 204000076 ps
CPU time 0.74 seconds
Started Jan 10 12:52:54 PM PST 24
Finished Jan 10 12:54:07 PM PST 24
Peak memory 202072 kb
Host smart-ca275128-1f6b-43bd-aaa9-b556e2e7c2a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518007249 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.sram_ctrl_same_csr_outstanding.3518007249
Directory /workspace/0.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2065122275
Short name T200
Test name
Test status
Simulation time 75892558 ps
CPU time 2.21 seconds
Started Jan 10 12:52:54 PM PST 24
Finished Jan 10 12:54:08 PM PST 24
Peak memory 202280 kb
Host smart-594f1823-1908-449d-b657-bf16a2cac2aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065122275 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 0.sram_ctrl_tl_errors.2065122275
Directory /workspace/0.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2604326785
Short name T43
Test name
Test status
Simulation time 620218664 ps
CPU time 2.23 seconds
Started Jan 10 12:53:00 PM PST 24
Finished Jan 10 12:54:14 PM PST 24
Peak memory 202352 kb
Host smart-746c8603-5e09-4516-91a2-3b5038d178f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604326785 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 0.sram_ctrl_tl_intg_err.2604326785
Directory /workspace/0.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1016710472
Short name T65
Test name
Test status
Simulation time 19409305 ps
CPU time 0.66 seconds
Started Jan 10 12:53:02 PM PST 24
Finished Jan 10 12:54:17 PM PST 24
Peak memory 201372 kb
Host smart-18f75454-190c-46a3-b7cf-120ead972869
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016710472 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.sram_ctrl_csr_aliasing.1016710472
Directory /workspace/1.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.269394448
Short name T133
Test name
Test status
Simulation time 261481121 ps
CPU time 1.37 seconds
Started Jan 10 12:53:04 PM PST 24
Finished Jan 10 12:54:15 PM PST 24
Peak memory 202112 kb
Host smart-e89bd8fd-2562-4094-aa58-0324cc58b741
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269394448 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.sram_ctrl_csr_bit_bash.269394448
Directory /workspace/1.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1158835184
Short name T140
Test name
Test status
Simulation time 40708291 ps
CPU time 0.67 seconds
Started Jan 10 12:52:55 PM PST 24
Finished Jan 10 12:54:09 PM PST 24
Peak memory 202192 kb
Host smart-f9042473-ce08-49c8-8d96-cd71c1edfefc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158835184 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.sram_ctrl_csr_hw_reset.1158835184
Directory /workspace/1.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1280182136
Short name T158
Test name
Test status
Simulation time 440254278 ps
CPU time 5.39 seconds
Started Jan 10 12:53:04 PM PST 24
Finished Jan 10 12:54:19 PM PST 24
Peak memory 202468 kb
Host smart-89263409-04c2-4900-9d30-edcd5a2135fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280182136 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_mem_rw_with_rand_reset.1280182136
Directory /workspace/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.265347023
Short name T77
Test name
Test status
Simulation time 27250109 ps
CPU time 0.65 seconds
Started Jan 10 12:53:03 PM PST 24
Finished Jan 10 12:54:15 PM PST 24
Peak memory 202048 kb
Host smart-985298bb-4a27-4bbb-a6c8-d1e8564a6922
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265347023 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.sram_ctrl_csr_rw.265347023
Directory /workspace/1.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.427187131
Short name T129
Test name
Test status
Simulation time 6626357380 ps
CPU time 59.88 seconds
Started Jan 10 12:52:50 PM PST 24
Finished Jan 10 12:55:01 PM PST 24
Peak memory 202480 kb
Host smart-5431fc78-4a53-4c5f-869b-2bcfcff7a8fd
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427187131 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.sram_ctrl_passthru_mem_tl_intg_err.427187131
Directory /workspace/1.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.525153604
Short name T161
Test name
Test status
Simulation time 79920644 ps
CPU time 0.75 seconds
Started Jan 10 12:52:58 PM PST 24
Finished Jan 10 12:54:11 PM PST 24
Peak memory 202060 kb
Host smart-a815cbed-4dc5-4ee4-9fe8-61e1cd240f7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525153604 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.sram_ctrl_same_csr_outstanding.525153604
Directory /workspace/1.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3710274495
Short name T149
Test name
Test status
Simulation time 56167334 ps
CPU time 2.06 seconds
Started Jan 10 12:53:00 PM PST 24
Finished Jan 10 12:54:14 PM PST 24
Peak memory 202356 kb
Host smart-6bef1e5a-db07-4b29-b9a2-e6136fefc2ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710274495 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 1.sram_ctrl_tl_errors.3710274495
Directory /workspace/1.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3472647582
Short name T101
Test name
Test status
Simulation time 499674335 ps
CPU time 1.54 seconds
Started Jan 10 12:52:55 PM PST 24
Finished Jan 10 12:54:09 PM PST 24
Peak memory 202328 kb
Host smart-8b308cae-d9bf-4c95-87ca-8fc7b4411b0c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472647582 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 1.sram_ctrl_tl_intg_err.3472647582
Directory /workspace/1.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3422427340
Short name T135
Test name
Test status
Simulation time 371851718 ps
CPU time 6.28 seconds
Started Jan 10 12:53:04 PM PST 24
Finished Jan 10 12:54:22 PM PST 24
Peak memory 202364 kb
Host smart-03d8f464-cfd9-45d7-adab-f5dd6d47be12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422427340 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_mem_rw_with_rand_reset.3422427340
Directory /workspace/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3114677442
Short name T74
Test name
Test status
Simulation time 12985598 ps
CPU time 0.66 seconds
Started Jan 10 12:52:58 PM PST 24
Finished Jan 10 12:54:10 PM PST 24
Peak memory 202020 kb
Host smart-823b84e2-8f66-4181-9971-e44bc8100061
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114677442 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 10.sram_ctrl_csr_rw.3114677442
Directory /workspace/10.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2527957318
Short name T130
Test name
Test status
Simulation time 7240182187 ps
CPU time 116.58 seconds
Started Jan 10 12:53:02 PM PST 24
Finished Jan 10 12:56:10 PM PST 24
Peak memory 202540 kb
Host smart-7430b944-6e8f-4b92-b6ef-8a311975453a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527957318 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 10.sram_ctrl_passthru_mem_tl_intg_err.2527957318
Directory /workspace/10.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2652828476
Short name T90
Test name
Test status
Simulation time 21973728 ps
CPU time 0.71 seconds
Started Jan 10 12:55:07 PM PST 24
Finished Jan 10 12:56:13 PM PST 24
Peak memory 201540 kb
Host smart-4938d317-cf01-477d-8086-665ef77e4fa1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652828476 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.sram_ctrl_same_csr_outstanding.2652828476
Directory /workspace/10.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1923001129
Short name T46
Test name
Test status
Simulation time 532003522 ps
CPU time 4.72 seconds
Started Jan 10 12:53:11 PM PST 24
Finished Jan 10 12:54:29 PM PST 24
Peak memory 202420 kb
Host smart-78484a61-27e7-4aa9-9bdd-57f595be6647
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923001129 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 10.sram_ctrl_tl_errors.1923001129
Directory /workspace/10.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3493394324
Short name T166
Test name
Test status
Simulation time 680166284 ps
CPU time 4.9 seconds
Started Jan 10 12:52:58 PM PST 24
Finished Jan 10 12:54:15 PM PST 24
Peak memory 202296 kb
Host smart-158fb844-dd75-46e5-b939-a1feb65ec66b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493394324 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_mem_rw_with_rand_reset.3493394324
Directory /workspace/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.583808046
Short name T182
Test name
Test status
Simulation time 41993999 ps
CPU time 0.63 seconds
Started Jan 10 12:53:03 PM PST 24
Finished Jan 10 12:54:15 PM PST 24
Peak memory 201260 kb
Host smart-9c1e8403-e653-4304-8c4d-ca2919b78757
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583808046 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 11.sram_ctrl_csr_rw.583808046
Directory /workspace/11.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1613669632
Short name T204
Test name
Test status
Simulation time 3859098777 ps
CPU time 139.31 seconds
Started Jan 10 12:55:05 PM PST 24
Finished Jan 10 12:58:30 PM PST 24
Peak memory 210376 kb
Host smart-bb81e969-d2e4-40a1-b2f2-3fbeb4920529
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613669632 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 11.sram_ctrl_passthru_mem_tl_intg_err.1613669632
Directory /workspace/11.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3848945689
Short name T176
Test name
Test status
Simulation time 71953570 ps
CPU time 0.73 seconds
Started Jan 10 12:52:59 PM PST 24
Finished Jan 10 12:54:14 PM PST 24
Peak memory 202248 kb
Host smart-5a068bc1-ab7c-49ec-adcf-265f047bb9f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848945689 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.sram_ctrl_same_csr_outstanding.3848945689
Directory /workspace/11.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.445139278
Short name T51
Test name
Test status
Simulation time 538479987 ps
CPU time 4.4 seconds
Started Jan 10 12:53:04 PM PST 24
Finished Jan 10 12:54:20 PM PST 24
Peak memory 202348 kb
Host smart-38e67a3e-d4cb-43d8-8c1e-680db7340a7b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445139278 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
11.sram_ctrl_tl_errors.445139278
Directory /workspace/11.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3541193351
Short name T205
Test name
Test status
Simulation time 214115221 ps
CPU time 1.35 seconds
Started Jan 10 12:53:02 PM PST 24
Finished Jan 10 12:54:14 PM PST 24
Peak memory 202388 kb
Host smart-275752a2-f908-4f80-b4c8-f38edc62163b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541193351 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 11.sram_ctrl_tl_intg_err.3541193351
Directory /workspace/11.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.293147385
Short name T156
Test name
Test status
Simulation time 701725868 ps
CPU time 5.35 seconds
Started Jan 10 12:53:08 PM PST 24
Finished Jan 10 12:54:24 PM PST 24
Peak memory 210480 kb
Host smart-500036f6-1d76-49fb-8f2f-7daaea658657
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293147385 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_mem_rw_with_rand_reset.293147385
Directory /workspace/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2403649347
Short name T177
Test name
Test status
Simulation time 29595733 ps
CPU time 0.61 seconds
Started Jan 10 12:53:01 PM PST 24
Finished Jan 10 12:54:12 PM PST 24
Peak memory 201352 kb
Host smart-0afd0787-c7dd-432a-9fe2-d53098cede1e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403649347 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 12.sram_ctrl_csr_rw.2403649347
Directory /workspace/12.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2690530744
Short name T132
Test name
Test status
Simulation time 3838607260 ps
CPU time 135.96 seconds
Started Jan 10 12:53:28 PM PST 24
Finished Jan 10 12:56:57 PM PST 24
Peak memory 202520 kb
Host smart-2347f303-4be5-48fe-a6dc-d6ba8eb5d70f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690530744 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 12.sram_ctrl_passthru_mem_tl_intg_err.2690530744
Directory /workspace/12.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1949666938
Short name T178
Test name
Test status
Simulation time 12716194 ps
CPU time 0.66 seconds
Started Jan 10 12:53:06 PM PST 24
Finished Jan 10 12:54:18 PM PST 24
Peak memory 201960 kb
Host smart-15c31d4b-496b-423e-a43d-479ce3dd7a23
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949666938 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.sram_ctrl_same_csr_outstanding.1949666938
Directory /workspace/12.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3814060525
Short name T30
Test name
Test status
Simulation time 208187332 ps
CPU time 2.18 seconds
Started Jan 10 12:53:01 PM PST 24
Finished Jan 10 12:54:15 PM PST 24
Peak memory 202408 kb
Host smart-cf2ca382-d2bc-4fc7-a0c5-0a6f89697ea8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814060525 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 12.sram_ctrl_tl_errors.3814060525
Directory /workspace/12.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.29849526
Short name T199
Test name
Test status
Simulation time 176122276 ps
CPU time 1.44 seconds
Started Jan 10 12:53:01 PM PST 24
Finished Jan 10 12:54:14 PM PST 24
Peak memory 202316 kb
Host smart-386b41dd-5892-45c5-b655-c931a386fc24
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29849526 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_te
st +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.sram_ctrl_tl_intg_err.29849526
Directory /workspace/12.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1778418795
Short name T29
Test name
Test status
Simulation time 1409717541 ps
CPU time 6.29 seconds
Started Jan 10 12:53:12 PM PST 24
Finished Jan 10 12:54:31 PM PST 24
Peak memory 210592 kb
Host smart-5ffb11f1-9cb2-432e-9926-70f12121154a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778418795 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_mem_rw_with_rand_reset.1778418795
Directory /workspace/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3757499897
Short name T75
Test name
Test status
Simulation time 112622633 ps
CPU time 0.65 seconds
Started Jan 10 12:53:07 PM PST 24
Finished Jan 10 12:54:19 PM PST 24
Peak memory 202000 kb
Host smart-9059e886-12cd-4082-a202-c07ae21ad2a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757499897 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 13.sram_ctrl_csr_rw.3757499897
Directory /workspace/13.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2648607981
Short name T154
Test name
Test status
Simulation time 23041090712 ps
CPU time 149.41 seconds
Started Jan 10 12:53:13 PM PST 24
Finished Jan 10 12:56:55 PM PST 24
Peak memory 202524 kb
Host smart-ff64174e-664e-4285-8777-82b41d7d4fca
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648607981 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 13.sram_ctrl_passthru_mem_tl_intg_err.2648607981
Directory /workspace/13.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2022516314
Short name T175
Test name
Test status
Simulation time 102276638 ps
CPU time 0.66 seconds
Started Jan 10 12:53:04 PM PST 24
Finished Jan 10 12:54:16 PM PST 24
Peak memory 202236 kb
Host smart-9e86062b-3b3f-4662-ac47-516d742311eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022516314 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.sram_ctrl_same_csr_outstanding.2022516314
Directory /workspace/13.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2827369003
Short name T152
Test name
Test status
Simulation time 130794716 ps
CPU time 2.58 seconds
Started Jan 10 12:53:07 PM PST 24
Finished Jan 10 12:54:19 PM PST 24
Peak memory 210668 kb
Host smart-3fe73f9f-9879-4b94-91b4-f26cc99f11ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827369003 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 13.sram_ctrl_tl_errors.2827369003
Directory /workspace/13.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3939003964
Short name T47
Test name
Test status
Simulation time 2022771697 ps
CPU time 5.08 seconds
Started Jan 10 12:53:14 PM PST 24
Finished Jan 10 12:54:31 PM PST 24
Peak memory 202464 kb
Host smart-603fd900-068c-4950-bdef-4b68eba11d0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939003964 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_mem_rw_with_rand_reset.3939003964
Directory /workspace/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1001829956
Short name T127
Test name
Test status
Simulation time 13541078 ps
CPU time 0.67 seconds
Started Jan 10 12:53:06 PM PST 24
Finished Jan 10 12:54:19 PM PST 24
Peak memory 202048 kb
Host smart-304cd1a8-02cd-4b33-bbff-d2d09c0606e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001829956 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 14.sram_ctrl_csr_rw.1001829956
Directory /workspace/14.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2753989893
Short name T163
Test name
Test status
Simulation time 7424571871 ps
CPU time 60.21 seconds
Started Jan 10 12:53:07 PM PST 24
Finished Jan 10 12:55:17 PM PST 24
Peak memory 210736 kb
Host smart-ba128570-b919-4d1b-8d0b-b1c735e11a77
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753989893 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 14.sram_ctrl_passthru_mem_tl_intg_err.2753989893
Directory /workspace/14.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.4267284935
Short name T73
Test name
Test status
Simulation time 49395384 ps
CPU time 0.66 seconds
Started Jan 10 12:53:06 PM PST 24
Finished Jan 10 12:54:19 PM PST 24
Peak memory 202172 kb
Host smart-4d3ae1c6-3a7e-42d9-980f-1ba712c2d3ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267284935 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.sram_ctrl_same_csr_outstanding.4267284935
Directory /workspace/14.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2159441847
Short name T208
Test name
Test status
Simulation time 58802288 ps
CPU time 2.3 seconds
Started Jan 10 12:53:08 PM PST 24
Finished Jan 10 12:54:22 PM PST 24
Peak memory 202316 kb
Host smart-b29bc857-f5d2-418b-9f43-0a9a2297edad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159441847 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 14.sram_ctrl_tl_errors.2159441847
Directory /workspace/14.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1764612852
Short name T100
Test name
Test status
Simulation time 339366338 ps
CPU time 1.57 seconds
Started Jan 10 12:53:05 PM PST 24
Finished Jan 10 12:54:21 PM PST 24
Peak memory 202364 kb
Host smart-20112fbf-9cf5-4fc7-842f-9dd9867128cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764612852 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 14.sram_ctrl_tl_intg_err.1764612852
Directory /workspace/14.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.840662999
Short name T45
Test name
Test status
Simulation time 2313912143 ps
CPU time 6.02 seconds
Started Jan 10 12:53:07 PM PST 24
Finished Jan 10 12:54:25 PM PST 24
Peak memory 210728 kb
Host smart-d2c0f101-95cd-4c3c-8654-cdb0fd66a667
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840662999 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_mem_rw_with_rand_reset.840662999
Directory /workspace/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3736000697
Short name T84
Test name
Test status
Simulation time 177237877 ps
CPU time 0.63 seconds
Started Jan 10 12:53:07 PM PST 24
Finished Jan 10 12:54:19 PM PST 24
Peak memory 201392 kb
Host smart-2ee9d9ed-1ac2-4d24-9d04-6757ebb9ea59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736000697 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 15.sram_ctrl_csr_rw.3736000697
Directory /workspace/15.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2221557784
Short name T68
Test name
Test status
Simulation time 8107489148 ps
CPU time 296.44 seconds
Started Jan 10 12:53:07 PM PST 24
Finished Jan 10 12:59:15 PM PST 24
Peak memory 210772 kb
Host smart-f8ee7d52-e10f-4d50-9aea-ba7c8c8aa2ec
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221557784 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 15.sram_ctrl_passthru_mem_tl_intg_err.2221557784
Directory /workspace/15.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.645541030
Short name T142
Test name
Test status
Simulation time 66616922 ps
CPU time 0.67 seconds
Started Jan 10 12:53:04 PM PST 24
Finished Jan 10 12:54:16 PM PST 24
Peak memory 201888 kb
Host smart-0ada72e2-cd63-4aac-954b-a9a8d319a6da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645541030 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.sram_ctrl_same_csr_outstanding.645541030
Directory /workspace/15.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1465411574
Short name T168
Test name
Test status
Simulation time 77541495 ps
CPU time 2.11 seconds
Started Jan 10 12:53:13 PM PST 24
Finished Jan 10 12:54:28 PM PST 24
Peak memory 210612 kb
Host smart-1f55064b-ea7c-496b-bf7e-e3dbca029957
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465411574 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 15.sram_ctrl_tl_errors.1465411574
Directory /workspace/15.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2606274520
Short name T53
Test name
Test status
Simulation time 417800763 ps
CPU time 1.45 seconds
Started Jan 10 12:53:12 PM PST 24
Finished Jan 10 12:54:25 PM PST 24
Peak memory 202408 kb
Host smart-a3b9281d-3a65-4bca-b44c-702065e53a0d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606274520 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 15.sram_ctrl_tl_intg_err.2606274520
Directory /workspace/15.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2246734164
Short name T172
Test name
Test status
Simulation time 404393094 ps
CPU time 12.98 seconds
Started Jan 10 12:53:15 PM PST 24
Finished Jan 10 12:54:40 PM PST 24
Peak memory 210716 kb
Host smart-24d050df-db84-4c70-bf99-619ed190fd42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246734164 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_mem_rw_with_rand_reset.2246734164
Directory /workspace/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.247969213
Short name T138
Test name
Test status
Simulation time 15811632 ps
CPU time 0.65 seconds
Started Jan 10 12:53:13 PM PST 24
Finished Jan 10 12:54:26 PM PST 24
Peak memory 201500 kb
Host smart-e595461c-9dac-4cb9-b61b-a9e92aeb83c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247969213 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 16.sram_ctrl_csr_rw.247969213
Directory /workspace/16.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1279044934
Short name T181
Test name
Test status
Simulation time 3956753105 ps
CPU time 62.42 seconds
Started Jan 10 12:53:12 PM PST 24
Finished Jan 10 12:55:26 PM PST 24
Peak memory 210792 kb
Host smart-ac588e89-68aa-4119-8f17-b7248c80e018
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279044934 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 16.sram_ctrl_passthru_mem_tl_intg_err.1279044934
Directory /workspace/16.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.687167304
Short name T147
Test name
Test status
Simulation time 27259638 ps
CPU time 0.81 seconds
Started Jan 10 12:53:12 PM PST 24
Finished Jan 10 12:54:25 PM PST 24
Peak memory 202164 kb
Host smart-eed4ec52-1943-4e17-a4ad-0898a1dcc628
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687167304 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.sram_ctrl_same_csr_outstanding.687167304
Directory /workspace/16.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.370126711
Short name T203
Test name
Test status
Simulation time 314824038 ps
CPU time 4.51 seconds
Started Jan 10 12:53:04 PM PST 24
Finished Jan 10 12:54:19 PM PST 24
Peak memory 202388 kb
Host smart-ca6b140c-7a0b-47ee-9816-dff6e50c5fbb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370126711 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
16.sram_ctrl_tl_errors.370126711
Directory /workspace/16.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.608030448
Short name T144
Test name
Test status
Simulation time 415883718 ps
CPU time 2.15 seconds
Started Jan 10 12:53:14 PM PST 24
Finished Jan 10 12:54:28 PM PST 24
Peak memory 202436 kb
Host smart-69703597-5aa6-4b93-afe1-066caa167cc0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608030448 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 16.sram_ctrl_tl_intg_err.608030448
Directory /workspace/16.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3571664393
Short name T42
Test name
Test status
Simulation time 363933467 ps
CPU time 13.8 seconds
Started Jan 10 12:53:19 PM PST 24
Finished Jan 10 12:54:45 PM PST 24
Peak memory 210624 kb
Host smart-607f1ac4-e794-461e-9dbd-8f66d857275e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571664393 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_mem_rw_with_rand_reset.3571664393
Directory /workspace/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1843808031
Short name T159
Test name
Test status
Simulation time 11496482 ps
CPU time 0.65 seconds
Started Jan 10 12:53:17 PM PST 24
Finished Jan 10 12:54:31 PM PST 24
Peak memory 201472 kb
Host smart-6bae5ac4-af88-44c8-9092-9fe0bd52281b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843808031 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 17.sram_ctrl_csr_rw.1843808031
Directory /workspace/17.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1142735792
Short name T78
Test name
Test status
Simulation time 14073058796 ps
CPU time 271.37 seconds
Started Jan 10 12:53:12 PM PST 24
Finished Jan 10 12:58:55 PM PST 24
Peak memory 210764 kb
Host smart-cec81007-b92b-4ca6-8eaa-556868b6598d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142735792 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 17.sram_ctrl_passthru_mem_tl_intg_err.1142735792
Directory /workspace/17.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.4165448231
Short name T128
Test name
Test status
Simulation time 18060487 ps
CPU time 0.66 seconds
Started Jan 10 12:53:13 PM PST 24
Finished Jan 10 12:54:26 PM PST 24
Peak memory 201708 kb
Host smart-450f99c2-41ef-40a8-a090-755f56b3ac74
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165448231 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.sram_ctrl_same_csr_outstanding.4165448231
Directory /workspace/17.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1586406391
Short name T162
Test name
Test status
Simulation time 38459458 ps
CPU time 1.79 seconds
Started Jan 10 12:53:19 PM PST 24
Finished Jan 10 12:54:33 PM PST 24
Peak memory 202400 kb
Host smart-e45b98b6-18cc-46fe-bfae-01055858bc1d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586406391 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 17.sram_ctrl_tl_errors.1586406391
Directory /workspace/17.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2122576939
Short name T105
Test name
Test status
Simulation time 211354439 ps
CPU time 1.63 seconds
Started Jan 10 12:53:14 PM PST 24
Finished Jan 10 12:54:28 PM PST 24
Peak memory 202408 kb
Host smart-a7c81626-ee4d-4557-9176-fe5cad5c9887
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122576939 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 17.sram_ctrl_tl_intg_err.2122576939
Directory /workspace/17.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3831877695
Short name T155
Test name
Test status
Simulation time 683542903 ps
CPU time 5.15 seconds
Started Jan 10 12:53:17 PM PST 24
Finished Jan 10 12:54:35 PM PST 24
Peak memory 202364 kb
Host smart-668616b4-d942-4091-8118-a0fc776ce5a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831877695 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_mem_rw_with_rand_reset.3831877695
Directory /workspace/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3395046278
Short name T209
Test name
Test status
Simulation time 18668121 ps
CPU time 0.68 seconds
Started Jan 10 12:53:13 PM PST 24
Finished Jan 10 12:54:26 PM PST 24
Peak memory 201492 kb
Host smart-4d87525c-ce53-42d6-8db8-48ae7f594216
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395046278 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 18.sram_ctrl_csr_rw.3395046278
Directory /workspace/18.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3884539267
Short name T85
Test name
Test status
Simulation time 7033593780 ps
CPU time 267.27 seconds
Started Jan 10 12:53:14 PM PST 24
Finished Jan 10 12:58:53 PM PST 24
Peak memory 202564 kb
Host smart-89bc1fa3-e2c6-4768-a492-3248ec8ccec4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884539267 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 18.sram_ctrl_passthru_mem_tl_intg_err.3884539267
Directory /workspace/18.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.269881967
Short name T185
Test name
Test status
Simulation time 23834071 ps
CPU time 0.65 seconds
Started Jan 10 12:53:12 PM PST 24
Finished Jan 10 12:54:24 PM PST 24
Peak memory 201692 kb
Host smart-e7221f0e-1954-4582-a1e8-ee28aa18345f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269881967 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.sram_ctrl_same_csr_outstanding.269881967
Directory /workspace/18.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.396963784
Short name T179
Test name
Test status
Simulation time 447057800 ps
CPU time 4.43 seconds
Started Jan 10 12:53:21 PM PST 24
Finished Jan 10 12:54:38 PM PST 24
Peak memory 202344 kb
Host smart-4d53e3a8-d515-487c-b429-f01003b1ab2d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396963784 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
18.sram_ctrl_tl_errors.396963784
Directory /workspace/18.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1605608582
Short name T196
Test name
Test status
Simulation time 1413238061 ps
CPU time 6.44 seconds
Started Jan 10 12:53:17 PM PST 24
Finished Jan 10 12:54:37 PM PST 24
Peak memory 210572 kb
Host smart-92519cb2-1aeb-4a6b-9f95-a24e3a5c2a71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605608582 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_mem_rw_with_rand_reset.1605608582
Directory /workspace/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1817278068
Short name T187
Test name
Test status
Simulation time 50702694 ps
CPU time 0.66 seconds
Started Jan 10 12:53:15 PM PST 24
Finished Jan 10 12:54:28 PM PST 24
Peak memory 202072 kb
Host smart-123fc621-2261-486f-823e-31a3d798d5df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817278068 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 19.sram_ctrl_csr_rw.1817278068
Directory /workspace/19.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1874297692
Short name T193
Test name
Test status
Simulation time 15420275757 ps
CPU time 56.39 seconds
Started Jan 10 12:53:15 PM PST 24
Finished Jan 10 12:55:25 PM PST 24
Peak memory 202540 kb
Host smart-2c7e3cda-c6c5-43ff-89e4-802644856c79
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874297692 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 19.sram_ctrl_passthru_mem_tl_intg_err.1874297692
Directory /workspace/19.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2429306282
Short name T60
Test name
Test status
Simulation time 90348022 ps
CPU time 0.77 seconds
Started Jan 10 12:53:19 PM PST 24
Finished Jan 10 12:54:32 PM PST 24
Peak memory 202184 kb
Host smart-e5e3db20-bd27-4e5f-8073-71173a809c4a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429306282 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.sram_ctrl_same_csr_outstanding.2429306282
Directory /workspace/19.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1953578277
Short name T151
Test name
Test status
Simulation time 132264177 ps
CPU time 3.99 seconds
Started Jan 10 12:53:12 PM PST 24
Finished Jan 10 12:54:28 PM PST 24
Peak memory 202436 kb
Host smart-c8b34a96-7969-4297-92ae-f7bd7c680784
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953578277 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 19.sram_ctrl_tl_errors.1953578277
Directory /workspace/19.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2745840567
Short name T106
Test name
Test status
Simulation time 190142182 ps
CPU time 2.38 seconds
Started Jan 10 12:53:13 PM PST 24
Finished Jan 10 12:54:27 PM PST 24
Peak memory 210616 kb
Host smart-ebf94612-be6a-45b0-a21f-386e3ac8a7f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745840567 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 19.sram_ctrl_tl_intg_err.2745840567
Directory /workspace/19.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.908322250
Short name T69
Test name
Test status
Simulation time 20432986 ps
CPU time 0.66 seconds
Started Jan 10 12:52:57 PM PST 24
Finished Jan 10 12:54:11 PM PST 24
Peak memory 201284 kb
Host smart-24000a18-c4d9-42f9-9bc2-2bc713bce92d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908322250 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.sram_ctrl_csr_aliasing.908322250
Directory /workspace/2.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2920631246
Short name T202
Test name
Test status
Simulation time 60086585 ps
CPU time 1.18 seconds
Started Jan 10 12:52:47 PM PST 24
Finished Jan 10 12:54:11 PM PST 24
Peak memory 201836 kb
Host smart-dbeb0d4b-8541-437c-827a-a8efc2f430f6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920631246 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.sram_ctrl_csr_bit_bash.2920631246
Directory /workspace/2.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2967579671
Short name T71
Test name
Test status
Simulation time 42228964 ps
CPU time 0.68 seconds
Started Jan 10 12:52:52 PM PST 24
Finished Jan 10 12:54:05 PM PST 24
Peak memory 201444 kb
Host smart-465c9483-4fb3-49f8-b37f-fe85b18e31a1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967579671 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.sram_ctrl_csr_hw_reset.2967579671
Directory /workspace/2.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3321844236
Short name T186
Test name
Test status
Simulation time 700921122 ps
CPU time 6.01 seconds
Started Jan 10 12:52:48 PM PST 24
Finished Jan 10 12:54:04 PM PST 24
Peak memory 202420 kb
Host smart-2703a61d-fc72-498c-b555-ba411860f937
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321844236 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_mem_rw_with_rand_reset.3321844236
Directory /workspace/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3101703568
Short name T64
Test name
Test status
Simulation time 22642118 ps
CPU time 0.67 seconds
Started Jan 10 12:52:53 PM PST 24
Finished Jan 10 12:54:06 PM PST 24
Peak memory 202040 kb
Host smart-0e3de8a3-72f6-4353-bcdf-ace80aee1237
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101703568 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 2.sram_ctrl_csr_rw.3101703568
Directory /workspace/2.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1920555062
Short name T153
Test name
Test status
Simulation time 23455755746 ps
CPU time 269.83 seconds
Started Jan 10 12:52:48 PM PST 24
Finished Jan 10 12:58:29 PM PST 24
Peak memory 210748 kb
Host smart-087c5792-f54a-497f-8cdf-287ad2e5c82c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920555062 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.sram_ctrl_passthru_mem_tl_intg_err.1920555062
Directory /workspace/2.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.239999513
Short name T201
Test name
Test status
Simulation time 154990545 ps
CPU time 0.72 seconds
Started Jan 10 12:53:00 PM PST 24
Finished Jan 10 12:54:13 PM PST 24
Peak memory 202156 kb
Host smart-4dab20f9-4a19-430b-b537-9f14b6071b7e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239999513 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.sram_ctrl_same_csr_outstanding.239999513
Directory /workspace/2.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3992412907
Short name T197
Test name
Test status
Simulation time 936954100 ps
CPU time 4.7 seconds
Started Jan 10 12:53:09 PM PST 24
Finished Jan 10 12:54:25 PM PST 24
Peak memory 202412 kb
Host smart-6ec1b060-569d-4bf2-82a4-fd4c0ae9eda2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992412907 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 2.sram_ctrl_tl_errors.3992412907
Directory /workspace/2.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1014916296
Short name T58
Test name
Test status
Simulation time 207344247 ps
CPU time 1.96 seconds
Started Jan 10 12:53:00 PM PST 24
Finished Jan 10 12:54:15 PM PST 24
Peak memory 202340 kb
Host smart-1bf22fa2-11bf-47c5-aa01-8fcb9a872016
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014916296 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 2.sram_ctrl_tl_intg_err.1014916296
Directory /workspace/2.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2706427514
Short name T169
Test name
Test status
Simulation time 20537467 ps
CPU time 0.66 seconds
Started Jan 10 12:52:56 PM PST 24
Finished Jan 10 12:54:09 PM PST 24
Peak memory 201348 kb
Host smart-d5b28c88-e717-430a-9abe-a9ed7cae0a50
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706427514 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.sram_ctrl_csr_aliasing.2706427514
Directory /workspace/3.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.48694027
Short name T167
Test name
Test status
Simulation time 86515489 ps
CPU time 1.15 seconds
Started Jan 10 12:53:01 PM PST 24
Finished Jan 10 12:54:13 PM PST 24
Peak memory 202244 kb
Host smart-d987c057-af6e-440d-ad3d-ad99da21da08
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48694027 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.sram_ctrl_csr_bit_bash.48694027
Directory /workspace/3.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2070251772
Short name T137
Test name
Test status
Simulation time 30336274 ps
CPU time 0.67 seconds
Started Jan 10 12:53:02 PM PST 24
Finished Jan 10 12:54:17 PM PST 24
Peak memory 201212 kb
Host smart-57dee6c5-ef85-4a82-9c47-3befa97bf9e6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070251772 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.sram_ctrl_csr_hw_reset.2070251772
Directory /workspace/3.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2092235927
Short name T141
Test name
Test status
Simulation time 353817156 ps
CPU time 5.27 seconds
Started Jan 10 12:53:03 PM PST 24
Finished Jan 10 12:54:20 PM PST 24
Peak memory 202372 kb
Host smart-16666339-ab07-46e3-b987-87cf99c6f0e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092235927 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_mem_rw_with_rand_reset.2092235927
Directory /workspace/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3939612108
Short name T207
Test name
Test status
Simulation time 14845833 ps
CPU time 0.67 seconds
Started Jan 10 12:53:28 PM PST 24
Finished Jan 10 12:54:41 PM PST 24
Peak memory 201472 kb
Host smart-b75e7d70-024e-4917-a7eb-b2e0b2c58ad0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939612108 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 3.sram_ctrl_csr_rw.3939612108
Directory /workspace/3.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1309729383
Short name T86
Test name
Test status
Simulation time 7434112433 ps
CPU time 54.59 seconds
Started Jan 10 12:52:53 PM PST 24
Finished Jan 10 12:54:59 PM PST 24
Peak memory 202564 kb
Host smart-c1b834db-612c-477f-aebf-db4ee0779e6f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309729383 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.sram_ctrl_passthru_mem_tl_intg_err.1309729383
Directory /workspace/3.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3734348929
Short name T192
Test name
Test status
Simulation time 49734197 ps
CPU time 0.68 seconds
Started Jan 10 12:52:58 PM PST 24
Finished Jan 10 12:54:10 PM PST 24
Peak memory 202224 kb
Host smart-3c5c8bc1-10be-440a-a179-2561e1fff101
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734348929 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.sram_ctrl_same_csr_outstanding.3734348929
Directory /workspace/3.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2806347076
Short name T189
Test name
Test status
Simulation time 524909480 ps
CPU time 4.31 seconds
Started Jan 10 12:52:55 PM PST 24
Finished Jan 10 12:54:13 PM PST 24
Peak memory 202452 kb
Host smart-a0a9da55-94a8-447e-91f4-d288d51257aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806347076 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 3.sram_ctrl_tl_errors.2806347076
Directory /workspace/3.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.4191240717
Short name T49
Test name
Test status
Simulation time 683885733 ps
CPU time 2.35 seconds
Started Jan 10 12:53:20 PM PST 24
Finished Jan 10 12:54:34 PM PST 24
Peak memory 202332 kb
Host smart-db738bbc-2991-489a-bbe7-9064cacf21b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191240717 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 3.sram_ctrl_tl_intg_err.4191240717
Directory /workspace/3.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.600589065
Short name T145
Test name
Test status
Simulation time 33825948 ps
CPU time 0.73 seconds
Started Jan 10 12:53:03 PM PST 24
Finished Jan 10 12:54:20 PM PST 24
Peak memory 201168 kb
Host smart-29401df1-b43b-4b77-9f6b-51bbfef35967
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600589065 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.sram_ctrl_csr_aliasing.600589065
Directory /workspace/4.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1859504709
Short name T136
Test name
Test status
Simulation time 139930952 ps
CPU time 1.54 seconds
Started Jan 10 12:53:01 PM PST 24
Finished Jan 10 12:54:13 PM PST 24
Peak memory 202408 kb
Host smart-48a93109-b869-4a15-9f93-07ec7cb35694
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859504709 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.sram_ctrl_csr_bit_bash.1859504709
Directory /workspace/4.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3546405600
Short name T184
Test name
Test status
Simulation time 43946556 ps
CPU time 0.64 seconds
Started Jan 10 12:53:07 PM PST 24
Finished Jan 10 12:54:19 PM PST 24
Peak memory 201444 kb
Host smart-685adaa0-5cf8-4709-9156-bb42497bf956
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546405600 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.sram_ctrl_csr_hw_reset.3546405600
Directory /workspace/4.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1251351703
Short name T165
Test name
Test status
Simulation time 343433038 ps
CPU time 12.05 seconds
Started Jan 10 12:52:55 PM PST 24
Finished Jan 10 12:54:20 PM PST 24
Peak memory 202460 kb
Host smart-25d46842-b506-4dfe-9b6c-54767d996a74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251351703 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_mem_rw_with_rand_reset.1251351703
Directory /workspace/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2897190050
Short name T164
Test name
Test status
Simulation time 39008128 ps
CPU time 0.62 seconds
Started Jan 10 12:55:07 PM PST 24
Finished Jan 10 12:56:12 PM PST 24
Peak memory 201788 kb
Host smart-808d2fcd-fc73-40bf-ad4b-fa491d874170
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897190050 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 4.sram_ctrl_csr_rw.2897190050
Directory /workspace/4.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3653457897
Short name T131
Test name
Test status
Simulation time 7344954458 ps
CPU time 120.23 seconds
Started Jan 10 12:53:06 PM PST 24
Finished Jan 10 12:56:18 PM PST 24
Peak memory 210708 kb
Host smart-9ef47e26-7390-4368-959a-bd70e36fa6eb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653457897 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.sram_ctrl_passthru_mem_tl_intg_err.3653457897
Directory /workspace/4.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2283161666
Short name T183
Test name
Test status
Simulation time 64743506 ps
CPU time 0.69 seconds
Started Jan 10 12:53:03 PM PST 24
Finished Jan 10 12:54:15 PM PST 24
Peak memory 202192 kb
Host smart-59041e67-9519-46d5-a81b-ad7bc6f5a847
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283161666 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.sram_ctrl_same_csr_outstanding.2283161666
Directory /workspace/4.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2088186050
Short name T48
Test name
Test status
Simulation time 127328313 ps
CPU time 3.94 seconds
Started Jan 10 12:53:05 PM PST 24
Finished Jan 10 12:54:23 PM PST 24
Peak memory 202444 kb
Host smart-a62d1e34-dc53-4ed6-9f1b-9333c421b543
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088186050 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 4.sram_ctrl_tl_errors.2088186050
Directory /workspace/4.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1827794229
Short name T174
Test name
Test status
Simulation time 362015140 ps
CPU time 5.95 seconds
Started Jan 10 12:53:00 PM PST 24
Finished Jan 10 12:54:17 PM PST 24
Peak memory 210668 kb
Host smart-8ed8a632-2cc7-483b-aac7-35f95d4a55c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827794229 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_mem_rw_with_rand_reset.1827794229
Directory /workspace/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.4122516734
Short name T195
Test name
Test status
Simulation time 48705393 ps
CPU time 0.61 seconds
Started Jan 10 12:53:02 PM PST 24
Finished Jan 10 12:54:17 PM PST 24
Peak memory 201412 kb
Host smart-acc7bb9d-65d9-49b3-89d4-0dac0c3a39ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122516734 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 5.sram_ctrl_csr_rw.4122516734
Directory /workspace/5.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3619350498
Short name T76
Test name
Test status
Simulation time 14189425883 ps
CPU time 139.39 seconds
Started Jan 10 12:52:52 PM PST 24
Finished Jan 10 12:56:33 PM PST 24
Peak memory 202424 kb
Host smart-ca1e9617-3d92-4a3a-a053-04e487275c5f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619350498 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.sram_ctrl_passthru_mem_tl_intg_err.3619350498
Directory /workspace/5.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.102386089
Short name T190
Test name
Test status
Simulation time 48964855 ps
CPU time 0.73 seconds
Started Jan 10 12:55:07 PM PST 24
Finished Jan 10 12:56:13 PM PST 24
Peak memory 201880 kb
Host smart-ce7380d4-1c22-4729-b6a2-faf255f7797f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102386089 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.sram_ctrl_same_csr_outstanding.102386089
Directory /workspace/5.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.309874752
Short name T52
Test name
Test status
Simulation time 369708272 ps
CPU time 3.78 seconds
Started Jan 10 12:52:52 PM PST 24
Finished Jan 10 12:54:07 PM PST 24
Peak memory 202444 kb
Host smart-b34f7dd5-b162-473d-a1c0-3cbcb219d7d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309874752 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
5.sram_ctrl_tl_errors.309874752
Directory /workspace/5.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3933895914
Short name T107
Test name
Test status
Simulation time 411511712 ps
CPU time 1.7 seconds
Started Jan 10 12:52:58 PM PST 24
Finished Jan 10 12:54:13 PM PST 24
Peak memory 202472 kb
Host smart-510c614b-1781-484f-ad64-9241eb2a7cf8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933895914 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 5.sram_ctrl_tl_intg_err.3933895914
Directory /workspace/5.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.561866643
Short name T198
Test name
Test status
Simulation time 1380864458 ps
CPU time 5.79 seconds
Started Jan 10 12:53:02 PM PST 24
Finished Jan 10 12:54:19 PM PST 24
Peak memory 210632 kb
Host smart-af2dab38-a34d-47bc-b522-a213d617a711
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561866643 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_mem_rw_with_rand_reset.561866643
Directory /workspace/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3031525540
Short name T63
Test name
Test status
Simulation time 19421471 ps
CPU time 0.61 seconds
Started Jan 10 12:53:02 PM PST 24
Finished Jan 10 12:54:14 PM PST 24
Peak memory 201540 kb
Host smart-006e5f93-5acf-4ab8-9ada-11e659289c48
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031525540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 6.sram_ctrl_csr_rw.3031525540
Directory /workspace/6.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.95646282
Short name T88
Test name
Test status
Simulation time 16046163337 ps
CPU time 256.63 seconds
Started Jan 10 12:52:58 PM PST 24
Finished Jan 10 12:58:26 PM PST 24
Peak memory 210620 kb
Host smart-ff76d4d4-8bbc-4a60-95c0-0c3cc02e09a1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95646282 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base
_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.sram_ctrl_passthru_mem_tl_intg_err.95646282
Directory /workspace/6.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.798438619
Short name T150
Test name
Test status
Simulation time 55897967 ps
CPU time 0.74 seconds
Started Jan 10 12:52:52 PM PST 24
Finished Jan 10 12:54:04 PM PST 24
Peak memory 201824 kb
Host smart-02518821-f483-4b3b-84e7-85b59447ed57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798438619 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.sram_ctrl_same_csr_outstanding.798438619
Directory /workspace/6.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1757529101
Short name T191
Test name
Test status
Simulation time 122616471 ps
CPU time 2.89 seconds
Started Jan 10 12:52:56 PM PST 24
Finished Jan 10 12:54:11 PM PST 24
Peak memory 202396 kb
Host smart-39c9de2f-b303-42e9-b830-d3aea43caa03
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757529101 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 6.sram_ctrl_tl_errors.1757529101
Directory /workspace/6.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1837676465
Short name T206
Test name
Test status
Simulation time 145862104 ps
CPU time 1.31 seconds
Started Jan 10 12:52:59 PM PST 24
Finished Jan 10 12:54:15 PM PST 24
Peak memory 202364 kb
Host smart-a3680ca4-87b4-4e79-9a33-683007d16344
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837676465 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 6.sram_ctrl_tl_intg_err.1837676465
Directory /workspace/6.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.452429647
Short name T44
Test name
Test status
Simulation time 1656809965 ps
CPU time 5.11 seconds
Started Jan 10 12:52:52 PM PST 24
Finished Jan 10 12:54:10 PM PST 24
Peak memory 210712 kb
Host smart-748765be-430c-42d4-bf14-07f71bbe3711
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452429647 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_mem_rw_with_rand_reset.452429647
Directory /workspace/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2213962681
Short name T83
Test name
Test status
Simulation time 24427572 ps
CPU time 0.62 seconds
Started Jan 10 12:53:02 PM PST 24
Finished Jan 10 12:54:14 PM PST 24
Peak memory 202128 kb
Host smart-cfe86cd6-f09e-44b5-9110-b5b143f6328b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213962681 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 7.sram_ctrl_csr_rw.2213962681
Directory /workspace/7.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1982181809
Short name T146
Test name
Test status
Simulation time 58134555 ps
CPU time 0.7 seconds
Started Jan 10 12:52:58 PM PST 24
Finished Jan 10 12:54:12 PM PST 24
Peak memory 201980 kb
Host smart-272e453b-4297-4061-a869-8c2fb8cceec9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982181809 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.sram_ctrl_same_csr_outstanding.1982181809
Directory /workspace/7.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.264530896
Short name T170
Test name
Test status
Simulation time 198367220 ps
CPU time 1.93 seconds
Started Jan 10 12:53:03 PM PST 24
Finished Jan 10 12:54:21 PM PST 24
Peak memory 202372 kb
Host smart-45ec3b02-a74e-4e76-9db4-8f7643473084
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264530896 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
7.sram_ctrl_tl_errors.264530896
Directory /workspace/7.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3132828699
Short name T59
Test name
Test status
Simulation time 204872145 ps
CPU time 2.36 seconds
Started Jan 10 12:53:03 PM PST 24
Finished Jan 10 12:54:17 PM PST 24
Peak memory 202396 kb
Host smart-8a329749-e3b3-4157-8881-488f15856de4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132828699 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 7.sram_ctrl_tl_intg_err.3132828699
Directory /workspace/7.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3891889676
Short name T134
Test name
Test status
Simulation time 1453976066 ps
CPU time 5.9 seconds
Started Jan 10 12:52:53 PM PST 24
Finished Jan 10 12:54:12 PM PST 24
Peak memory 210672 kb
Host smart-a2406d11-28a9-44bc-baae-48885fabae71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891889676 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_mem_rw_with_rand_reset.3891889676
Directory /workspace/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.4005428090
Short name T160
Test name
Test status
Simulation time 19497896 ps
CPU time 0.7 seconds
Started Jan 10 12:52:58 PM PST 24
Finished Jan 10 12:54:10 PM PST 24
Peak memory 201436 kb
Host smart-c10a5223-b870-495f-a63c-a7b787de4cd6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005428090 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 8.sram_ctrl_csr_rw.4005428090
Directory /workspace/8.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1939069878
Short name T89
Test name
Test status
Simulation time 3859899125 ps
CPU time 139.25 seconds
Started Jan 10 12:55:06 PM PST 24
Finished Jan 10 12:58:31 PM PST 24
Peak memory 202276 kb
Host smart-a86924fe-4cf1-4ee0-ab34-406d7035150d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939069878 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.sram_ctrl_passthru_mem_tl_intg_err.1939069878
Directory /workspace/8.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3380607278
Short name T92
Test name
Test status
Simulation time 151977776 ps
CPU time 0.73 seconds
Started Jan 10 12:54:49 PM PST 24
Finished Jan 10 12:55:56 PM PST 24
Peak memory 200312 kb
Host smart-e1899baf-41bf-453c-a88e-beb6f78b6008
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380607278 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.sram_ctrl_same_csr_outstanding.3380607278
Directory /workspace/8.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.4291624707
Short name T194
Test name
Test status
Simulation time 33477819 ps
CPU time 2.66 seconds
Started Jan 10 12:55:05 PM PST 24
Finished Jan 10 12:56:13 PM PST 24
Peak memory 202036 kb
Host smart-f5f71fc6-bc30-4e7b-8db6-8062abec955a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291624707 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 8.sram_ctrl_tl_errors.4291624707
Directory /workspace/8.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1929386047
Short name T50
Test name
Test status
Simulation time 112030254 ps
CPU time 1.3 seconds
Started Jan 10 12:55:07 PM PST 24
Finished Jan 10 12:56:13 PM PST 24
Peak memory 202048 kb
Host smart-173b5cfd-1497-4ec1-b73b-27c1fea9a0be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929386047 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 8.sram_ctrl_tl_intg_err.1929386047
Directory /workspace/8.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1796600265
Short name T143
Test name
Test status
Simulation time 373994695 ps
CPU time 12.9 seconds
Started Jan 10 12:53:00 PM PST 24
Finished Jan 10 12:54:25 PM PST 24
Peak memory 210660 kb
Host smart-c03f457f-82e3-4900-8181-65860d4e9b31
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796600265 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_mem_rw_with_rand_reset.1796600265
Directory /workspace/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.716967779
Short name T62
Test name
Test status
Simulation time 12402660 ps
CPU time 0.65 seconds
Started Jan 10 12:53:07 PM PST 24
Finished Jan 10 12:54:19 PM PST 24
Peak memory 202052 kb
Host smart-3fe5e023-389c-4088-8ff3-c32043af1af5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716967779 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 9.sram_ctrl_csr_rw.716967779
Directory /workspace/9.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1501849516
Short name T87
Test name
Test status
Simulation time 7142653188 ps
CPU time 259.95 seconds
Started Jan 10 12:53:12 PM PST 24
Finished Jan 10 12:58:44 PM PST 24
Peak memory 210652 kb
Host smart-d6bf95c2-3bef-4362-b50f-fb17955c10c7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501849516 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.sram_ctrl_passthru_mem_tl_intg_err.1501849516
Directory /workspace/9.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2729221960
Short name T157
Test name
Test status
Simulation time 31275718 ps
CPU time 0.68 seconds
Started Jan 10 12:55:06 PM PST 24
Finished Jan 10 12:56:12 PM PST 24
Peak memory 201844 kb
Host smart-9ce7388b-e77e-49a8-beb8-47eef003032c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729221960 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.sram_ctrl_same_csr_outstanding.2729221960
Directory /workspace/9.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.952584272
Short name T139
Test name
Test status
Simulation time 615724627 ps
CPU time 4.49 seconds
Started Jan 10 12:53:00 PM PST 24
Finished Jan 10 12:54:17 PM PST 24
Peak memory 210620 kb
Host smart-2f357c60-ee24-4be1-9eb9-2ef90fe594dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952584272 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
9.sram_ctrl_tl_errors.952584272
Directory /workspace/9.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.180369205
Short name T103
Test name
Test status
Simulation time 432822837 ps
CPU time 2.73 seconds
Started Jan 10 12:52:59 PM PST 24
Finished Jan 10 12:54:19 PM PST 24
Peak memory 202284 kb
Host smart-5ec53304-6ff0-4f97-9c98-3cd6e08a0326
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180369205 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 9.sram_ctrl_tl_intg_err.180369205
Directory /workspace/9.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.sram_ctrl_access_during_key_req.1115673068
Short name T945
Test name
Test status
Simulation time 24964278806 ps
CPU time 828.57 seconds
Started Jan 10 01:26:11 PM PST 24
Finished Jan 10 01:40:25 PM PST 24
Peak memory 379008 kb
Host smart-43ebec69-6d84-4925-bdaf-370ba520c262
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115673068 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.sram_ctrl_access_during_key_req.1115673068
Directory /workspace/0.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/0.sram_ctrl_alert_test.1910251717
Short name T361
Test name
Test status
Simulation time 53638268 ps
CPU time 0.63 seconds
Started Jan 10 01:26:10 PM PST 24
Finished Jan 10 01:26:33 PM PST 24
Peak memory 201936 kb
Host smart-3d5c0f00-5826-459a-b85b-e882166f340d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910251717 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.sram_ctrl_alert_test.1910251717
Directory /workspace/0.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.sram_ctrl_bijection.1961308298
Short name T292
Test name
Test status
Simulation time 83890025764 ps
CPU time 1676.75 seconds
Started Jan 10 01:26:02 PM PST 24
Finished Jan 10 01:54:15 PM PST 24
Peak memory 202148 kb
Host smart-8193e89a-4820-47bb-a939-7b7c504cec53
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961308298 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection.
1961308298
Directory /workspace/0.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/0.sram_ctrl_executable.2234963229
Short name T449
Test name
Test status
Simulation time 46875525505 ps
CPU time 718.59 seconds
Started Jan 10 01:26:12 PM PST 24
Finished Jan 10 01:38:32 PM PST 24
Peak memory 372748 kb
Host smart-ec6f8bff-bfac-4be8-abd9-94060ad43fb8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234963229 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_executabl
e.2234963229
Directory /workspace/0.sram_ctrl_executable/latest

Test location /workspace/coverage/default/0.sram_ctrl_lc_escalation.3327245034
Short name T573
Test name
Test status
Simulation time 47120258561 ps
CPU time 133.86 seconds
Started Jan 10 01:26:04 PM PST 24
Finished Jan 10 01:28:35 PM PST 24
Peak memory 210400 kb
Host smart-069f7e20-4125-4e15-8351-2ceed1a4b217
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327245034 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_lc_esc
alation.3327245034
Directory /workspace/0.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/0.sram_ctrl_max_throughput.933528442
Short name T635
Test name
Test status
Simulation time 762789455 ps
CPU time 118.2 seconds
Started Jan 10 01:26:08 PM PST 24
Finished Jan 10 01:28:29 PM PST 24
Peak memory 354512 kb
Host smart-613d700e-57f9-4e06-b0f6-278b58dbf807
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933528442 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.sram_ctrl_max_throughput.933528442
Directory /workspace/0.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/0.sram_ctrl_mem_partial_access.893657463
Short name T266
Test name
Test status
Simulation time 70947783471 ps
CPU time 153.51 seconds
Started Jan 10 01:26:16 PM PST 24
Finished Jan 10 01:29:10 PM PST 24
Peak memory 211544 kb
Host smart-e920cd2e-9e52-40de-b226-352908feef77
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893657463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
sram_ctrl_mem_partial_access.893657463
Directory /workspace/0.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/0.sram_ctrl_mem_walk.1140753870
Short name T805
Test name
Test status
Simulation time 8240944213 ps
CPU time 121.38 seconds
Started Jan 10 01:26:01 PM PST 24
Finished Jan 10 01:28:18 PM PST 24
Peak memory 202120 kb
Host smart-10577245-80d5-4cc1-9b75-dde1250876d3
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140753870 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl
_mem_walk.1140753870
Directory /workspace/0.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/0.sram_ctrl_multiple_keys.3705088888
Short name T494
Test name
Test status
Simulation time 21388182157 ps
CPU time 960.22 seconds
Started Jan 10 01:26:05 PM PST 24
Finished Jan 10 01:42:31 PM PST 24
Peak memory 379044 kb
Host smart-77e5010c-1e8c-4c77-83a6-08a83f1df7af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705088888 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multip
le_keys.3705088888
Directory /workspace/0.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/0.sram_ctrl_partial_access.995158464
Short name T396
Test name
Test status
Simulation time 743389963 ps
CPU time 12.32 seconds
Started Jan 10 01:26:07 PM PST 24
Finished Jan 10 01:26:41 PM PST 24
Peak memory 202092 kb
Host smart-6c3e5870-8192-4111-902e-59ccb5f5e158
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995158464 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sr
am_ctrl_partial_access.995158464
Directory /workspace/0.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.1366977208
Short name T513
Test name
Test status
Simulation time 33283765109 ps
CPU time 395.56 seconds
Started Jan 10 01:26:10 PM PST 24
Finished Jan 10 01:33:08 PM PST 24
Peak memory 202160 kb
Host smart-51275311-8c1e-4fb7-9dc7-85b7785c5506
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366977208 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 0.sram_ctrl_partial_access_b2b.1366977208
Directory /workspace/0.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/0.sram_ctrl_ram_cfg.1947142995
Short name T576
Test name
Test status
Simulation time 1411688376 ps
CPU time 7.04 seconds
Started Jan 10 01:26:00 PM PST 24
Finished Jan 10 01:26:23 PM PST 24
Peak memory 202432 kb
Host smart-ad457e2e-3880-4533-84ed-514f3116b7e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947142995 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.1947142995
Directory /workspace/0.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/0.sram_ctrl_regwen.3745731517
Short name T271
Test name
Test status
Simulation time 2001465969 ps
CPU time 746.97 seconds
Started Jan 10 01:26:09 PM PST 24
Finished Jan 10 01:38:58 PM PST 24
Peak memory 376904 kb
Host smart-87718b3d-a21e-45cd-a4b6-5cd4517e7dcb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745731517 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.3745731517
Directory /workspace/0.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/0.sram_ctrl_sec_cm.3258514296
Short name T34
Test name
Test status
Simulation time 541498706 ps
CPU time 4.03 seconds
Started Jan 10 01:26:12 PM PST 24
Finished Jan 10 01:26:38 PM PST 24
Peak memory 220860 kb
Host smart-f39a7d6d-e191-4eaf-8ed1-5ab66eae5996
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258514296 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.sram_ctrl_sec_cm.3258514296
Directory /workspace/0.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.sram_ctrl_smoke.3626634795
Short name T556
Test name
Test status
Simulation time 4236916625 ps
CPU time 19.43 seconds
Started Jan 10 01:26:05 PM PST 24
Finished Jan 10 01:26:43 PM PST 24
Peak memory 202136 kb
Host smart-fcb1a315-95ad-4425-9f50-34affb6143a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626634795 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.3626634795
Directory /workspace/0.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/0.sram_ctrl_stress_all.1874975963
Short name T891
Test name
Test status
Simulation time 20615358278 ps
CPU time 879.7 seconds
Started Jan 10 01:26:14 PM PST 24
Finished Jan 10 01:41:15 PM PST 24
Peak memory 386304 kb
Host smart-53e1d4d7-036f-4cf2-8323-01c895f97aa0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874975963 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 0.sram_ctrl_stress_all.1874975963
Directory /workspace/0.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1305413258
Short name T471
Test name
Test status
Simulation time 4231653741 ps
CPU time 4921.81 seconds
Started Jan 10 01:26:04 PM PST 24
Finished Jan 10 02:48:32 PM PST 24
Peak memory 557684 kb
Host smart-f143b444-2a49-4b1b-a792-2d48e3c9bf9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1305413258 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all_with_rand_reset.1305413258
Directory /workspace/0.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.sram_ctrl_stress_pipeline.2582416616
Short name T798
Test name
Test status
Simulation time 4705781198 ps
CPU time 137.95 seconds
Started Jan 10 01:26:07 PM PST 24
Finished Jan 10 01:28:47 PM PST 24
Peak memory 202180 kb
Host smart-aa3ae5fe-dc61-47ba-84e7-8c62feb3fed9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582416616 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.sram_ctrl_stress_pipeline.2582416616
Directory /workspace/0.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.3544535857
Short name T610
Test name
Test status
Simulation time 1617287061 ps
CPU time 85 seconds
Started Jan 10 01:26:07 PM PST 24
Finished Jan 10 01:27:53 PM PST 24
Peak memory 334984 kb
Host smart-b930de72-74df-4c88-b068-d8384d7722c9
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544535857 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.sram_ctrl_throughput_w_partial_write.3544535857
Directory /workspace/0.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/1.sram_ctrl_access_during_key_req.285916875
Short name T563
Test name
Test status
Simulation time 2242362473 ps
CPU time 262.22 seconds
Started Jan 10 01:26:05 PM PST 24
Finished Jan 10 01:30:45 PM PST 24
Peak memory 373836 kb
Host smart-26a97d8b-8c3b-474b-9fe6-26b74c36519d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285916875 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 1.sram_ctrl_access_during_key_req.285916875
Directory /workspace/1.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/1.sram_ctrl_alert_test.2177624103
Short name T941
Test name
Test status
Simulation time 13343296 ps
CPU time 0.63 seconds
Started Jan 10 01:25:59 PM PST 24
Finished Jan 10 01:26:15 PM PST 24
Peak memory 201460 kb
Host smart-fbfa40bf-13a3-4681-b695-13d97c273b71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177624103 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.sram_ctrl_alert_test.2177624103
Directory /workspace/1.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.sram_ctrl_bijection.1899549816
Short name T826
Test name
Test status
Simulation time 59023341328 ps
CPU time 1038.64 seconds
Started Jan 10 01:26:05 PM PST 24
Finished Jan 10 01:43:43 PM PST 24
Peak memory 202160 kb
Host smart-f93d355e-0262-4132-88d9-6af1489208e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899549816 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection.
1899549816
Directory /workspace/1.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/1.sram_ctrl_lc_escalation.1757750115
Short name T924
Test name
Test status
Simulation time 20382866966 ps
CPU time 43.72 seconds
Started Jan 10 01:26:04 PM PST 24
Finished Jan 10 01:27:05 PM PST 24
Peak memory 210368 kb
Host smart-a15c3747-3571-4933-a26e-f23616723bdb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757750115 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_lc_esc
alation.1757750115
Directory /workspace/1.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/1.sram_ctrl_max_throughput.2050092425
Short name T350
Test name
Test status
Simulation time 4336727200 ps
CPU time 77.14 seconds
Started Jan 10 01:26:14 PM PST 24
Finished Jan 10 01:27:53 PM PST 24
Peak memory 325980 kb
Host smart-f1ff1b45-eb77-4206-9d62-0fe55832b394
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050092425 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.sram_ctrl_max_throughput.2050092425
Directory /workspace/1.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/1.sram_ctrl_mem_partial_access.2681133792
Short name T758
Test name
Test status
Simulation time 31264334364 ps
CPU time 136.09 seconds
Started Jan 10 01:25:56 PM PST 24
Finished Jan 10 01:28:27 PM PST 24
Peak memory 211440 kb
Host smart-620da97b-fd59-48ba-a713-26671dfe90ba
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681133792 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.sram_ctrl_mem_partial_access.2681133792
Directory /workspace/1.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/1.sram_ctrl_mem_walk.4071614964
Short name T430
Test name
Test status
Simulation time 55216474937 ps
CPU time 272.4 seconds
Started Jan 10 01:26:04 PM PST 24
Finished Jan 10 01:30:54 PM PST 24
Peak memory 202168 kb
Host smart-d4b60f5c-07f5-4e72-8aab-7e470c06ae80
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071614964 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl
_mem_walk.4071614964
Directory /workspace/1.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/1.sram_ctrl_multiple_keys.2760555033
Short name T121
Test name
Test status
Simulation time 45053911235 ps
CPU time 703.88 seconds
Started Jan 10 01:26:10 PM PST 24
Finished Jan 10 01:38:16 PM PST 24
Peak memory 379244 kb
Host smart-e2f180d6-1e32-4fb9-b19a-a0229be2abea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760555033 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multip
le_keys.2760555033
Directory /workspace/1.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/1.sram_ctrl_partial_access.723539540
Short name T338
Test name
Test status
Simulation time 792828544 ps
CPU time 67.14 seconds
Started Jan 10 01:26:04 PM PST 24
Finished Jan 10 01:27:28 PM PST 24
Peak memory 307356 kb
Host smart-50b440a2-a63b-4386-a0ac-e57b396d2db7
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723539540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sr
am_ctrl_partial_access.723539540
Directory /workspace/1.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/1.sram_ctrl_ram_cfg.1365599305
Short name T630
Test name
Test status
Simulation time 709790426 ps
CPU time 14.32 seconds
Started Jan 10 01:26:09 PM PST 24
Finished Jan 10 01:26:47 PM PST 24
Peak memory 202384 kb
Host smart-6fd70a9b-9a82-42bf-b77f-f911aa562456
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365599305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.1365599305
Directory /workspace/1.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/1.sram_ctrl_smoke.732700841
Short name T867
Test name
Test status
Simulation time 5054565925 ps
CPU time 82.87 seconds
Started Jan 10 01:26:15 PM PST 24
Finished Jan 10 01:27:59 PM PST 24
Peak memory 336264 kb
Host smart-2e80c099-73e4-42b0-9f13-6e4a34f0da94
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732700841 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.732700841
Directory /workspace/1.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/1.sram_ctrl_stress_all.871359900
Short name T729
Test name
Test status
Simulation time 122304290581 ps
CPU time 2192.02 seconds
Started Jan 10 01:26:05 PM PST 24
Finished Jan 10 02:02:57 PM PST 24
Peak memory 384168 kb
Host smart-84965a37-8cdf-4e52-b775-3b88a3b367db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871359900 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 1.sram_ctrl_stress_all.871359900
Directory /workspace/1.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.1203610046
Short name T868
Test name
Test status
Simulation time 186944678 ps
CPU time 920.17 seconds
Started Jan 10 01:25:53 PM PST 24
Finished Jan 10 01:41:28 PM PST 24
Peak memory 433404 kb
Host smart-081c21c7-b155-43c4-bf07-47d6af47887a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1203610046 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all_with_rand_reset.1203610046
Directory /workspace/1.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.sram_ctrl_stress_pipeline.1496484395
Short name T91
Test name
Test status
Simulation time 19869273967 ps
CPU time 363.56 seconds
Started Jan 10 01:26:07 PM PST 24
Finished Jan 10 01:32:33 PM PST 24
Peak memory 202088 kb
Host smart-259a430c-a859-4493-8e6e-7c5310b59372
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496484395 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.sram_ctrl_stress_pipeline.1496484395
Directory /workspace/1.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.94854546
Short name T291
Test name
Test status
Simulation time 1146826537 ps
CPU time 168.07 seconds
Started Jan 10 01:26:12 PM PST 24
Finished Jan 10 01:29:22 PM PST 24
Peak memory 357500 kb
Host smart-5232d3a7-3391-47bc-bc46-e665bc3e6c9d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94854546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.sram_ctrl_throughput_w_partial_write.94854546
Directory /workspace/1.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/10.sram_ctrl_access_during_key_req.2997676520
Short name T814
Test name
Test status
Simulation time 7675245037 ps
CPU time 554.29 seconds
Started Jan 10 01:26:33 PM PST 24
Finished Jan 10 01:36:01 PM PST 24
Peak memory 375000 kb
Host smart-a8ae2949-9936-47a7-9d4f-cdac78121831
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997676520 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 10.sram_ctrl_access_during_key_req.2997676520
Directory /workspace/10.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/10.sram_ctrl_alert_test.4287563937
Short name T682
Test name
Test status
Simulation time 42686641 ps
CPU time 0.63 seconds
Started Jan 10 01:26:33 PM PST 24
Finished Jan 10 01:26:46 PM PST 24
Peak memory 201448 kb
Host smart-5b02048c-fd87-428a-874c-970643f6413c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287563937 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.sram_ctrl_alert_test.4287563937
Directory /workspace/10.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.sram_ctrl_bijection.3334947561
Short name T337
Test name
Test status
Simulation time 159893534238 ps
CPU time 1830.17 seconds
Started Jan 10 01:26:34 PM PST 24
Finished Jan 10 01:57:18 PM PST 24
Peak memory 202124 kb
Host smart-b46c5641-a7ae-4405-80b3-8152c8ed088a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334947561 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection
.3334947561
Directory /workspace/10.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/10.sram_ctrl_executable.153363878
Short name T702
Test name
Test status
Simulation time 4826080170 ps
CPU time 225.03 seconds
Started Jan 10 01:26:35 PM PST 24
Finished Jan 10 01:30:35 PM PST 24
Peak memory 370872 kb
Host smart-e7ce3e28-76e1-42db-968a-b1df4d798d21
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153363878 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executabl
e.153363878
Directory /workspace/10.sram_ctrl_executable/latest

Test location /workspace/coverage/default/10.sram_ctrl_max_throughput.1073217547
Short name T921
Test name
Test status
Simulation time 779805175 ps
CPU time 107.35 seconds
Started Jan 10 01:26:29 PM PST 24
Finished Jan 10 01:28:29 PM PST 24
Peak memory 340172 kb
Host smart-9c9b9c95-ec97-4a40-8349-1bc914e5c4e8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073217547 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 10.sram_ctrl_max_throughput.1073217547
Directory /workspace/10.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/10.sram_ctrl_mem_partial_access.2356613420
Short name T80
Test name
Test status
Simulation time 1987390657 ps
CPU time 74.11 seconds
Started Jan 10 01:26:42 PM PST 24
Finished Jan 10 01:28:11 PM PST 24
Peak memory 210800 kb
Host smart-07210000-3cbc-477b-85ad-4502dd8d7e92
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356613420 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.sram_ctrl_mem_partial_access.2356613420
Directory /workspace/10.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/10.sram_ctrl_mem_walk.3245833286
Short name T659
Test name
Test status
Simulation time 93791576386 ps
CPU time 315.93 seconds
Started Jan 10 01:26:45 PM PST 24
Finished Jan 10 01:32:15 PM PST 24
Peak memory 202184 kb
Host smart-d47ab0dd-966e-40f5-aa92-c728ddf2205e
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245833286 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctr
l_mem_walk.3245833286
Directory /workspace/10.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/10.sram_ctrl_multiple_keys.1369286121
Short name T760
Test name
Test status
Simulation time 4215467199 ps
CPU time 368.19 seconds
Started Jan 10 01:26:30 PM PST 24
Finished Jan 10 01:32:51 PM PST 24
Peak memory 365904 kb
Host smart-6b910d8c-1080-4edc-9a21-2456c28945f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369286121 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multi
ple_keys.1369286121
Directory /workspace/10.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/10.sram_ctrl_partial_access.1775282230
Short name T819
Test name
Test status
Simulation time 811340999 ps
CPU time 51.71 seconds
Started Jan 10 01:26:25 PM PST 24
Finished Jan 10 01:27:32 PM PST 24
Peak memory 319592 kb
Host smart-c9610634-98ce-4a9f-a39f-1c20977223da
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775282230 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
sram_ctrl_partial_access.1775282230
Directory /workspace/10.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.1333285430
Short name T822
Test name
Test status
Simulation time 168054987640 ps
CPU time 491.75 seconds
Started Jan 10 01:26:31 PM PST 24
Finished Jan 10 01:34:55 PM PST 24
Peak memory 202176 kb
Host smart-90bbb5ac-ded0-43b5-a5a9-f1c12fb20864
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333285430 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 10.sram_ctrl_partial_access_b2b.1333285430
Directory /workspace/10.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/10.sram_ctrl_ram_cfg.647103853
Short name T431
Test name
Test status
Simulation time 664311749 ps
CPU time 5.67 seconds
Started Jan 10 01:26:45 PM PST 24
Finished Jan 10 01:27:05 PM PST 24
Peak memory 202400 kb
Host smart-53991d8d-dbe5-4818-b9e8-d0b8efc46d3c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647103853 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.647103853
Directory /workspace/10.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/10.sram_ctrl_regwen.217249235
Short name T407
Test name
Test status
Simulation time 8035487082 ps
CPU time 161.25 seconds
Started Jan 10 01:26:35 PM PST 24
Finished Jan 10 01:29:31 PM PST 24
Peak memory 363568 kb
Host smart-fc9e1fd7-c1c0-4deb-b928-faf4ce1e5cc8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217249235 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.217249235
Directory /workspace/10.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/10.sram_ctrl_smoke.2491698497
Short name T878
Test name
Test status
Simulation time 11270627014 ps
CPU time 147.11 seconds
Started Jan 10 01:26:30 PM PST 24
Finished Jan 10 01:29:10 PM PST 24
Peak memory 369028 kb
Host smart-8d8e2f5a-5bfd-482c-8db7-4c9c5d628a62
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491698497 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.2491698497
Directory /workspace/10.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/10.sram_ctrl_stress_all.2184420098
Short name T643
Test name
Test status
Simulation time 105468549686 ps
CPU time 5218.14 seconds
Started Jan 10 01:26:31 PM PST 24
Finished Jan 10 02:53:42 PM PST 24
Peak memory 385196 kb
Host smart-6ca6f6e6-cf61-4584-aff1-6550c5ab52b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184420098 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 10.sram_ctrl_stress_all.2184420098
Directory /workspace/10.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3438380449
Short name T498
Test name
Test status
Simulation time 730840301 ps
CPU time 5422.04 seconds
Started Jan 10 01:26:34 PM PST 24
Finished Jan 10 02:57:12 PM PST 24
Peak memory 778248 kb
Host smart-e73667da-3b86-4a28-99fe-0d2efd91cd12
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3438380449 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all_with_rand_reset.3438380449
Directory /workspace/10.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.sram_ctrl_stress_pipeline.2485774168
Short name T507
Test name
Test status
Simulation time 6398811123 ps
CPU time 225.66 seconds
Started Jan 10 01:26:45 PM PST 24
Finished Jan 10 01:30:45 PM PST 24
Peak memory 202356 kb
Host smart-f11802c8-6f37-4f5f-ac29-ee7498caeac5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485774168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.sram_ctrl_stress_pipeline.2485774168
Directory /workspace/10.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.210994100
Short name T249
Test name
Test status
Simulation time 1514508259 ps
CPU time 71.83 seconds
Started Jan 10 01:26:29 PM PST 24
Finished Jan 10 01:27:54 PM PST 24
Peak memory 308168 kb
Host smart-a5c66284-eed6-41fb-91fa-e2df146fcb69
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210994100 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 10.sram_ctrl_throughput_w_partial_write.210994100
Directory /workspace/10.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/11.sram_ctrl_access_during_key_req.453291746
Short name T402
Test name
Test status
Simulation time 18023288464 ps
CPU time 1167.56 seconds
Started Jan 10 01:26:47 PM PST 24
Finished Jan 10 01:46:28 PM PST 24
Peak memory 380124 kb
Host smart-edd5bb26-702c-49fa-83d9-a9eb44a33bbb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453291746 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 11.sram_ctrl_access_during_key_req.453291746
Directory /workspace/11.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/11.sram_ctrl_alert_test.1325331893
Short name T740
Test name
Test status
Simulation time 43855836 ps
CPU time 0.62 seconds
Started Jan 10 01:26:55 PM PST 24
Finished Jan 10 01:27:07 PM PST 24
Peak memory 201388 kb
Host smart-64f2cacd-a545-4bcb-ab91-0160e598e5f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325331893 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.sram_ctrl_alert_test.1325331893
Directory /workspace/11.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.sram_ctrl_bijection.2991012941
Short name T597
Test name
Test status
Simulation time 690017920833 ps
CPU time 2334.6 seconds
Started Jan 10 01:26:47 PM PST 24
Finished Jan 10 02:05:56 PM PST 24
Peak memory 202160 kb
Host smart-1ab0ddae-f934-4100-80e5-979a8ada3dba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991012941 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection
.2991012941
Directory /workspace/11.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/11.sram_ctrl_lc_escalation.3482753250
Short name T316
Test name
Test status
Simulation time 10638326264 ps
CPU time 255.84 seconds
Started Jan 10 01:26:56 PM PST 24
Finished Jan 10 01:31:23 PM PST 24
Peak memory 202148 kb
Host smart-fc2c735a-68cd-446e-b85a-a92d6401de8e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482753250 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_lc_es
calation.3482753250
Directory /workspace/11.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/11.sram_ctrl_max_throughput.3425141943
Short name T791
Test name
Test status
Simulation time 778116048 ps
CPU time 140.17 seconds
Started Jan 10 01:26:42 PM PST 24
Finished Jan 10 01:29:17 PM PST 24
Peak memory 367820 kb
Host smart-6e69b725-c3fd-49f4-ad61-d8e7274c847c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425141943 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 11.sram_ctrl_max_throughput.3425141943
Directory /workspace/11.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/11.sram_ctrl_mem_partial_access.2729938314
Short name T618
Test name
Test status
Simulation time 9417496622 ps
CPU time 75.29 seconds
Started Jan 10 01:27:02 PM PST 24
Finished Jan 10 01:28:28 PM PST 24
Peak memory 211012 kb
Host smart-d3bb812b-cd36-443d-9be9-ea4b9493c3a6
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729938314 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.sram_ctrl_mem_partial_access.2729938314
Directory /workspace/11.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/11.sram_ctrl_mem_walk.92528818
Short name T923
Test name
Test status
Simulation time 7037557940 ps
CPU time 145 seconds
Started Jan 10 01:26:48 PM PST 24
Finished Jan 10 01:29:26 PM PST 24
Peak memory 202144 kb
Host smart-5dd78efe-b601-44f1-ab2e-344bd2de4b77
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92528818 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sr
am_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_
mem_walk.92528818
Directory /workspace/11.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/11.sram_ctrl_multiple_keys.3662240113
Short name T517
Test name
Test status
Simulation time 29416138017 ps
CPU time 543.69 seconds
Started Jan 10 01:26:54 PM PST 24
Finished Jan 10 01:36:09 PM PST 24
Peak memory 373908 kb
Host smart-97bc6834-8dd2-4632-a28e-aa8b388fcb49
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662240113 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multi
ple_keys.3662240113
Directory /workspace/11.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/11.sram_ctrl_partial_access.772954637
Short name T237
Test name
Test status
Simulation time 3645527832 ps
CPU time 43.45 seconds
Started Jan 10 01:26:58 PM PST 24
Finished Jan 10 01:27:54 PM PST 24
Peak memory 202108 kb
Host smart-ffc41a2c-551b-4217-831d-75164c720248
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772954637 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.s
ram_ctrl_partial_access.772954637
Directory /workspace/11.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.791973929
Short name T540
Test name
Test status
Simulation time 18932120543 ps
CPU time 474.25 seconds
Started Jan 10 01:26:57 PM PST 24
Finished Jan 10 01:35:04 PM PST 24
Peak memory 202052 kb
Host smart-0f4a3bcd-54dc-40c8-9cdd-1e8ee1bc265b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791973929 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.sram_ctrl_partial_access_b2b.791973929
Directory /workspace/11.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/11.sram_ctrl_smoke.1401714738
Short name T349
Test name
Test status
Simulation time 1535720171 ps
CPU time 39.6 seconds
Started Jan 10 01:26:42 PM PST 24
Finished Jan 10 01:27:37 PM PST 24
Peak memory 254720 kb
Host smart-e1ebc118-571b-4005-9add-e1cbcdcbdcdc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401714738 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.1401714738
Directory /workspace/11.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/11.sram_ctrl_stress_all.898578081
Short name T442
Test name
Test status
Simulation time 20682175548 ps
CPU time 1949.2 seconds
Started Jan 10 01:26:57 PM PST 24
Finished Jan 10 01:59:38 PM PST 24
Peak memory 375040 kb
Host smart-0d7e8ed4-f9e6-4137-b7b5-88dc3026bfb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898578081 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 11.sram_ctrl_stress_all.898578081
Directory /workspace/11.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.3868303566
Short name T500
Test name
Test status
Simulation time 471912070 ps
CPU time 1982.87 seconds
Started Jan 10 01:27:02 PM PST 24
Finished Jan 10 02:00:16 PM PST 24
Peak memory 439504 kb
Host smart-8ccc1ddc-3290-4125-961c-45db22cd3504
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3868303566 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all_with_rand_reset.3868303566
Directory /workspace/11.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.sram_ctrl_stress_pipeline.3434694931
Short name T241
Test name
Test status
Simulation time 4460261608 ps
CPU time 191.54 seconds
Started Jan 10 01:26:43 PM PST 24
Finished Jan 10 01:30:10 PM PST 24
Peak memory 202176 kb
Host smart-a1da5e63-84d9-4d15-a05f-9f70d9ace900
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434694931 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.sram_ctrl_stress_pipeline.3434694931
Directory /workspace/11.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.1662000793
Short name T413
Test name
Test status
Simulation time 1672392634 ps
CPU time 43.18 seconds
Started Jan 10 01:26:55 PM PST 24
Finished Jan 10 01:27:50 PM PST 24
Peak memory 267500 kb
Host smart-7dda03c4-e6ce-46b8-a026-79c1242c1bb2
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662000793 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.sram_ctrl_throughput_w_partial_write.1662000793
Directory /workspace/11.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/12.sram_ctrl_access_during_key_req.1899873180
Short name T609
Test name
Test status
Simulation time 1929965728 ps
CPU time 102.25 seconds
Started Jan 10 01:26:58 PM PST 24
Finished Jan 10 01:28:53 PM PST 24
Peak memory 210260 kb
Host smart-e2091203-a0e1-4b8a-b7ef-b6bc7e4d33a6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899873180 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 12.sram_ctrl_access_during_key_req.1899873180
Directory /workspace/12.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/12.sram_ctrl_alert_test.1354458125
Short name T849
Test name
Test status
Simulation time 28417199 ps
CPU time 0.67 seconds
Started Jan 10 01:26:33 PM PST 24
Finished Jan 10 01:26:47 PM PST 24
Peak memory 201760 kb
Host smart-6bf3500e-91c9-4807-8efa-e15a18a6c30a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354458125 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.sram_ctrl_alert_test.1354458125
Directory /workspace/12.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.sram_ctrl_bijection.198001683
Short name T860
Test name
Test status
Simulation time 17385647344 ps
CPU time 1146.11 seconds
Started Jan 10 01:26:57 PM PST 24
Finished Jan 10 01:46:16 PM PST 24
Peak memory 202184 kb
Host smart-ec983cbd-4132-4d3f-a82e-cc7f5c59fb78
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198001683 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection.
198001683
Directory /workspace/12.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/12.sram_ctrl_executable.983433600
Short name T462
Test name
Test status
Simulation time 49015383977 ps
CPU time 905.88 seconds
Started Jan 10 01:26:57 PM PST 24
Finished Jan 10 01:42:15 PM PST 24
Peak memory 376000 kb
Host smart-fb7d2e79-2bbe-4f90-9be0-2945034045ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983433600 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_executabl
e.983433600
Directory /workspace/12.sram_ctrl_executable/latest

Test location /workspace/coverage/default/12.sram_ctrl_max_throughput.657869731
Short name T512
Test name
Test status
Simulation time 2656497922 ps
CPU time 55.45 seconds
Started Jan 10 01:27:01 PM PST 24
Finished Jan 10 01:28:09 PM PST 24
Peak memory 287452 kb
Host smart-74fc70bd-5692-4dc2-90f1-7b02dd055999
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657869731 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.sram_ctrl_max_throughput.657869731
Directory /workspace/12.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/12.sram_ctrl_mem_partial_access.2525823357
Short name T358
Test name
Test status
Simulation time 1622290511 ps
CPU time 130.96 seconds
Started Jan 10 01:26:59 PM PST 24
Finished Jan 10 01:29:22 PM PST 24
Peak memory 210584 kb
Host smart-e9796b37-1a99-4300-8ed3-78380f3e4c96
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525823357 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.sram_ctrl_mem_partial_access.2525823357
Directory /workspace/12.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/12.sram_ctrl_mem_walk.309263168
Short name T875
Test name
Test status
Simulation time 8226557593 ps
CPU time 120.21 seconds
Started Jan 10 01:26:58 PM PST 24
Finished Jan 10 01:29:11 PM PST 24
Peak memory 202076 kb
Host smart-50e6ac87-ae03-4dc7-bd6c-8c01e991b8ee
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309263168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl
_mem_walk.309263168
Directory /workspace/12.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/12.sram_ctrl_multiple_keys.1648358006
Short name T703
Test name
Test status
Simulation time 1813265020 ps
CPU time 371.61 seconds
Started Jan 10 01:26:56 PM PST 24
Finished Jan 10 01:33:20 PM PST 24
Peak memory 372980 kb
Host smart-8a956084-ed3c-4dbe-9b00-53fec239c230
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648358006 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multi
ple_keys.1648358006
Directory /workspace/12.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/12.sram_ctrl_partial_access.370854715
Short name T306
Test name
Test status
Simulation time 775553879 ps
CPU time 14.46 seconds
Started Jan 10 01:26:54 PM PST 24
Finished Jan 10 01:27:20 PM PST 24
Peak memory 202076 kb
Host smart-06dda9b6-4280-4084-9634-6786abfdde13
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370854715 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.s
ram_ctrl_partial_access.370854715
Directory /workspace/12.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.2442313992
Short name T95
Test name
Test status
Simulation time 5116943984 ps
CPU time 224.98 seconds
Started Jan 10 01:27:02 PM PST 24
Finished Jan 10 01:30:58 PM PST 24
Peak memory 202040 kb
Host smart-823d2ab4-d4ec-4a87-8abb-a1859f38bc1d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442313992 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 12.sram_ctrl_partial_access_b2b.2442313992
Directory /workspace/12.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/12.sram_ctrl_ram_cfg.796273751
Short name T811
Test name
Test status
Simulation time 362966428 ps
CPU time 5.37 seconds
Started Jan 10 01:27:00 PM PST 24
Finished Jan 10 01:27:18 PM PST 24
Peak memory 202432 kb
Host smart-5ca4add7-fc62-4fba-acae-e2909b329a67
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796273751 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.796273751
Directory /workspace/12.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/12.sram_ctrl_regwen.825772745
Short name T918
Test name
Test status
Simulation time 5336930480 ps
CPU time 328.85 seconds
Started Jan 10 01:26:56 PM PST 24
Finished Jan 10 01:32:37 PM PST 24
Peak memory 369800 kb
Host smart-b79c5703-3589-485a-94dd-7c8893c945ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825772745 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.825772745
Directory /workspace/12.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/12.sram_ctrl_smoke.1567310201
Short name T433
Test name
Test status
Simulation time 798551967 ps
CPU time 13.14 seconds
Started Jan 10 01:27:02 PM PST 24
Finished Jan 10 01:27:27 PM PST 24
Peak memory 201948 kb
Host smart-e7735af6-9526-4944-ab7a-f9f3303db8e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567310201 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.1567310201
Directory /workspace/12.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.3231508443
Short name T287
Test name
Test status
Simulation time 3783488774 ps
CPU time 2470.94 seconds
Started Jan 10 01:26:59 PM PST 24
Finished Jan 10 02:08:23 PM PST 24
Peak memory 431680 kb
Host smart-e3da7510-9430-4b82-851b-036f293c4d91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3231508443 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all_with_rand_reset.3231508443
Directory /workspace/12.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.sram_ctrl_stress_pipeline.2972776827
Short name T57
Test name
Test status
Simulation time 5126746346 ps
CPU time 372.06 seconds
Started Jan 10 01:26:50 PM PST 24
Finished Jan 10 01:33:15 PM PST 24
Peak memory 202188 kb
Host smart-9e9fbd60-e9a5-47b0-bf88-47802aa753a4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972776827 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.sram_ctrl_stress_pipeline.2972776827
Directory /workspace/12.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.597962044
Short name T967
Test name
Test status
Simulation time 734372009 ps
CPU time 45.67 seconds
Started Jan 10 01:26:57 PM PST 24
Finished Jan 10 01:27:55 PM PST 24
Peak memory 268784 kb
Host smart-5b7bcb81-a5d4-4238-952d-9c465434c507
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597962044 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 12.sram_ctrl_throughput_w_partial_write.597962044
Directory /workspace/12.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/13.sram_ctrl_access_during_key_req.4184349043
Short name T813
Test name
Test status
Simulation time 45606440370 ps
CPU time 1048.68 seconds
Started Jan 10 01:26:54 PM PST 24
Finished Jan 10 01:44:35 PM PST 24
Peak memory 377008 kb
Host smart-a207ba35-89d2-46d4-bba7-81e967548c74
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184349043 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 13.sram_ctrl_access_during_key_req.4184349043
Directory /workspace/13.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/13.sram_ctrl_alert_test.1729533098
Short name T690
Test name
Test status
Simulation time 15683979 ps
CPU time 0.62 seconds
Started Jan 10 01:26:55 PM PST 24
Finished Jan 10 01:27:07 PM PST 24
Peak memory 201576 kb
Host smart-57c45c5e-6d19-4241-956b-72ff7fcd7aed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729533098 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.sram_ctrl_alert_test.1729533098
Directory /workspace/13.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.sram_ctrl_bijection.325953706
Short name T575
Test name
Test status
Simulation time 81613404457 ps
CPU time 1794.45 seconds
Started Jan 10 01:26:29 PM PST 24
Finished Jan 10 01:56:37 PM PST 24
Peak memory 202164 kb
Host smart-750eaf27-8671-4c15-9d46-96def2490158
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325953706 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection.
325953706
Directory /workspace/13.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/13.sram_ctrl_lc_escalation.1211110441
Short name T920
Test name
Test status
Simulation time 8613752661 ps
CPU time 190.16 seconds
Started Jan 10 01:26:52 PM PST 24
Finished Jan 10 01:30:14 PM PST 24
Peak memory 210488 kb
Host smart-09fde5e0-66af-4466-9314-f782c198e6e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211110441 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_es
calation.1211110441
Directory /workspace/13.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/13.sram_ctrl_max_throughput.2776109190
Short name T776
Test name
Test status
Simulation time 758329797 ps
CPU time 57.99 seconds
Started Jan 10 01:26:32 PM PST 24
Finished Jan 10 01:27:42 PM PST 24
Peak memory 293144 kb
Host smart-9264d539-f721-43f3-983d-55594c9542ff
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776109190 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 13.sram_ctrl_max_throughput.2776109190
Directory /workspace/13.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/13.sram_ctrl_mem_partial_access.1494375514
Short name T54
Test name
Test status
Simulation time 9759567730 ps
CPU time 77.24 seconds
Started Jan 10 01:26:55 PM PST 24
Finished Jan 10 01:28:24 PM PST 24
Peak memory 218532 kb
Host smart-2d624291-f721-4fd2-970f-577d6fe44f35
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494375514 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.sram_ctrl_mem_partial_access.1494375514
Directory /workspace/13.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/13.sram_ctrl_mem_walk.985057418
Short name T680
Test name
Test status
Simulation time 4028237929 ps
CPU time 244.62 seconds
Started Jan 10 01:26:47 PM PST 24
Finished Jan 10 01:31:06 PM PST 24
Peak memory 202160 kb
Host smart-593bbc26-f55c-4edf-9619-37fe697fc381
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985057418 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl
_mem_walk.985057418
Directory /workspace/13.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/13.sram_ctrl_multiple_keys.2171267496
Short name T339
Test name
Test status
Simulation time 1677697979 ps
CPU time 112.38 seconds
Started Jan 10 01:26:41 PM PST 24
Finished Jan 10 01:28:49 PM PST 24
Peak memory 291812 kb
Host smart-33a59b66-ca27-4a9e-a96b-16f16ae98fb1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171267496 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multi
ple_keys.2171267496
Directory /workspace/13.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/13.sram_ctrl_partial_access.1657533387
Short name T836
Test name
Test status
Simulation time 1620710728 ps
CPU time 28.87 seconds
Started Jan 10 01:26:34 PM PST 24
Finished Jan 10 01:27:18 PM PST 24
Peak memory 255964 kb
Host smart-ebd02446-7471-4b83-ade3-62d67f72cc6f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657533387 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
sram_ctrl_partial_access.1657533387
Directory /workspace/13.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.2547476365
Short name T120
Test name
Test status
Simulation time 30063699965 ps
CPU time 372.11 seconds
Started Jan 10 01:26:42 PM PST 24
Finished Jan 10 01:33:09 PM PST 24
Peak memory 202180 kb
Host smart-d6850127-e908-4ff5-a47c-8a64557fc9db
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547476365 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 13.sram_ctrl_partial_access_b2b.2547476365
Directory /workspace/13.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/13.sram_ctrl_ram_cfg.2620773424
Short name T619
Test name
Test status
Simulation time 2239265181 ps
CPU time 14.69 seconds
Started Jan 10 01:26:57 PM PST 24
Finished Jan 10 01:27:24 PM PST 24
Peak memory 202436 kb
Host smart-583c27e7-acda-45ca-88ad-638e95f3bc7e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620773424 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.2620773424
Directory /workspace/13.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/13.sram_ctrl_regwen.2395359871
Short name T487
Test name
Test status
Simulation time 17014160649 ps
CPU time 1534.96 seconds
Started Jan 10 01:26:46 PM PST 24
Finished Jan 10 01:52:35 PM PST 24
Peak memory 381152 kb
Host smart-3d6a440f-1525-457e-b9d4-f7ad0f88d118
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395359871 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.2395359871
Directory /workspace/13.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/13.sram_ctrl_smoke.1698670252
Short name T698
Test name
Test status
Simulation time 532096647 ps
CPU time 25.62 seconds
Started Jan 10 01:26:23 PM PST 24
Finished Jan 10 01:27:05 PM PST 24
Peak memory 202064 kb
Host smart-319c15a1-6667-4e0a-b516-25a739467bc7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698670252 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.1698670252
Directory /workspace/13.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/13.sram_ctrl_stress_all.3910263050
Short name T347
Test name
Test status
Simulation time 35304233785 ps
CPU time 1306.27 seconds
Started Jan 10 01:26:56 PM PST 24
Finished Jan 10 01:48:54 PM PST 24
Peak memory 365840 kb
Host smart-3cc201d8-0dc7-408a-b0d9-976129f9eb9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910263050 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 13.sram_ctrl_stress_all.3910263050
Directory /workspace/13.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.2942277473
Short name T472
Test name
Test status
Simulation time 230657863 ps
CPU time 3215.55 seconds
Started Jan 10 01:26:51 PM PST 24
Finished Jan 10 02:20:40 PM PST 24
Peak memory 539292 kb
Host smart-03340877-9d92-43bd-acb0-71fc4612fad6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2942277473 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all_with_rand_reset.2942277473
Directory /workspace/13.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.sram_ctrl_stress_pipeline.3121239698
Short name T693
Test name
Test status
Simulation time 3085098540 ps
CPU time 242.1 seconds
Started Jan 10 01:26:57 PM PST 24
Finished Jan 10 01:31:11 PM PST 24
Peak memory 202204 kb
Host smart-c731e002-4a0f-46a3-a6fb-1b346d7c414b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121239698 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.sram_ctrl_stress_pipeline.3121239698
Directory /workspace/13.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.4142530174
Short name T245
Test name
Test status
Simulation time 2991744535 ps
CPU time 70.67 seconds
Started Jan 10 01:26:51 PM PST 24
Finished Jan 10 01:28:14 PM PST 24
Peak memory 319832 kb
Host smart-d317f85e-2af4-495d-975a-4a2f8580c046
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142530174 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.sram_ctrl_throughput_w_partial_write.4142530174
Directory /workspace/13.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/14.sram_ctrl_access_during_key_req.1292630828
Short name T646
Test name
Test status
Simulation time 5276214863 ps
CPU time 636.41 seconds
Started Jan 10 01:26:56 PM PST 24
Finished Jan 10 01:37:44 PM PST 24
Peak memory 380136 kb
Host smart-f3ad0fbb-6770-4cb1-8356-00b30342b170
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292630828 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.sram_ctrl_access_during_key_req.1292630828
Directory /workspace/14.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/14.sram_ctrl_alert_test.2553941212
Short name T611
Test name
Test status
Simulation time 27403529 ps
CPU time 0.63 seconds
Started Jan 10 01:26:46 PM PST 24
Finished Jan 10 01:27:01 PM PST 24
Peak memory 201880 kb
Host smart-ef31a18a-3fb5-4140-9902-60b6fd515ffb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553941212 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.sram_ctrl_alert_test.2553941212
Directory /workspace/14.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.sram_ctrl_bijection.3433850604
Short name T432
Test name
Test status
Simulation time 61611249804 ps
CPU time 1067.33 seconds
Started Jan 10 01:26:45 PM PST 24
Finished Jan 10 01:44:47 PM PST 24
Peak memory 202172 kb
Host smart-7466dec6-e7cf-4f05-962a-9e9ddbf33404
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433850604 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection
.3433850604
Directory /workspace/14.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/14.sram_ctrl_lc_escalation.2304089076
Short name T359
Test name
Test status
Simulation time 19953809433 ps
CPU time 230.04 seconds
Started Jan 10 01:26:57 PM PST 24
Finished Jan 10 01:31:01 PM PST 24
Peak memory 210408 kb
Host smart-7bf361a4-07c0-4840-946f-6f0252c610de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304089076 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_es
calation.2304089076
Directory /workspace/14.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/14.sram_ctrl_max_throughput.927315249
Short name T718
Test name
Test status
Simulation time 3009183687 ps
CPU time 54.8 seconds
Started Jan 10 01:26:47 PM PST 24
Finished Jan 10 01:27:56 PM PST 24
Peak memory 293320 kb
Host smart-925c8f66-b764-406e-ab27-ae3074d84ebe
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927315249 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.sram_ctrl_max_throughput.927315249
Directory /workspace/14.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/14.sram_ctrl_mem_partial_access.775312249
Short name T546
Test name
Test status
Simulation time 10437959807 ps
CPU time 82.08 seconds
Started Jan 10 01:26:48 PM PST 24
Finished Jan 10 01:28:23 PM PST 24
Peak memory 211188 kb
Host smart-9374f391-3991-4aa6-bacd-e4e75aa988ff
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775312249 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.sram_ctrl_mem_partial_access.775312249
Directory /workspace/14.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/14.sram_ctrl_mem_walk.877186458
Short name T898
Test name
Test status
Simulation time 41313843676 ps
CPU time 312.12 seconds
Started Jan 10 01:26:56 PM PST 24
Finished Jan 10 01:32:20 PM PST 24
Peak memory 202368 kb
Host smart-826825e6-cdaf-4b32-a04a-40dcb1777b35
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877186458 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl
_mem_walk.877186458
Directory /workspace/14.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/14.sram_ctrl_multiple_keys.1039352499
Short name T831
Test name
Test status
Simulation time 15859340789 ps
CPU time 1126.86 seconds
Started Jan 10 01:26:48 PM PST 24
Finished Jan 10 01:45:49 PM PST 24
Peak memory 372836 kb
Host smart-2efb1da8-b4ac-4c91-9b2c-93318a86cc2e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039352499 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multi
ple_keys.1039352499
Directory /workspace/14.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/14.sram_ctrl_partial_access.3250589813
Short name T614
Test name
Test status
Simulation time 2829192645 ps
CPU time 26.03 seconds
Started Jan 10 01:26:55 PM PST 24
Finished Jan 10 01:27:33 PM PST 24
Peak memory 202168 kb
Host smart-422e0abe-fd14-4835-b04f-8fe069605ba4
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250589813 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
sram_ctrl_partial_access.3250589813
Directory /workspace/14.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.1989038887
Short name T645
Test name
Test status
Simulation time 6386708281 ps
CPU time 389.4 seconds
Started Jan 10 01:26:57 PM PST 24
Finished Jan 10 01:33:39 PM PST 24
Peak memory 202220 kb
Host smart-3210683b-f7e2-45e8-8417-0b707a6fbea7
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989038887 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 14.sram_ctrl_partial_access_b2b.1989038887
Directory /workspace/14.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/14.sram_ctrl_ram_cfg.559747433
Short name T843
Test name
Test status
Simulation time 713616515 ps
CPU time 13.81 seconds
Started Jan 10 01:26:56 PM PST 24
Finished Jan 10 01:27:22 PM PST 24
Peak memory 202424 kb
Host smart-4a3d8254-31ca-4474-8fec-36f880d2c133
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559747433 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.559747433
Directory /workspace/14.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/14.sram_ctrl_regwen.3287729515
Short name T599
Test name
Test status
Simulation time 4042511816 ps
CPU time 1056.02 seconds
Started Jan 10 01:26:55 PM PST 24
Finished Jan 10 01:44:43 PM PST 24
Peak memory 378088 kb
Host smart-0969e782-c865-4020-a5b3-9d0d85eb2f06
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287729515 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.3287729515
Directory /workspace/14.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/14.sram_ctrl_smoke.1001664346
Short name T696
Test name
Test status
Simulation time 6414930165 ps
CPU time 122.63 seconds
Started Jan 10 01:26:55 PM PST 24
Finished Jan 10 01:29:10 PM PST 24
Peak memory 369728 kb
Host smart-2ed4458a-39f5-4ea2-b6d8-70f65beced43
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001664346 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.1001664346
Directory /workspace/14.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/14.sram_ctrl_stress_all.1289517403
Short name T936
Test name
Test status
Simulation time 142863877793 ps
CPU time 3149.8 seconds
Started Jan 10 01:26:48 PM PST 24
Finished Jan 10 02:19:31 PM PST 24
Peak memory 381188 kb
Host smart-cc38ed8b-fc21-4a0b-a18c-72e849122cf1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289517403 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 14.sram_ctrl_stress_all.1289517403
Directory /workspace/14.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.3317428344
Short name T799
Test name
Test status
Simulation time 3235494178 ps
CPU time 2087.46 seconds
Started Jan 10 01:26:56 PM PST 24
Finished Jan 10 02:01:55 PM PST 24
Peak memory 421364 kb
Host smart-0276ca48-1aee-454a-8ff9-84175ecca0e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3317428344 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all_with_rand_reset.3317428344
Directory /workspace/14.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.sram_ctrl_stress_pipeline.2260200144
Short name T863
Test name
Test status
Simulation time 17807320917 ps
CPU time 303.76 seconds
Started Jan 10 01:26:57 PM PST 24
Finished Jan 10 01:32:13 PM PST 24
Peak memory 202200 kb
Host smart-0bc203f2-173a-4f04-b914-a60f2485a828
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260200144 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.sram_ctrl_stress_pipeline.2260200144
Directory /workspace/14.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.1907517202
Short name T780
Test name
Test status
Simulation time 700001102 ps
CPU time 34.56 seconds
Started Jan 10 01:26:47 PM PST 24
Finished Jan 10 01:27:36 PM PST 24
Peak memory 240656 kb
Host smart-e2ad3058-65f2-4bc8-bf77-08f61d0b8844
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907517202 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 14.sram_ctrl_throughput_w_partial_write.1907517202
Directory /workspace/14.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/15.sram_ctrl_alert_test.2903897707
Short name T529
Test name
Test status
Simulation time 14936629 ps
CPU time 0.64 seconds
Started Jan 10 01:26:55 PM PST 24
Finished Jan 10 01:27:08 PM PST 24
Peak memory 201872 kb
Host smart-b17d9da5-eb5b-4e22-8a28-eacd854cbdd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903897707 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.sram_ctrl_alert_test.2903897707
Directory /workspace/15.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.sram_ctrl_bijection.3633824388
Short name T123
Test name
Test status
Simulation time 24955082114 ps
CPU time 1647.38 seconds
Started Jan 10 01:26:58 PM PST 24
Finished Jan 10 01:54:38 PM PST 24
Peak memory 202208 kb
Host smart-e4396583-2587-4d13-be95-2a5cd4a1f009
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633824388 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection
.3633824388
Directory /workspace/15.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/15.sram_ctrl_lc_escalation.43162735
Short name T657
Test name
Test status
Simulation time 9313267154 ps
CPU time 89.54 seconds
Started Jan 10 01:26:55 PM PST 24
Finished Jan 10 01:28:36 PM PST 24
Peak memory 202264 kb
Host smart-e7a5c64b-943e-4732-9fde-86b27db33655
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43162735 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_esc
alation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_esca
lation.43162735
Directory /workspace/15.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/15.sram_ctrl_max_throughput.3020822717
Short name T376
Test name
Test status
Simulation time 6079126088 ps
CPU time 29.76 seconds
Started Jan 10 01:26:59 PM PST 24
Finished Jan 10 01:27:41 PM PST 24
Peak memory 210532 kb
Host smart-0db277e0-cb19-418f-b31c-f821a7624628
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020822717 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 15.sram_ctrl_max_throughput.3020822717
Directory /workspace/15.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/15.sram_ctrl_mem_partial_access.1866815673
Short name T738
Test name
Test status
Simulation time 1950484638 ps
CPU time 73.41 seconds
Started Jan 10 01:26:56 PM PST 24
Finished Jan 10 01:28:21 PM PST 24
Peak memory 210688 kb
Host smart-ba768d5f-8de1-4bcd-ba84-cd2c38346aec
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866815673 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.sram_ctrl_mem_partial_access.1866815673
Directory /workspace/15.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/15.sram_ctrl_mem_walk.2347790351
Short name T304
Test name
Test status
Simulation time 2669916541 ps
CPU time 119.92 seconds
Started Jan 10 01:26:51 PM PST 24
Finished Jan 10 01:29:04 PM PST 24
Peak memory 202148 kb
Host smart-234d0487-7da9-4f94-a1c5-a470053ed275
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347790351 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctr
l_mem_walk.2347790351
Directory /workspace/15.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/15.sram_ctrl_multiple_keys.338319803
Short name T865
Test name
Test status
Simulation time 3387041772 ps
CPU time 322.61 seconds
Started Jan 10 01:26:52 PM PST 24
Finished Jan 10 01:32:27 PM PST 24
Peak memory 374840 kb
Host smart-a1abc1d1-d189-4820-a324-16d152d62085
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338319803 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multip
le_keys.338319803
Directory /workspace/15.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/15.sram_ctrl_partial_access.1302760283
Short name T689
Test name
Test status
Simulation time 1518534313 ps
CPU time 20.92 seconds
Started Jan 10 01:26:47 PM PST 24
Finished Jan 10 01:27:22 PM PST 24
Peak memory 202012 kb
Host smart-5fccba17-ad68-4dfc-b4be-f90c03b22657
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302760283 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
sram_ctrl_partial_access.1302760283
Directory /workspace/15.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.2971622713
Short name T913
Test name
Test status
Simulation time 11653948668 ps
CPU time 570.7 seconds
Started Jan 10 01:26:57 PM PST 24
Finished Jan 10 01:36:40 PM PST 24
Peak memory 202188 kb
Host smart-50a3da32-7fd9-4d2d-b7cd-f651c5cab144
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971622713 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 15.sram_ctrl_partial_access_b2b.2971622713
Directory /workspace/15.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/15.sram_ctrl_ram_cfg.2092070298
Short name T916
Test name
Test status
Simulation time 754439295 ps
CPU time 6.22 seconds
Started Jan 10 01:26:57 PM PST 24
Finished Jan 10 01:27:15 PM PST 24
Peak memory 202432 kb
Host smart-0324487e-b95d-4509-a686-2b6c742ed951
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092070298 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.2092070298
Directory /workspace/15.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/15.sram_ctrl_regwen.3652637216
Short name T26
Test name
Test status
Simulation time 8150994366 ps
CPU time 647.58 seconds
Started Jan 10 01:26:57 PM PST 24
Finished Jan 10 01:37:56 PM PST 24
Peak memory 366012 kb
Host smart-7bb2c42a-1de5-4198-8b86-319139319e20
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652637216 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.3652637216
Directory /workspace/15.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/15.sram_ctrl_smoke.969017807
Short name T260
Test name
Test status
Simulation time 3770899408 ps
CPU time 39.88 seconds
Started Jan 10 01:26:47 PM PST 24
Finished Jan 10 01:27:41 PM PST 24
Peak memory 202084 kb
Host smart-181da0ef-8d05-4b0b-ab3b-9ef8d6723ebf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969017807 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.969017807
Directory /workspace/15.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/15.sram_ctrl_stress_pipeline.2334245868
Short name T762
Test name
Test status
Simulation time 10728312420 ps
CPU time 407.12 seconds
Started Jan 10 01:26:55 PM PST 24
Finished Jan 10 01:33:54 PM PST 24
Peak memory 202356 kb
Host smart-4f1fd9e3-ddc8-4cf0-9547-f609c0adbc52
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334245868 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.sram_ctrl_stress_pipeline.2334245868
Directory /workspace/15.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.2388609574
Short name T928
Test name
Test status
Simulation time 811486540 ps
CPU time 161.57 seconds
Started Jan 10 01:26:50 PM PST 24
Finished Jan 10 01:29:44 PM PST 24
Peak memory 372904 kb
Host smart-2a2e4a8c-2c88-4e8c-85c7-154a8d65169a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388609574 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.sram_ctrl_throughput_w_partial_write.2388609574
Directory /workspace/15.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/16.sram_ctrl_access_during_key_req.2492371701
Short name T17
Test name
Test status
Simulation time 154816222614 ps
CPU time 840.44 seconds
Started Jan 10 01:26:57 PM PST 24
Finished Jan 10 01:41:09 PM PST 24
Peak memory 380144 kb
Host smart-eb630baa-41c8-4cd0-95e2-c12c34c07dc3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492371701 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 16.sram_ctrl_access_during_key_req.2492371701
Directory /workspace/16.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/16.sram_ctrl_bijection.3386074921
Short name T959
Test name
Test status
Simulation time 46043319676 ps
CPU time 1802.6 seconds
Started Jan 10 01:26:52 PM PST 24
Finished Jan 10 01:57:07 PM PST 24
Peak memory 202152 kb
Host smart-9caf21c0-1c0d-40e5-8a5b-a7ef98226a71
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386074921 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection
.3386074921
Directory /workspace/16.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/16.sram_ctrl_lc_escalation.3409936827
Short name T728
Test name
Test status
Simulation time 26440365137 ps
CPU time 183.63 seconds
Started Jan 10 01:26:56 PM PST 24
Finished Jan 10 01:30:12 PM PST 24
Peak memory 210404 kb
Host smart-34101a7e-fff2-4876-a8a9-a0b2e3f23bc8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409936827 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_lc_es
calation.3409936827
Directory /workspace/16.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/16.sram_ctrl_max_throughput.1207836072
Short name T627
Test name
Test status
Simulation time 3124227211 ps
CPU time 84.36 seconds
Started Jan 10 01:26:58 PM PST 24
Finished Jan 10 01:28:34 PM PST 24
Peak memory 339168 kb
Host smart-454f6610-7b33-4e01-ac7a-19fa1537ba07
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207836072 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 16.sram_ctrl_max_throughput.1207836072
Directory /workspace/16.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/16.sram_ctrl_mem_partial_access.3417289354
Short name T711
Test name
Test status
Simulation time 9025309656 ps
CPU time 79.03 seconds
Started Jan 10 01:26:54 PM PST 24
Finished Jan 10 01:28:25 PM PST 24
Peak memory 218532 kb
Host smart-e00710d3-546f-4246-81bd-b2d1f4063f05
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417289354 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.sram_ctrl_mem_partial_access.3417289354
Directory /workspace/16.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/16.sram_ctrl_mem_walk.1486882890
Short name T590
Test name
Test status
Simulation time 42990573202 ps
CPU time 162.65 seconds
Started Jan 10 01:26:58 PM PST 24
Finished Jan 10 01:29:52 PM PST 24
Peak memory 202180 kb
Host smart-06d4ee89-fbea-4de6-9301-69af0b10a8f4
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486882890 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctr
l_mem_walk.1486882890
Directory /workspace/16.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/16.sram_ctrl_multiple_keys.2382722908
Short name T523
Test name
Test status
Simulation time 2352182994 ps
CPU time 373.98 seconds
Started Jan 10 01:26:49 PM PST 24
Finished Jan 10 01:33:16 PM PST 24
Peak memory 372024 kb
Host smart-c9265000-92bd-494a-b58e-3813287c9481
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382722908 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multi
ple_keys.2382722908
Directory /workspace/16.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/16.sram_ctrl_partial_access.495191040
Short name T285
Test name
Test status
Simulation time 3431464604 ps
CPU time 22.41 seconds
Started Jan 10 01:26:47 PM PST 24
Finished Jan 10 01:27:24 PM PST 24
Peak memory 240252 kb
Host smart-6e40baf5-f5a4-47e1-a758-8a2b3817606c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495191040 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.s
ram_ctrl_partial_access.495191040
Directory /workspace/16.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.2358813322
Short name T809
Test name
Test status
Simulation time 6670726148 ps
CPU time 401.31 seconds
Started Jan 10 01:26:59 PM PST 24
Finished Jan 10 01:33:52 PM PST 24
Peak memory 202284 kb
Host smart-8ba6ff53-9dd3-4e74-93f0-f75a3b29c849
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358813322 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 16.sram_ctrl_partial_access_b2b.2358813322
Directory /workspace/16.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/16.sram_ctrl_ram_cfg.3813674267
Short name T691
Test name
Test status
Simulation time 3362442686 ps
CPU time 7.45 seconds
Started Jan 10 01:26:56 PM PST 24
Finished Jan 10 01:27:15 PM PST 24
Peak memory 202468 kb
Host smart-26425815-50bf-4541-91ff-6fa220e2c3ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813674267 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.3813674267
Directory /workspace/16.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/16.sram_ctrl_regwen.871755080
Short name T640
Test name
Test status
Simulation time 1777704330 ps
CPU time 571.85 seconds
Started Jan 10 01:26:50 PM PST 24
Finished Jan 10 01:36:34 PM PST 24
Peak memory 373836 kb
Host smart-0cfe4f79-0d7b-4e33-9aa7-3140d382bdf2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871755080 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.871755080
Directory /workspace/16.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/16.sram_ctrl_smoke.258296516
Short name T577
Test name
Test status
Simulation time 820652717 ps
CPU time 8.11 seconds
Started Jan 10 01:26:57 PM PST 24
Finished Jan 10 01:27:17 PM PST 24
Peak memory 206628 kb
Host smart-d2d567ee-93b0-4de7-a5c4-585d3e940638
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258296516 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.258296516
Directory /workspace/16.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/16.sram_ctrl_stress_all.1721845412
Short name T629
Test name
Test status
Simulation time 156232553484 ps
CPU time 4008.68 seconds
Started Jan 10 01:26:52 PM PST 24
Finished Jan 10 02:33:53 PM PST 24
Peak memory 382188 kb
Host smart-aefc41bd-3267-4138-8b5c-d9eeb0b351ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721845412 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 16.sram_ctrl_stress_all.1721845412
Directory /workspace/16.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.4173352004
Short name T606
Test name
Test status
Simulation time 10254781577 ps
CPU time 3672.71 seconds
Started Jan 10 01:27:02 PM PST 24
Finished Jan 10 02:28:26 PM PST 24
Peak memory 699016 kb
Host smart-97019f6c-3c55-49ef-b928-f0cfbd11ec97
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4173352004 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all_with_rand_reset.4173352004
Directory /workspace/16.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.sram_ctrl_stress_pipeline.2100082716
Short name T40
Test name
Test status
Simulation time 29029955458 ps
CPU time 267.32 seconds
Started Jan 10 01:27:02 PM PST 24
Finished Jan 10 01:31:41 PM PST 24
Peak memory 202084 kb
Host smart-de8438b5-d993-4470-b71e-48babc1e6bc8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100082716 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.sram_ctrl_stress_pipeline.2100082716
Directory /workspace/16.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.4005413937
Short name T676
Test name
Test status
Simulation time 815466632 ps
CPU time 134.77 seconds
Started Jan 10 01:26:54 PM PST 24
Finished Jan 10 01:29:26 PM PST 24
Peak memory 354512 kb
Host smart-b818d0e2-8388-4b18-af73-ca1009ce8dd4
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005413937 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.sram_ctrl_throughput_w_partial_write.4005413937
Directory /workspace/16.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/17.sram_ctrl_access_during_key_req.2650243896
Short name T411
Test name
Test status
Simulation time 24370027391 ps
CPU time 491.07 seconds
Started Jan 10 01:26:59 PM PST 24
Finished Jan 10 01:35:22 PM PST 24
Peak memory 351568 kb
Host smart-20d2deb0-d322-4ebc-86fa-0cee45b0582a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650243896 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.sram_ctrl_access_during_key_req.2650243896
Directory /workspace/17.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/17.sram_ctrl_alert_test.25929883
Short name T20
Test name
Test status
Simulation time 12475752 ps
CPU time 0.7 seconds
Started Jan 10 01:27:02 PM PST 24
Finished Jan 10 01:27:14 PM PST 24
Peak memory 201836 kb
Host smart-a0045065-544a-402d-9d5b-4c91c62ccb4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25929883 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.sram_ctrl_alert_test.25929883
Directory /workspace/17.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.sram_ctrl_bijection.3543755012
Short name T9
Test name
Test status
Simulation time 431004546518 ps
CPU time 2151.1 seconds
Started Jan 10 01:26:53 PM PST 24
Finished Jan 10 02:02:56 PM PST 24
Peak memory 202176 kb
Host smart-d4b16056-8e94-45d1-b2cd-2ed3d8d5c5c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543755012 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection
.3543755012
Directory /workspace/17.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/17.sram_ctrl_executable.1325033801
Short name T122
Test name
Test status
Simulation time 10250924362 ps
CPU time 371.32 seconds
Started Jan 10 01:27:02 PM PST 24
Finished Jan 10 01:33:25 PM PST 24
Peak memory 378080 kb
Host smart-ce7ff3a4-1fc5-481f-8e48-394e77eff93d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325033801 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_executab
le.1325033801
Directory /workspace/17.sram_ctrl_executable/latest

Test location /workspace/coverage/default/17.sram_ctrl_lc_escalation.71394718
Short name T263
Test name
Test status
Simulation time 2236195579 ps
CPU time 33.2 seconds
Started Jan 10 01:26:55 PM PST 24
Finished Jan 10 01:27:40 PM PST 24
Peak memory 210348 kb
Host smart-b1e15caa-ff85-447c-b6bc-7ac857a0c137
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71394718 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_esc
alation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_esca
lation.71394718
Directory /workspace/17.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/17.sram_ctrl_max_throughput.1876053647
Short name T709
Test name
Test status
Simulation time 8455028824 ps
CPU time 115.21 seconds
Started Jan 10 01:27:10 PM PST 24
Finished Jan 10 01:29:11 PM PST 24
Peak memory 366784 kb
Host smart-fa806306-6b3c-4714-a6ec-28fd41d6776a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876053647 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 17.sram_ctrl_max_throughput.1876053647
Directory /workspace/17.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/17.sram_ctrl_mem_partial_access.838536570
Short name T79
Test name
Test status
Simulation time 9211905395 ps
CPU time 146.19 seconds
Started Jan 10 01:27:07 PM PST 24
Finished Jan 10 01:29:41 PM PST 24
Peak memory 211200 kb
Host smart-481d7a15-6534-4fb0-aad9-6d63c95c96a0
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838536570 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.sram_ctrl_mem_partial_access.838536570
Directory /workspace/17.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/17.sram_ctrl_mem_walk.3420303567
Short name T686
Test name
Test status
Simulation time 11039846875 ps
CPU time 150.6 seconds
Started Jan 10 01:26:54 PM PST 24
Finished Jan 10 01:29:36 PM PST 24
Peak memory 202576 kb
Host smart-3ab692b3-b8e1-4de5-8382-e9d3e569ba31
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420303567 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctr
l_mem_walk.3420303567
Directory /workspace/17.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/17.sram_ctrl_multiple_keys.4192754151
Short name T455
Test name
Test status
Simulation time 14013954273 ps
CPU time 534.29 seconds
Started Jan 10 01:27:00 PM PST 24
Finished Jan 10 01:36:07 PM PST 24
Peak memory 340912 kb
Host smart-1d6d60ed-8a43-40cf-8f62-cf058a774170
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192754151 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multi
ple_keys.4192754151
Directory /workspace/17.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/17.sram_ctrl_partial_access.2001177436
Short name T726
Test name
Test status
Simulation time 2228636495 ps
CPU time 19.05 seconds
Started Jan 10 01:26:53 PM PST 24
Finished Jan 10 01:27:23 PM PST 24
Peak memory 257416 kb
Host smart-8d857ed7-4de4-4424-ba23-1094cbb348c1
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001177436 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
sram_ctrl_partial_access.2001177436
Directory /workspace/17.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.2170354966
Short name T435
Test name
Test status
Simulation time 11684157203 ps
CPU time 233.8 seconds
Started Jan 10 01:26:58 PM PST 24
Finished Jan 10 01:31:04 PM PST 24
Peak memory 202144 kb
Host smart-4069c72e-d83b-408f-a9b2-a6eea5d80698
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170354966 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 17.sram_ctrl_partial_access_b2b.2170354966
Directory /workspace/17.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/17.sram_ctrl_ram_cfg.2197698632
Short name T789
Test name
Test status
Simulation time 1530818444 ps
CPU time 13.34 seconds
Started Jan 10 01:27:11 PM PST 24
Finished Jan 10 01:27:29 PM PST 24
Peak memory 202488 kb
Host smart-73b10a48-07a1-42ad-8d0b-1fba0975e8a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197698632 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.2197698632
Directory /workspace/17.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/17.sram_ctrl_regwen.673261420
Short name T569
Test name
Test status
Simulation time 65991352911 ps
CPU time 907.78 seconds
Started Jan 10 01:26:59 PM PST 24
Finished Jan 10 01:42:19 PM PST 24
Peak memory 373004 kb
Host smart-44ca6b5e-4cc2-4605-9c2a-b64d69c8cd94
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673261420 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.673261420
Directory /workspace/17.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/17.sram_ctrl_smoke.4240456167
Short name T510
Test name
Test status
Simulation time 4537473311 ps
CPU time 18.88 seconds
Started Jan 10 01:26:56 PM PST 24
Finished Jan 10 01:27:27 PM PST 24
Peak memory 233068 kb
Host smart-71834084-63a5-46e2-a44b-d1859a2b12b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240456167 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.4240456167
Directory /workspace/17.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/17.sram_ctrl_stress_all.315322407
Short name T531
Test name
Test status
Simulation time 157835890401 ps
CPU time 5527.27 seconds
Started Jan 10 01:26:56 PM PST 24
Finished Jan 10 02:59:15 PM PST 24
Peak memory 381108 kb
Host smart-ed27367c-5d6e-48e8-97cc-03f330264e0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315322407 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 17.sram_ctrl_stress_all.315322407
Directory /workspace/17.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.2777706389
Short name T257
Test name
Test status
Simulation time 11124530209 ps
CPU time 4374.56 seconds
Started Jan 10 01:27:03 PM PST 24
Finished Jan 10 02:40:09 PM PST 24
Peak memory 570804 kb
Host smart-d96b8c5d-8960-4510-87a8-0b0f1edcfe6c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2777706389 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all_with_rand_reset.2777706389
Directory /workspace/17.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.sram_ctrl_stress_pipeline.1697849540
Short name T448
Test name
Test status
Simulation time 4754376268 ps
CPU time 348.61 seconds
Started Jan 10 01:27:09 PM PST 24
Finished Jan 10 01:33:04 PM PST 24
Peak memory 202172 kb
Host smart-eed62761-00ab-459f-989b-1c3a6b7d5d55
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697849540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.sram_ctrl_stress_pipeline.1697849540
Directory /workspace/17.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.644612931
Short name T756
Test name
Test status
Simulation time 2091827337 ps
CPU time 57.72 seconds
Started Jan 10 01:26:58 PM PST 24
Finished Jan 10 01:28:08 PM PST 24
Peak memory 290992 kb
Host smart-0f3cfdef-6d74-4a92-943c-4576d6110c1e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644612931 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 17.sram_ctrl_throughput_w_partial_write.644612931
Directory /workspace/17.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/18.sram_ctrl_access_during_key_req.567573545
Short name T672
Test name
Test status
Simulation time 14452852889 ps
CPU time 2477.96 seconds
Started Jan 10 01:26:56 PM PST 24
Finished Jan 10 02:08:25 PM PST 24
Peak memory 380044 kb
Host smart-026c36d6-f115-4525-aebe-ce6a24a05134
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567573545 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 18.sram_ctrl_access_during_key_req.567573545
Directory /workspace/18.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/18.sram_ctrl_alert_test.3664032587
Short name T679
Test name
Test status
Simulation time 27834749 ps
CPU time 0.66 seconds
Started Jan 10 01:26:51 PM PST 24
Finished Jan 10 01:27:04 PM PST 24
Peak memory 201900 kb
Host smart-c5d6e88c-d47b-46d0-8332-d072af09d800
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664032587 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.sram_ctrl_alert_test.3664032587
Directory /workspace/18.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.sram_ctrl_bijection.1097890989
Short name T221
Test name
Test status
Simulation time 149414339568 ps
CPU time 962.8 seconds
Started Jan 10 01:26:57 PM PST 24
Finished Jan 10 01:43:12 PM PST 24
Peak memory 202064 kb
Host smart-2c815196-ba6f-4c2f-a17d-09d5a4e1f3c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097890989 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection
.1097890989
Directory /workspace/18.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/18.sram_ctrl_max_throughput.3261767193
Short name T794
Test name
Test status
Simulation time 1429834031 ps
CPU time 71.69 seconds
Started Jan 10 01:26:58 PM PST 24
Finished Jan 10 01:28:22 PM PST 24
Peak memory 311316 kb
Host smart-1c3389f7-49f1-42a4-8952-21b03f69da79
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261767193 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 18.sram_ctrl_max_throughput.3261767193
Directory /workspace/18.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/18.sram_ctrl_mem_partial_access.1480813792
Short name T365
Test name
Test status
Simulation time 17419659099 ps
CPU time 150.3 seconds
Started Jan 10 01:26:46 PM PST 24
Finished Jan 10 01:29:31 PM PST 24
Peak memory 211292 kb
Host smart-33fc4042-01dc-4f72-a3a0-05ad16f1fb5e
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480813792 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.sram_ctrl_mem_partial_access.1480813792
Directory /workspace/18.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/18.sram_ctrl_mem_walk.265132049
Short name T509
Test name
Test status
Simulation time 108536991488 ps
CPU time 310.06 seconds
Started Jan 10 01:26:46 PM PST 24
Finished Jan 10 01:32:10 PM PST 24
Peak memory 202180 kb
Host smart-afc237c0-4665-48c5-86c8-75d03463e07d
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265132049 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl
_mem_walk.265132049
Directory /workspace/18.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/18.sram_ctrl_multiple_keys.223125030
Short name T319
Test name
Test status
Simulation time 15709776981 ps
CPU time 238.53 seconds
Started Jan 10 01:27:16 PM PST 24
Finished Jan 10 01:31:17 PM PST 24
Peak memory 344212 kb
Host smart-8c1b2929-bc8e-4ee8-932d-d848838b87f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223125030 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multip
le_keys.223125030
Directory /workspace/18.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/18.sram_ctrl_partial_access.4127590218
Short name T524
Test name
Test status
Simulation time 3034735844 ps
CPU time 115.88 seconds
Started Jan 10 01:27:00 PM PST 24
Finished Jan 10 01:29:08 PM PST 24
Peak memory 345280 kb
Host smart-b905dc70-06c1-44dd-8790-93bc35da462b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127590218 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
sram_ctrl_partial_access.4127590218
Directory /workspace/18.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/18.sram_ctrl_ram_cfg.8802975
Short name T909
Test name
Test status
Simulation time 1532037520 ps
CPU time 6.44 seconds
Started Jan 10 01:26:58 PM PST 24
Finished Jan 10 01:27:16 PM PST 24
Peak memory 202432 kb
Host smart-386e1475-de91-4dd4-a484-1899143a120a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8802975 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.8802975
Directory /workspace/18.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/18.sram_ctrl_regwen.4066673677
Short name T669
Test name
Test status
Simulation time 58067598800 ps
CPU time 1355.96 seconds
Started Jan 10 01:26:51 PM PST 24
Finished Jan 10 01:49:40 PM PST 24
Peak memory 379104 kb
Host smart-1365bfac-5fb7-4fe9-9f4a-ddeaf33a601f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066673677 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.4066673677
Directory /workspace/18.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/18.sram_ctrl_smoke.2653045261
Short name T387
Test name
Test status
Simulation time 3793840079 ps
CPU time 20.6 seconds
Started Jan 10 01:26:56 PM PST 24
Finished Jan 10 01:27:28 PM PST 24
Peak memory 202128 kb
Host smart-0e1e04d7-775f-4ea8-be58-56a2c3b81d0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653045261 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.2653045261
Directory /workspace/18.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.10032234
Short name T395
Test name
Test status
Simulation time 3098924947 ps
CPU time 5022.1 seconds
Started Jan 10 01:26:48 PM PST 24
Finished Jan 10 02:50:44 PM PST 24
Peak memory 538044 kb
Host smart-6e7c3375-3405-4d31-84a2-99d1626443ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=10032234 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_all_with_rand_reset.10032234
Directory /workspace/18.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.sram_ctrl_stress_pipeline.3069579312
Short name T252
Test name
Test status
Simulation time 12360216783 ps
CPU time 193.36 seconds
Started Jan 10 01:26:54 PM PST 24
Finished Jan 10 01:30:20 PM PST 24
Peak memory 202160 kb
Host smart-179f8970-9791-4b21-b58d-4e1fc702ebdd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069579312 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.sram_ctrl_stress_pipeline.3069579312
Directory /workspace/18.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.35114729
Short name T720
Test name
Test status
Simulation time 1326971850 ps
CPU time 28.23 seconds
Started Jan 10 01:26:53 PM PST 24
Finished Jan 10 01:27:33 PM PST 24
Peak memory 219560 kb
Host smart-a5b5bae3-8255-495a-be97-509ceb36c4c2
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35114729 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.sram_ctrl_throughput_w_partial_write.35114729
Directory /workspace/18.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/19.sram_ctrl_access_during_key_req.1560380262
Short name T788
Test name
Test status
Simulation time 44625823501 ps
CPU time 753.76 seconds
Started Jan 10 01:26:57 PM PST 24
Finished Jan 10 01:39:43 PM PST 24
Peak memory 379092 kb
Host smart-faa3c560-3145-4fe1-84eb-39ad2342685e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560380262 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.sram_ctrl_access_during_key_req.1560380262
Directory /workspace/19.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/19.sram_ctrl_alert_test.2827742383
Short name T847
Test name
Test status
Simulation time 14581287 ps
CPU time 0.65 seconds
Started Jan 10 01:26:52 PM PST 24
Finished Jan 10 01:27:05 PM PST 24
Peak memory 201460 kb
Host smart-29015fb1-b652-49cd-b970-07ab097ec972
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827742383 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.sram_ctrl_alert_test.2827742383
Directory /workspace/19.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.sram_ctrl_bijection.4019667268
Short name T233
Test name
Test status
Simulation time 103426146637 ps
CPU time 1391.52 seconds
Started Jan 10 01:27:01 PM PST 24
Finished Jan 10 01:50:25 PM PST 24
Peak memory 202168 kb
Host smart-5750875c-daaa-4658-92bb-d8920067ceb4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019667268 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection
.4019667268
Directory /workspace/19.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/19.sram_ctrl_lc_escalation.4134053491
Short name T426
Test name
Test status
Simulation time 45767190211 ps
CPU time 295.08 seconds
Started Jan 10 01:26:57 PM PST 24
Finished Jan 10 01:32:04 PM PST 24
Peak memory 202188 kb
Host smart-543f2a8b-41b8-4a50-a435-f56d2c31d51a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134053491 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_es
calation.4134053491
Directory /workspace/19.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/19.sram_ctrl_max_throughput.3283036791
Short name T303
Test name
Test status
Simulation time 2941790806 ps
CPU time 66.85 seconds
Started Jan 10 01:26:58 PM PST 24
Finished Jan 10 01:28:17 PM PST 24
Peak memory 306536 kb
Host smart-67e810c4-337f-494c-8360-404f882400af
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283036791 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 19.sram_ctrl_max_throughput.3283036791
Directory /workspace/19.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/19.sram_ctrl_mem_partial_access.767966376
Short name T280
Test name
Test status
Simulation time 2751443993 ps
CPU time 81.34 seconds
Started Jan 10 01:26:59 PM PST 24
Finished Jan 10 01:28:33 PM PST 24
Peak memory 211832 kb
Host smart-a118eae7-3a80-46e2-bc4c-be98f38d48bf
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767966376 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.sram_ctrl_mem_partial_access.767966376
Directory /workspace/19.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/19.sram_ctrl_mem_walk.3465584339
Short name T541
Test name
Test status
Simulation time 2038851582 ps
CPU time 120.92 seconds
Started Jan 10 01:26:58 PM PST 24
Finished Jan 10 01:29:11 PM PST 24
Peak memory 202036 kb
Host smart-c3a9f9ff-bcb0-45b2-9f8d-206e6da8f115
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465584339 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctr
l_mem_walk.3465584339
Directory /workspace/19.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/19.sram_ctrl_multiple_keys.3208914852
Short name T216
Test name
Test status
Simulation time 154289761568 ps
CPU time 1626.07 seconds
Started Jan 10 01:26:58 PM PST 24
Finished Jan 10 01:54:17 PM PST 24
Peak memory 372016 kb
Host smart-76eaf272-e30f-4d34-92d3-085b3c37c2e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208914852 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multi
ple_keys.3208914852
Directory /workspace/19.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/19.sram_ctrl_partial_access.552975761
Short name T837
Test name
Test status
Simulation time 1344549108 ps
CPU time 14.13 seconds
Started Jan 10 01:26:59 PM PST 24
Finished Jan 10 01:27:26 PM PST 24
Peak memory 202092 kb
Host smart-a7a80039-f85d-4d1c-815f-50400bd3f00e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552975761 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.s
ram_ctrl_partial_access.552975761
Directory /workspace/19.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.2641078245
Short name T532
Test name
Test status
Simulation time 6723752571 ps
CPU time 449.16 seconds
Started Jan 10 01:26:52 PM PST 24
Finished Jan 10 01:34:33 PM PST 24
Peak memory 202160 kb
Host smart-31d49b55-dcb7-4604-8bc5-dbd0818dca22
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641078245 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 19.sram_ctrl_partial_access_b2b.2641078245
Directory /workspace/19.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/19.sram_ctrl_ram_cfg.1411485654
Short name T912
Test name
Test status
Simulation time 695844136 ps
CPU time 14.29 seconds
Started Jan 10 01:26:50 PM PST 24
Finished Jan 10 01:27:17 PM PST 24
Peak memory 202340 kb
Host smart-3b1c9a8d-8523-43de-834a-05ac821aa35d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411485654 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.1411485654
Directory /workspace/19.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/19.sram_ctrl_regwen.943130199
Short name T919
Test name
Test status
Simulation time 26454881453 ps
CPU time 315.14 seconds
Started Jan 10 01:26:57 PM PST 24
Finished Jan 10 01:32:25 PM PST 24
Peak memory 375300 kb
Host smart-2da2a019-f8e6-48d2-9a4f-558a4b37f199
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943130199 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.943130199
Directory /workspace/19.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/19.sram_ctrl_smoke.3753504760
Short name T663
Test name
Test status
Simulation time 2245118785 ps
CPU time 21.93 seconds
Started Jan 10 01:26:56 PM PST 24
Finished Jan 10 01:27:29 PM PST 24
Peak memory 256516 kb
Host smart-041eb85b-7ead-4f6f-96fc-7658e406eab0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753504760 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.3753504760
Directory /workspace/19.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.740377890
Short name T481
Test name
Test status
Simulation time 2283504615 ps
CPU time 3318.52 seconds
Started Jan 10 01:27:00 PM PST 24
Finished Jan 10 02:22:31 PM PST 24
Peak memory 594384 kb
Host smart-9d64ece3-de79-4052-b5c9-d1f9d82900e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=740377890 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all_with_rand_reset.740377890
Directory /workspace/19.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.sram_ctrl_stress_pipeline.927265588
Short name T504
Test name
Test status
Simulation time 14405223926 ps
CPU time 309.87 seconds
Started Jan 10 01:26:47 PM PST 24
Finished Jan 10 01:32:11 PM PST 24
Peak memory 202096 kb
Host smart-2b645067-9830-4daf-8826-28b9e6bca5a8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927265588 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.sram_ctrl_stress_pipeline.927265588
Directory /workspace/19.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.1048520484
Short name T592
Test name
Test status
Simulation time 1380685907 ps
CPU time 48.89 seconds
Started Jan 10 01:26:51 PM PST 24
Finished Jan 10 01:27:52 PM PST 24
Peak memory 275476 kb
Host smart-6f276d04-0a0f-4595-b20d-7189754d811e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048520484 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 19.sram_ctrl_throughput_w_partial_write.1048520484
Directory /workspace/19.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/2.sram_ctrl_access_during_key_req.1881120752
Short name T422
Test name
Test status
Simulation time 50547776376 ps
CPU time 1287.56 seconds
Started Jan 10 01:25:58 PM PST 24
Finished Jan 10 01:47:41 PM PST 24
Peak memory 376036 kb
Host smart-0a613c98-c719-45e3-be00-efb1f4be0233
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881120752 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.sram_ctrl_access_during_key_req.1881120752
Directory /workspace/2.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/2.sram_ctrl_alert_test.2385846937
Short name T297
Test name
Test status
Simulation time 41483290 ps
CPU time 0.64 seconds
Started Jan 10 01:26:03 PM PST 24
Finished Jan 10 01:26:21 PM PST 24
Peak memory 201856 kb
Host smart-dd092f8d-a34b-4a08-b18a-33a51823d32a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385846937 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.sram_ctrl_alert_test.2385846937
Directory /workspace/2.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.sram_ctrl_bijection.1616767427
Short name T737
Test name
Test status
Simulation time 154355594760 ps
CPU time 873.92 seconds
Started Jan 10 01:26:05 PM PST 24
Finished Jan 10 01:40:59 PM PST 24
Peak memory 202212 kb
Host smart-a998e765-de9a-445d-b26e-2c3b6f7c815e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616767427 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection.
1616767427
Directory /workspace/2.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/2.sram_ctrl_executable.735495910
Short name T651
Test name
Test status
Simulation time 18136310490 ps
CPU time 957.72 seconds
Started Jan 10 01:26:02 PM PST 24
Finished Jan 10 01:42:17 PM PST 24
Peak memory 375996 kb
Host smart-3aa4a03d-f8d2-47a7-ae0e-fbcfd1cb52b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735495910 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_executable
.735495910
Directory /workspace/2.sram_ctrl_executable/latest

Test location /workspace/coverage/default/2.sram_ctrl_lc_escalation.2286408090
Short name T506
Test name
Test status
Simulation time 28066700458 ps
CPU time 63.99 seconds
Started Jan 10 01:26:06 PM PST 24
Finished Jan 10 01:27:31 PM PST 24
Peak memory 202224 kb
Host smart-07b7f068-7907-4767-87b9-26b823eea1ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286408090 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_esc
alation.2286408090
Directory /workspace/2.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/2.sram_ctrl_max_throughput.2134484132
Short name T321
Test name
Test status
Simulation time 742566057 ps
CPU time 48.67 seconds
Started Jan 10 01:25:57 PM PST 24
Finished Jan 10 01:27:01 PM PST 24
Peak memory 284900 kb
Host smart-5f2701c5-bdea-4879-81bf-23c21c6d5089
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134484132 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.sram_ctrl_max_throughput.2134484132
Directory /workspace/2.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/2.sram_ctrl_mem_partial_access.92927409
Short name T346
Test name
Test status
Simulation time 19555605095 ps
CPU time 146.89 seconds
Started Jan 10 01:26:02 PM PST 24
Finished Jan 10 01:28:45 PM PST 24
Peak memory 211212 kb
Host smart-bd75d176-d461-424b-986b-dbac89ba427a
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92927409 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.s
ram_ctrl_mem_partial_access.92927409
Directory /workspace/2.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/2.sram_ctrl_mem_walk.1909431414
Short name T308
Test name
Test status
Simulation time 19706461602 ps
CPU time 241.67 seconds
Started Jan 10 01:26:09 PM PST 24
Finished Jan 10 01:30:33 PM PST 24
Peak memory 202348 kb
Host smart-254217bb-d6d7-4aa7-9cf9-5ac432bfaf55
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909431414 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl
_mem_walk.1909431414
Directory /workspace/2.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/2.sram_ctrl_multiple_keys.500307315
Short name T647
Test name
Test status
Simulation time 12924067593 ps
CPU time 1172.69 seconds
Started Jan 10 01:26:05 PM PST 24
Finished Jan 10 01:45:57 PM PST 24
Peak memory 374932 kb
Host smart-6d62c8ab-06fb-4190-9473-64a95c05a474
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500307315 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multipl
e_keys.500307315
Directory /workspace/2.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/2.sram_ctrl_partial_access.2441778805
Short name T552
Test name
Test status
Simulation time 524200319 ps
CPU time 112.74 seconds
Started Jan 10 01:26:05 PM PST 24
Finished Jan 10 01:28:17 PM PST 24
Peak memory 355264 kb
Host smart-0504df19-d14e-40e6-9b1c-5d5aa3df6105
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441778805 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.s
ram_ctrl_partial_access.2441778805
Directory /workspace/2.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.4186673876
Short name T356
Test name
Test status
Simulation time 35471917267 ps
CPU time 385.85 seconds
Started Jan 10 01:26:01 PM PST 24
Finished Jan 10 01:32:43 PM PST 24
Peak memory 202180 kb
Host smart-2f993c3a-2383-4606-8559-b9d396f063e5
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186673876 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 2.sram_ctrl_partial_access_b2b.4186673876
Directory /workspace/2.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/2.sram_ctrl_ram_cfg.2379712164
Short name T383
Test name
Test status
Simulation time 343085654 ps
CPU time 5.45 seconds
Started Jan 10 01:26:08 PM PST 24
Finished Jan 10 01:26:36 PM PST 24
Peak memory 202296 kb
Host smart-12d56b88-d531-421c-ad36-b0441d5f0134
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379712164 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.2379712164
Directory /workspace/2.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/2.sram_ctrl_regwen.3006496401
Short name T687
Test name
Test status
Simulation time 20033182772 ps
CPU time 487.07 seconds
Started Jan 10 01:26:06 PM PST 24
Finished Jan 10 01:34:34 PM PST 24
Peak memory 375988 kb
Host smart-6025879a-342e-459a-a21b-6075e7ad42c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006496401 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.3006496401
Directory /workspace/2.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/2.sram_ctrl_sec_cm.2823965608
Short name T35
Test name
Test status
Simulation time 566132329 ps
CPU time 3.14 seconds
Started Jan 10 01:26:08 PM PST 24
Finished Jan 10 01:26:34 PM PST 24
Peak memory 220764 kb
Host smart-4d77ba44-f65b-41d1-8134-343fb0fe4f68
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823965608 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.sram_ctrl_sec_cm.2823965608
Directory /workspace/2.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.sram_ctrl_smoke.1669359524
Short name T817
Test name
Test status
Simulation time 361704153 ps
CPU time 6.83 seconds
Started Jan 10 01:26:07 PM PST 24
Finished Jan 10 01:26:36 PM PST 24
Peak memory 202084 kb
Host smart-34a13ab5-8f0c-4a8d-b5d0-8f00fa0c4bd8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669359524 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.1669359524
Directory /workspace/2.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/2.sram_ctrl_stress_all.1981561586
Short name T899
Test name
Test status
Simulation time 134615025507 ps
CPU time 3727.5 seconds
Started Jan 10 01:25:56 PM PST 24
Finished Jan 10 02:28:19 PM PST 24
Peak memory 382240 kb
Host smart-1e05f084-0b98-4585-bcd7-a9458195a609
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981561586 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 2.sram_ctrl_stress_all.1981561586
Directory /workspace/2.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.1110403294
Short name T667
Test name
Test status
Simulation time 1843859495 ps
CPU time 2748.47 seconds
Started Jan 10 01:26:01 PM PST 24
Finished Jan 10 02:12:06 PM PST 24
Peak memory 448844 kb
Host smart-07f5f8d8-3a33-4789-8cc6-fa2dca3b0659
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1110403294 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all_with_rand_reset.1110403294
Directory /workspace/2.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.sram_ctrl_stress_pipeline.3961408356
Short name T571
Test name
Test status
Simulation time 6001983577 ps
CPU time 438.85 seconds
Started Jan 10 01:25:55 PM PST 24
Finished Jan 10 01:33:30 PM PST 24
Peak memory 202208 kb
Host smart-395e23a6-cab4-4f3b-9a94-24292f394460
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961408356 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.sram_ctrl_stress_pipeline.3961408356
Directory /workspace/2.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.3859615472
Short name T653
Test name
Test status
Simulation time 1542981925 ps
CPU time 80.97 seconds
Started Jan 10 01:26:06 PM PST 24
Finished Jan 10 01:27:48 PM PST 24
Peak memory 330900 kb
Host smart-b8a4ba5c-1ab2-4b1f-831d-747eec5ae32d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859615472 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.sram_ctrl_throughput_w_partial_write.3859615472
Directory /workspace/2.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/20.sram_ctrl_access_during_key_req.3544754105
Short name T851
Test name
Test status
Simulation time 17818734083 ps
CPU time 1038.41 seconds
Started Jan 10 01:26:50 PM PST 24
Finished Jan 10 01:44:22 PM PST 24
Peak memory 379252 kb
Host smart-5858b7ce-7690-43d9-b92f-54d7699fb51b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544754105 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.sram_ctrl_access_during_key_req.3544754105
Directory /workspace/20.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/20.sram_ctrl_alert_test.1633794619
Short name T745
Test name
Test status
Simulation time 15625828 ps
CPU time 0.69 seconds
Started Jan 10 01:27:10 PM PST 24
Finished Jan 10 01:27:16 PM PST 24
Peak memory 200808 kb
Host smart-92f09fa8-159f-4dd8-9883-e329ef516206
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633794619 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.sram_ctrl_alert_test.1633794619
Directory /workspace/20.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.sram_ctrl_bijection.795056111
Short name T219
Test name
Test status
Simulation time 50580029854 ps
CPU time 821.44 seconds
Started Jan 10 01:27:00 PM PST 24
Finished Jan 10 01:40:54 PM PST 24
Peak memory 202120 kb
Host smart-80760526-f5ea-48e1-992f-ba80ad86f3c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795056111 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection.
795056111
Directory /workspace/20.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/20.sram_ctrl_lc_escalation.2827475718
Short name T850
Test name
Test status
Simulation time 39877468648 ps
CPU time 124.16 seconds
Started Jan 10 01:27:09 PM PST 24
Finished Jan 10 01:29:20 PM PST 24
Peak memory 202192 kb
Host smart-76248e17-a2db-4b77-8ab3-67ab958f2800
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827475718 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_lc_es
calation.2827475718
Directory /workspace/20.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/20.sram_ctrl_max_throughput.1424384424
Short name T501
Test name
Test status
Simulation time 1373322931 ps
CPU time 31.95 seconds
Started Jan 10 01:27:01 PM PST 24
Finished Jan 10 01:27:45 PM PST 24
Peak memory 234812 kb
Host smart-3f041033-3e91-49bc-b5ed-226ae3c60eba
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424384424 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 20.sram_ctrl_max_throughput.1424384424
Directory /workspace/20.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/20.sram_ctrl_mem_partial_access.615743749
Short name T420
Test name
Test status
Simulation time 10158715681 ps
CPU time 147.43 seconds
Started Jan 10 01:27:01 PM PST 24
Finished Jan 10 01:29:40 PM PST 24
Peak memory 210540 kb
Host smart-2c0e2162-5d7c-4a9c-be73-93d6616c5948
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615743749 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.sram_ctrl_mem_partial_access.615743749
Directory /workspace/20.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/20.sram_ctrl_mem_walk.3739684722
Short name T496
Test name
Test status
Simulation time 30313352663 ps
CPU time 259.18 seconds
Started Jan 10 01:27:11 PM PST 24
Finished Jan 10 01:31:35 PM PST 24
Peak memory 202416 kb
Host smart-45adf5ce-372f-4483-8d2b-2be20394b657
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739684722 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctr
l_mem_walk.3739684722
Directory /workspace/20.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/20.sram_ctrl_multiple_keys.4002076657
Short name T754
Test name
Test status
Simulation time 42652346129 ps
CPU time 975.82 seconds
Started Jan 10 01:26:56 PM PST 24
Finished Jan 10 01:43:23 PM PST 24
Peak memory 379072 kb
Host smart-ab45663d-63d3-4fb7-9bf0-7c121e5d6e21
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002076657 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multi
ple_keys.4002076657
Directory /workspace/20.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/20.sram_ctrl_partial_access.1920895337
Short name T803
Test name
Test status
Simulation time 1798319062 ps
CPU time 127.54 seconds
Started Jan 10 01:26:53 PM PST 24
Finished Jan 10 01:29:12 PM PST 24
Peak memory 367752 kb
Host smart-281bca90-ef22-414d-9abc-6bad91d7d5ad
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920895337 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
sram_ctrl_partial_access.1920895337
Directory /workspace/20.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/20.sram_ctrl_partial_access_b2b.1268557316
Short name T274
Test name
Test status
Simulation time 8403055251 ps
CPU time 197.31 seconds
Started Jan 10 01:26:58 PM PST 24
Finished Jan 10 01:30:27 PM PST 24
Peak memory 202088 kb
Host smart-d2895d57-a7c1-4e49-978a-e1f4b7289674
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268557316 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 20.sram_ctrl_partial_access_b2b.1268557316
Directory /workspace/20.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/20.sram_ctrl_ram_cfg.135582413
Short name T699
Test name
Test status
Simulation time 729803183 ps
CPU time 6.68 seconds
Started Jan 10 01:26:59 PM PST 24
Finished Jan 10 01:27:18 PM PST 24
Peak memory 202340 kb
Host smart-4c498f9d-5860-4133-9a26-a32f3047d564
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135582413 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.135582413
Directory /workspace/20.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/20.sram_ctrl_regwen.925768766
Short name T855
Test name
Test status
Simulation time 8425855389 ps
CPU time 526.61 seconds
Started Jan 10 01:26:57 PM PST 24
Finished Jan 10 01:35:56 PM PST 24
Peak memory 380016 kb
Host smart-f0758485-aa05-40b5-87dd-dbd372d70bb2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925768766 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.925768766
Directory /workspace/20.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/20.sram_ctrl_smoke.3990595492
Short name T520
Test name
Test status
Simulation time 4076932065 ps
CPU time 102.5 seconds
Started Jan 10 01:27:00 PM PST 24
Finished Jan 10 01:28:55 PM PST 24
Peak memory 353428 kb
Host smart-0fbce1ac-d1de-4c22-a590-89f20b4a44df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990595492 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.3990595492
Directory /workspace/20.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/20.sram_ctrl_stress_all.3533251171
Short name T363
Test name
Test status
Simulation time 286896872109 ps
CPU time 3746.02 seconds
Started Jan 10 01:26:57 PM PST 24
Finished Jan 10 02:29:36 PM PST 24
Peak memory 378104 kb
Host smart-ba66ca2b-0721-48fc-9b8e-b7e20073a677
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533251171 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 20.sram_ctrl_stress_all.3533251171
Directory /workspace/20.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.653734219
Short name T222
Test name
Test status
Simulation time 636805997 ps
CPU time 4125.5 seconds
Started Jan 10 01:26:59 PM PST 24
Finished Jan 10 02:35:57 PM PST 24
Peak memory 734468 kb
Host smart-ab7a7daf-55c5-4250-a171-1e1638c3f77b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=653734219 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all_with_rand_reset.653734219
Directory /workspace/20.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.sram_ctrl_stress_pipeline.1172420620
Short name T824
Test name
Test status
Simulation time 38012642603 ps
CPU time 168.6 seconds
Started Jan 10 01:26:56 PM PST 24
Finished Jan 10 01:29:57 PM PST 24
Peak memory 202100 kb
Host smart-260a16f0-771b-49d8-8057-ea4effa10dca
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172420620 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.sram_ctrl_stress_pipeline.1172420620
Directory /workspace/20.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.3838702128
Short name T503
Test name
Test status
Simulation time 750684887 ps
CPU time 76.4 seconds
Started Jan 10 01:27:00 PM PST 24
Finished Jan 10 01:28:28 PM PST 24
Peak memory 319648 kb
Host smart-bea64d43-1b4d-43d0-8811-70c77dfb1d0d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838702128 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 20.sram_ctrl_throughput_w_partial_write.3838702128
Directory /workspace/20.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/21.sram_ctrl_access_during_key_req.4222487003
Short name T861
Test name
Test status
Simulation time 4117484700 ps
CPU time 151.53 seconds
Started Jan 10 01:27:01 PM PST 24
Finished Jan 10 01:29:44 PM PST 24
Peak memory 364704 kb
Host smart-3584a150-6828-4c2c-9b73-fc2fcf6fcd65
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222487003 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.sram_ctrl_access_during_key_req.4222487003
Directory /workspace/21.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/21.sram_ctrl_alert_test.3495841024
Short name T371
Test name
Test status
Simulation time 13681449 ps
CPU time 0.65 seconds
Started Jan 10 01:26:59 PM PST 24
Finished Jan 10 01:27:12 PM PST 24
Peak memory 201908 kb
Host smart-04e5a7ed-1de4-48f6-9a23-1263e03aa352
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495841024 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.sram_ctrl_alert_test.3495841024
Directory /workspace/21.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.sram_ctrl_bijection.1329367118
Short name T739
Test name
Test status
Simulation time 25197815921 ps
CPU time 1671.81 seconds
Started Jan 10 01:26:57 PM PST 24
Finished Jan 10 01:55:01 PM PST 24
Peak memory 202216 kb
Host smart-d524355b-864d-49c5-90b8-50bfe6538773
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329367118 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection
.1329367118
Directory /workspace/21.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/21.sram_ctrl_executable.3833774072
Short name T116
Test name
Test status
Simulation time 4059756589 ps
CPU time 194.78 seconds
Started Jan 10 01:26:59 PM PST 24
Finished Jan 10 01:30:26 PM PST 24
Peak memory 299240 kb
Host smart-2daab3f2-fffe-47ba-9c10-08d7be6dbf66
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833774072 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_executab
le.3833774072
Directory /workspace/21.sram_ctrl_executable/latest

Test location /workspace/coverage/default/21.sram_ctrl_lc_escalation.2685751780
Short name T778
Test name
Test status
Simulation time 19414848433 ps
CPU time 323.9 seconds
Started Jan 10 01:27:10 PM PST 24
Finished Jan 10 01:32:40 PM PST 24
Peak memory 213560 kb
Host smart-e183f478-da47-47d9-ac42-3576693e317e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685751780 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_lc_es
calation.2685751780
Directory /workspace/21.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/21.sram_ctrl_max_throughput.4179963691
Short name T664
Test name
Test status
Simulation time 2945891738 ps
CPU time 45.83 seconds
Started Jan 10 01:26:59 PM PST 24
Finished Jan 10 01:27:57 PM PST 24
Peak memory 273492 kb
Host smart-44be433f-3670-4887-a1b9-d69fbeae1758
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179963691 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 21.sram_ctrl_max_throughput.4179963691
Directory /workspace/21.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/21.sram_ctrl_mem_partial_access.2464067506
Short name T755
Test name
Test status
Simulation time 3519120713 ps
CPU time 70.94 seconds
Started Jan 10 01:26:58 PM PST 24
Finished Jan 10 01:28:21 PM PST 24
Peak memory 211144 kb
Host smart-62934a1a-f2a5-40b4-b5eb-8f3abcd378b8
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464067506 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.sram_ctrl_mem_partial_access.2464067506
Directory /workspace/21.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/21.sram_ctrl_mem_walk.841995586
Short name T289
Test name
Test status
Simulation time 35829400208 ps
CPU time 251.55 seconds
Started Jan 10 01:27:01 PM PST 24
Finished Jan 10 01:31:24 PM PST 24
Peak memory 202140 kb
Host smart-d0ede7a3-4683-4b01-987a-1e3c1f65a738
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841995586 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl
_mem_walk.841995586
Directory /workspace/21.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/21.sram_ctrl_multiple_keys.934207460
Short name T764
Test name
Test status
Simulation time 164271888892 ps
CPU time 992.44 seconds
Started Jan 10 01:27:01 PM PST 24
Finished Jan 10 01:43:45 PM PST 24
Peak memory 379012 kb
Host smart-214f0f76-4de5-48cf-814e-debe4b5b764f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934207460 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multip
le_keys.934207460
Directory /workspace/21.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/21.sram_ctrl_partial_access.2719012708
Short name T380
Test name
Test status
Simulation time 355812190 ps
CPU time 6.86 seconds
Started Jan 10 01:26:58 PM PST 24
Finished Jan 10 01:27:17 PM PST 24
Peak memory 202064 kb
Host smart-99fdcafe-2aa3-4417-8f1a-bf1cb7948a3a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719012708 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
sram_ctrl_partial_access.2719012708
Directory /workspace/21.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.1155324524
Short name T244
Test name
Test status
Simulation time 22070779654 ps
CPU time 345.04 seconds
Started Jan 10 01:26:56 PM PST 24
Finished Jan 10 01:32:53 PM PST 24
Peak memory 202104 kb
Host smart-1676c7b4-6a49-4b90-ab92-466bb461f696
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155324524 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 21.sram_ctrl_partial_access_b2b.1155324524
Directory /workspace/21.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/21.sram_ctrl_ram_cfg.3462375127
Short name T456
Test name
Test status
Simulation time 1301522967 ps
CPU time 12.84 seconds
Started Jan 10 01:26:57 PM PST 24
Finished Jan 10 01:27:22 PM PST 24
Peak memory 202436 kb
Host smart-e08dd9f4-fb63-41e9-84cf-424e2aea11ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462375127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.3462375127
Directory /workspace/21.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/21.sram_ctrl_regwen.2707926981
Short name T369
Test name
Test status
Simulation time 11951187772 ps
CPU time 520.29 seconds
Started Jan 10 01:27:01 PM PST 24
Finished Jan 10 01:35:53 PM PST 24
Peak memory 365732 kb
Host smart-2c2ba42b-fb68-4f7f-9375-5271353bcb6d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707926981 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.2707926981
Directory /workspace/21.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/21.sram_ctrl_smoke.3371078670
Short name T473
Test name
Test status
Simulation time 5550170768 ps
CPU time 47.16 seconds
Started Jan 10 01:27:10 PM PST 24
Finished Jan 10 01:28:03 PM PST 24
Peak memory 293136 kb
Host smart-d8919418-5617-45c4-88dd-cd03a628cc32
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371078670 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.3371078670
Directory /workspace/21.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.1836649019
Short name T636
Test name
Test status
Simulation time 3440192619 ps
CPU time 3790.96 seconds
Started Jan 10 01:26:58 PM PST 24
Finished Jan 10 02:30:22 PM PST 24
Peak memory 632260 kb
Host smart-9e78525e-a559-459f-9cba-44205b5a4451
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1836649019 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all_with_rand_reset.1836649019
Directory /workspace/21.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.sram_ctrl_stress_pipeline.2374090848
Short name T515
Test name
Test status
Simulation time 3168022235 ps
CPU time 245.98 seconds
Started Jan 10 01:26:57 PM PST 24
Finished Jan 10 01:31:15 PM PST 24
Peak memory 202116 kb
Host smart-2589b9f7-d2d1-49d8-a2af-410ded2f4cda
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374090848 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.sram_ctrl_stress_pipeline.2374090848
Directory /workspace/21.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.4043235417
Short name T623
Test name
Test status
Simulation time 5635875267 ps
CPU time 30.57 seconds
Started Jan 10 01:26:57 PM PST 24
Finished Jan 10 01:27:40 PM PST 24
Peak memory 219588 kb
Host smart-332c4c57-6d86-4ec8-8409-caf3431c1a08
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043235417 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.sram_ctrl_throughput_w_partial_write.4043235417
Directory /workspace/21.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/22.sram_ctrl_access_during_key_req.3038539576
Short name T405
Test name
Test status
Simulation time 2352678445 ps
CPU time 356.07 seconds
Started Jan 10 01:27:03 PM PST 24
Finished Jan 10 01:33:10 PM PST 24
Peak memory 370788 kb
Host smart-7671b8ec-675b-40fb-be43-500a4df1e0e0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038539576 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.sram_ctrl_access_during_key_req.3038539576
Directory /workspace/22.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/22.sram_ctrl_alert_test.328216909
Short name T882
Test name
Test status
Simulation time 19768354 ps
CPU time 0.63 seconds
Started Jan 10 01:27:04 PM PST 24
Finished Jan 10 01:27:15 PM PST 24
Peak memory 201868 kb
Host smart-dcec12ca-0ff9-4b49-9961-abb85f8b2890
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328216909 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.sram_ctrl_alert_test.328216909
Directory /workspace/22.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.sram_ctrl_bijection.2770147905
Short name T771
Test name
Test status
Simulation time 316808033230 ps
CPU time 1219.33 seconds
Started Jan 10 01:26:55 PM PST 24
Finished Jan 10 01:47:26 PM PST 24
Peak memory 202168 kb
Host smart-32450777-5f3d-4271-b3ff-ac24ecd238e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770147905 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection
.2770147905
Directory /workspace/22.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/22.sram_ctrl_max_throughput.3503128212
Short name T621
Test name
Test status
Simulation time 3183040160 ps
CPU time 149.79 seconds
Started Jan 10 01:27:02 PM PST 24
Finished Jan 10 01:29:43 PM PST 24
Peak memory 365824 kb
Host smart-f2722885-927a-440b-a630-c2fd0f2e8baf
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503128212 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 22.sram_ctrl_max_throughput.3503128212
Directory /workspace/22.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/22.sram_ctrl_mem_partial_access.397585035
Short name T892
Test name
Test status
Simulation time 3142332549 ps
CPU time 134.81 seconds
Started Jan 10 01:27:05 PM PST 24
Finished Jan 10 01:29:29 PM PST 24
Peak memory 218540 kb
Host smart-bf18f80c-e8a9-4a69-a8a5-d75928c05ba0
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397585035 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.sram_ctrl_mem_partial_access.397585035
Directory /workspace/22.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/22.sram_ctrl_mem_walk.311161680
Short name T961
Test name
Test status
Simulation time 8231858572 ps
CPU time 123.75 seconds
Started Jan 10 01:26:55 PM PST 24
Finished Jan 10 01:29:10 PM PST 24
Peak memory 202216 kb
Host smart-ab2e9eb0-de5a-4f55-91e6-d94daa79c358
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311161680 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl
_mem_walk.311161680
Directory /workspace/22.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/22.sram_ctrl_multiple_keys.1461406747
Short name T840
Test name
Test status
Simulation time 37549790404 ps
CPU time 871.91 seconds
Started Jan 10 01:27:02 PM PST 24
Finished Jan 10 01:41:45 PM PST 24
Peak memory 372600 kb
Host smart-c6efecf1-1ac8-4716-a0f9-14512b5659e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461406747 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multi
ple_keys.1461406747
Directory /workspace/22.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/22.sram_ctrl_partial_access.453166010
Short name T885
Test name
Test status
Simulation time 535082838 ps
CPU time 9.1 seconds
Started Jan 10 01:26:55 PM PST 24
Finished Jan 10 01:27:15 PM PST 24
Peak memory 201960 kb
Host smart-aab47405-aa7c-4f88-89ba-83eaf8ac3205
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453166010 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.s
ram_ctrl_partial_access.453166010
Directory /workspace/22.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.1975318524
Short name T370
Test name
Test status
Simulation time 76234333932 ps
CPU time 473.72 seconds
Started Jan 10 01:26:56 PM PST 24
Finished Jan 10 01:35:01 PM PST 24
Peak memory 202060 kb
Host smart-5f82dd89-be70-4c4c-859d-446754c0420a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975318524 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 22.sram_ctrl_partial_access_b2b.1975318524
Directory /workspace/22.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/22.sram_ctrl_ram_cfg.975192401
Short name T735
Test name
Test status
Simulation time 1401394428 ps
CPU time 13.6 seconds
Started Jan 10 01:27:05 PM PST 24
Finished Jan 10 01:27:28 PM PST 24
Peak memory 202452 kb
Host smart-18feb62a-95c0-4473-8b49-33730b705e6d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975192401 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.975192401
Directory /workspace/22.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/22.sram_ctrl_regwen.4116015732
Short name T716
Test name
Test status
Simulation time 3759748440 ps
CPU time 631.34 seconds
Started Jan 10 01:27:17 PM PST 24
Finished Jan 10 01:37:50 PM PST 24
Peak memory 377152 kb
Host smart-c7f45ebb-ca54-46bf-901b-6adf1b6b5d4e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116015732 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.4116015732
Directory /workspace/22.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/22.sram_ctrl_smoke.2587492367
Short name T637
Test name
Test status
Simulation time 1162195412 ps
CPU time 25.48 seconds
Started Jan 10 01:27:00 PM PST 24
Finished Jan 10 01:27:38 PM PST 24
Peak memory 202028 kb
Host smart-d44edfea-c93d-4853-9830-743ef12afd05
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587492367 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.2587492367
Directory /workspace/22.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.3809831504
Short name T553
Test name
Test status
Simulation time 1687668475 ps
CPU time 3863.45 seconds
Started Jan 10 01:27:02 PM PST 24
Finished Jan 10 02:31:38 PM PST 24
Peak memory 633176 kb
Host smart-9ef9573e-827c-4313-b237-9fb549445b13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3809831504 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all_with_rand_reset.3809831504
Directory /workspace/22.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.sram_ctrl_stress_pipeline.1293246864
Short name T666
Test name
Test status
Simulation time 47258399055 ps
CPU time 291.22 seconds
Started Jan 10 01:27:01 PM PST 24
Finished Jan 10 01:32:04 PM PST 24
Peak memory 202180 kb
Host smart-201ab2d5-cf96-4cfa-803a-e4ec02aed10b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293246864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.sram_ctrl_stress_pipeline.1293246864
Directory /workspace/22.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.3257247073
Short name T453
Test name
Test status
Simulation time 5279529717 ps
CPU time 70.24 seconds
Started Jan 10 01:26:58 PM PST 24
Finished Jan 10 01:28:21 PM PST 24
Peak memory 307756 kb
Host smart-6fa49a11-865d-41aa-8597-97a0c77b8726
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257247073 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 22.sram_ctrl_throughput_w_partial_write.3257247073
Directory /workspace/22.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/23.sram_ctrl_access_during_key_req.369690947
Short name T270
Test name
Test status
Simulation time 3418668867 ps
CPU time 478.66 seconds
Started Jan 10 01:26:59 PM PST 24
Finished Jan 10 01:35:10 PM PST 24
Peak memory 376728 kb
Host smart-dd0d342a-022b-4426-ba59-327a7a2192d3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369690947 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 23.sram_ctrl_access_during_key_req.369690947
Directory /workspace/23.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/23.sram_ctrl_alert_test.1108965292
Short name T400
Test name
Test status
Simulation time 16624871 ps
CPU time 0.67 seconds
Started Jan 10 01:27:07 PM PST 24
Finished Jan 10 01:27:16 PM PST 24
Peak memory 201700 kb
Host smart-3633635e-d54b-4e40-9fea-46bdf728b736
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108965292 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.sram_ctrl_alert_test.1108965292
Directory /workspace/23.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.sram_ctrl_bijection.565059350
Short name T406
Test name
Test status
Simulation time 18225874917 ps
CPU time 1032.1 seconds
Started Jan 10 01:27:16 PM PST 24
Finished Jan 10 01:44:30 PM PST 24
Peak memory 201044 kb
Host smart-fa3b8347-1f2a-45c3-8484-763b624dbf4f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565059350 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection.
565059350
Directory /workspace/23.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/23.sram_ctrl_lc_escalation.2576298135
Short name T634
Test name
Test status
Simulation time 18768892422 ps
CPU time 94.63 seconds
Started Jan 10 01:27:03 PM PST 24
Finished Jan 10 01:28:48 PM PST 24
Peak memory 210360 kb
Host smart-56a7e3a1-cf75-4222-830d-3ab4cc6311e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576298135 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_lc_es
calation.2576298135
Directory /workspace/23.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/23.sram_ctrl_max_throughput.1934549111
Short name T214
Test name
Test status
Simulation time 2902504204 ps
CPU time 110.41 seconds
Started Jan 10 01:26:58 PM PST 24
Finished Jan 10 01:29:00 PM PST 24
Peak memory 356532 kb
Host smart-3db47ef1-4698-45d1-bec4-f74bf0fac2d4
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934549111 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 23.sram_ctrl_max_throughput.1934549111
Directory /workspace/23.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/23.sram_ctrl_mem_partial_access.1613137867
Short name T845
Test name
Test status
Simulation time 5941665525 ps
CPU time 144.58 seconds
Started Jan 10 01:27:10 PM PST 24
Finished Jan 10 01:29:40 PM PST 24
Peak memory 214392 kb
Host smart-14e33193-d162-4792-a9a6-3f9aaaeeae82
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613137867 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.sram_ctrl_mem_partial_access.1613137867
Directory /workspace/23.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/23.sram_ctrl_mem_walk.1608350102
Short name T894
Test name
Test status
Simulation time 13933963104 ps
CPU time 264.83 seconds
Started Jan 10 01:26:58 PM PST 24
Finished Jan 10 01:31:36 PM PST 24
Peak memory 202240 kb
Host smart-80332f62-0826-4671-8fea-53cef8518b8b
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608350102 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctr
l_mem_walk.1608350102
Directory /workspace/23.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/23.sram_ctrl_multiple_keys.2328556777
Short name T324
Test name
Test status
Simulation time 28356550308 ps
CPU time 942.66 seconds
Started Jan 10 01:27:16 PM PST 24
Finished Jan 10 01:43:01 PM PST 24
Peak memory 375000 kb
Host smart-e2c05c6f-af90-40c2-a4da-18d8894296f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328556777 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multi
ple_keys.2328556777
Directory /workspace/23.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/23.sram_ctrl_partial_access.4287342958
Short name T796
Test name
Test status
Simulation time 1043047646 ps
CPU time 46.02 seconds
Started Jan 10 01:26:58 PM PST 24
Finished Jan 10 01:27:56 PM PST 24
Peak memory 293436 kb
Host smart-8e37dc52-6743-4eac-a53a-27dbecade09e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287342958 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
sram_ctrl_partial_access.4287342958
Directory /workspace/23.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.3153712750
Short name T307
Test name
Test status
Simulation time 16027969240 ps
CPU time 328.94 seconds
Started Jan 10 01:27:07 PM PST 24
Finished Jan 10 01:32:44 PM PST 24
Peak memory 202160 kb
Host smart-f2eaec63-b9fc-464e-8943-23eddb324eac
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153712750 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 23.sram_ctrl_partial_access_b2b.3153712750
Directory /workspace/23.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/23.sram_ctrl_ram_cfg.4249875050
Short name T242
Test name
Test status
Simulation time 1684974616 ps
CPU time 14.75 seconds
Started Jan 10 01:26:58 PM PST 24
Finished Jan 10 01:27:24 PM PST 24
Peak memory 202468 kb
Host smart-c1372491-0804-4f8e-ad87-adfe113b3b43
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249875050 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.4249875050
Directory /workspace/23.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/23.sram_ctrl_regwen.2967930115
Short name T926
Test name
Test status
Simulation time 8767243696 ps
CPU time 799.29 seconds
Started Jan 10 01:27:07 PM PST 24
Finished Jan 10 01:40:34 PM PST 24
Peak memory 376000 kb
Host smart-9537bcfa-955d-46df-8964-96d67392dd41
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967930115 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.2967930115
Directory /workspace/23.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/23.sram_ctrl_smoke.4199894483
Short name T617
Test name
Test status
Simulation time 1232036739 ps
CPU time 30.18 seconds
Started Jan 10 01:27:16 PM PST 24
Finished Jan 10 01:27:48 PM PST 24
Peak memory 201952 kb
Host smart-26615d8b-04c1-40a6-be3e-c95b927eebba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199894483 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.4199894483
Directory /workspace/23.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/23.sram_ctrl_stress_all.4007382960
Short name T272
Test name
Test status
Simulation time 79297829325 ps
CPU time 1270.3 seconds
Started Jan 10 01:26:57 PM PST 24
Finished Jan 10 01:48:20 PM PST 24
Peak memory 379008 kb
Host smart-4f12ff54-622d-4572-905c-82d5dbf7ff62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007382960 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 23.sram_ctrl_stress_all.4007382960
Directory /workspace/23.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.4054349313
Short name T582
Test name
Test status
Simulation time 1399039841 ps
CPU time 3021.95 seconds
Started Jan 10 01:26:54 PM PST 24
Finished Jan 10 02:17:28 PM PST 24
Peak memory 619556 kb
Host smart-60188398-cf6e-42c4-a64c-051f691c395d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4054349313 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all_with_rand_reset.4054349313
Directory /workspace/23.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.sram_ctrl_stress_pipeline.2721031008
Short name T887
Test name
Test status
Simulation time 43177682955 ps
CPU time 267.88 seconds
Started Jan 10 01:27:16 PM PST 24
Finished Jan 10 01:31:46 PM PST 24
Peak memory 201228 kb
Host smart-28fe03ca-9710-4ec1-b79b-ebbcaa1b95f9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721031008 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.sram_ctrl_stress_pipeline.2721031008
Directory /workspace/23.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.3718874003
Short name T525
Test name
Test status
Simulation time 1488874689 ps
CPU time 73.38 seconds
Started Jan 10 01:26:58 PM PST 24
Finished Jan 10 01:28:24 PM PST 24
Peak memory 315472 kb
Host smart-1e745931-c8ed-45e5-aa2b-9b447734d209
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718874003 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 23.sram_ctrl_throughput_w_partial_write.3718874003
Directory /workspace/23.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/24.sram_ctrl_access_during_key_req.3410271771
Short name T415
Test name
Test status
Simulation time 8897614500 ps
CPU time 1237.22 seconds
Started Jan 10 01:26:59 PM PST 24
Finished Jan 10 01:47:48 PM PST 24
Peak memory 380120 kb
Host smart-b9976ad5-b233-4f9c-8347-2e25e51fa311
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410271771 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 24.sram_ctrl_access_during_key_req.3410271771
Directory /workspace/24.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/24.sram_ctrl_alert_test.853998206
Short name T22
Test name
Test status
Simulation time 14914985 ps
CPU time 0.66 seconds
Started Jan 10 01:26:57 PM PST 24
Finished Jan 10 01:27:10 PM PST 24
Peak memory 201868 kb
Host smart-75fe42d5-58c7-4163-a5ca-8e121199aa93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853998206 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.sram_ctrl_alert_test.853998206
Directory /workspace/24.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.sram_ctrl_bijection.914032140
Short name T340
Test name
Test status
Simulation time 99865781843 ps
CPU time 1570.19 seconds
Started Jan 10 01:26:56 PM PST 24
Finished Jan 10 01:53:18 PM PST 24
Peak memory 210372 kb
Host smart-8333a976-65f3-4678-b27e-bcd10930c1fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914032140 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection.
914032140
Directory /workspace/24.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/24.sram_ctrl_lc_escalation.2759160510
Short name T668
Test name
Test status
Simulation time 13738614210 ps
CPU time 63.96 seconds
Started Jan 10 01:27:00 PM PST 24
Finished Jan 10 01:28:16 PM PST 24
Peak memory 202180 kb
Host smart-5d140eb4-a4b3-48d8-9162-9d6f7ae4a202
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759160510 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_lc_es
calation.2759160510
Directory /workspace/24.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/24.sram_ctrl_max_throughput.2359718999
Short name T368
Test name
Test status
Simulation time 748555293 ps
CPU time 46.85 seconds
Started Jan 10 01:27:03 PM PST 24
Finished Jan 10 01:28:01 PM PST 24
Peak memory 271616 kb
Host smart-8ae88f67-bb82-41b4-b8c4-3cff5714b471
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359718999 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 24.sram_ctrl_max_throughput.2359718999
Directory /workspace/24.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/24.sram_ctrl_mem_partial_access.187712482
Short name T81
Test name
Test status
Simulation time 9068582159 ps
CPU time 145.66 seconds
Started Jan 10 01:27:03 PM PST 24
Finished Jan 10 01:29:39 PM PST 24
Peak memory 211212 kb
Host smart-586cbdad-21a5-4c17-8ad7-3059be3f4503
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187712482 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.sram_ctrl_mem_partial_access.187712482
Directory /workspace/24.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/24.sram_ctrl_mem_walk.1765788635
Short name T275
Test name
Test status
Simulation time 13151895749 ps
CPU time 124.27 seconds
Started Jan 10 01:26:59 PM PST 24
Finished Jan 10 01:29:15 PM PST 24
Peak memory 202240 kb
Host smart-0635fcbd-44f2-431e-bbfd-7d9e65c98265
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765788635 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctr
l_mem_walk.1765788635
Directory /workspace/24.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/24.sram_ctrl_multiple_keys.1741318674
Short name T327
Test name
Test status
Simulation time 4125091925 ps
CPU time 128.05 seconds
Started Jan 10 01:26:59 PM PST 24
Finished Jan 10 01:29:19 PM PST 24
Peak memory 339268 kb
Host smart-eba45b61-54c2-4b8a-b534-89b2635e4c2f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741318674 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multi
ple_keys.1741318674
Directory /workspace/24.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/24.sram_ctrl_partial_access.4240355024
Short name T7
Test name
Test status
Simulation time 1065193937 ps
CPU time 53.63 seconds
Started Jan 10 01:26:57 PM PST 24
Finished Jan 10 01:28:03 PM PST 24
Peak memory 302288 kb
Host smart-090cd780-404f-4d41-9e7f-6dffa8f6d97a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240355024 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
sram_ctrl_partial_access.4240355024
Directory /workspace/24.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.4135165431
Short name T429
Test name
Test status
Simulation time 10583254049 ps
CPU time 230.61 seconds
Started Jan 10 01:26:59 PM PST 24
Finished Jan 10 01:31:02 PM PST 24
Peak memory 202140 kb
Host smart-82f2ba3f-b0af-4d34-ba8d-7c1ddd081c9f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135165431 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 24.sram_ctrl_partial_access_b2b.4135165431
Directory /workspace/24.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/24.sram_ctrl_ram_cfg.561423262
Short name T418
Test name
Test status
Simulation time 2108165497 ps
CPU time 14.17 seconds
Started Jan 10 01:26:59 PM PST 24
Finished Jan 10 01:27:26 PM PST 24
Peak memory 202408 kb
Host smart-1feb0aab-214b-4a97-b79b-f80360c5327b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561423262 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.561423262
Directory /workspace/24.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/24.sram_ctrl_regwen.1192099547
Short name T384
Test name
Test status
Simulation time 28140096876 ps
CPU time 819.93 seconds
Started Jan 10 01:27:11 PM PST 24
Finished Jan 10 01:40:56 PM PST 24
Peak memory 377052 kb
Host smart-5aa64d26-2655-4185-8518-1099b821854f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192099547 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.1192099547
Directory /workspace/24.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/24.sram_ctrl_smoke.1144564001
Short name T858
Test name
Test status
Simulation time 380021060 ps
CPU time 26.7 seconds
Started Jan 10 01:27:00 PM PST 24
Finished Jan 10 01:27:39 PM PST 24
Peak memory 257224 kb
Host smart-04dc09cc-9b0f-4807-91f3-acebd91da62a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144564001 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.1144564001
Directory /workspace/24.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.4232287083
Short name T97
Test name
Test status
Simulation time 2135739885 ps
CPU time 4676.89 seconds
Started Jan 10 01:27:12 PM PST 24
Finished Jan 10 02:45:14 PM PST 24
Peak memory 696852 kb
Host smart-6afc0b06-f3f7-4fab-93e2-f44086a12e3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4232287083 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all_with_rand_reset.4232287083
Directory /workspace/24.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.sram_ctrl_stress_pipeline.1205886463
Short name T956
Test name
Test status
Simulation time 3818935092 ps
CPU time 288.65 seconds
Started Jan 10 01:26:58 PM PST 24
Finished Jan 10 01:31:59 PM PST 24
Peak memory 202192 kb
Host smart-a0215420-fb9a-48ed-9a10-2fcd3e1e33f9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205886463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.sram_ctrl_stress_pipeline.1205886463
Directory /workspace/24.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.3231426039
Short name T581
Test name
Test status
Simulation time 834131687 ps
CPU time 129.58 seconds
Started Jan 10 01:26:59 PM PST 24
Finished Jan 10 01:29:21 PM PST 24
Peak memory 374996 kb
Host smart-c6a80d13-0d8f-4d21-9656-a1a36faf8af6
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231426039 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 24.sram_ctrl_throughput_w_partial_write.3231426039
Directory /workspace/24.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/25.sram_ctrl_access_during_key_req.3553229765
Short name T734
Test name
Test status
Simulation time 26984300265 ps
CPU time 1062.25 seconds
Started Jan 10 01:27:04 PM PST 24
Finished Jan 10 01:44:57 PM PST 24
Peak memory 380192 kb
Host smart-a54032dd-ae99-4b2c-a6e7-68bdd9dd7305
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553229765 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.sram_ctrl_access_during_key_req.3553229765
Directory /workspace/25.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/25.sram_ctrl_alert_test.3663581357
Short name T846
Test name
Test status
Simulation time 20228527 ps
CPU time 0.68 seconds
Started Jan 10 01:27:07 PM PST 24
Finished Jan 10 01:27:16 PM PST 24
Peak memory 201204 kb
Host smart-8a1a733b-719b-4c49-9f64-3bc5cd1831a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663581357 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.sram_ctrl_alert_test.3663581357
Directory /workspace/25.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.sram_ctrl_bijection.3696344850
Short name T296
Test name
Test status
Simulation time 17666999236 ps
CPU time 1171.38 seconds
Started Jan 10 01:26:56 PM PST 24
Finished Jan 10 01:46:40 PM PST 24
Peak memory 202160 kb
Host smart-8669c2b8-1fe1-42ce-9966-4cc322d35807
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696344850 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection
.3696344850
Directory /workspace/25.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/25.sram_ctrl_executable.2888687693
Short name T446
Test name
Test status
Simulation time 34231875822 ps
CPU time 1662.79 seconds
Started Jan 10 01:27:16 PM PST 24
Finished Jan 10 01:55:01 PM PST 24
Peak memory 378136 kb
Host smart-ca8f1d10-f59d-4258-a3d0-1d02d602f14a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888687693 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_executab
le.2888687693
Directory /workspace/25.sram_ctrl_executable/latest

Test location /workspace/coverage/default/25.sram_ctrl_lc_escalation.2293417833
Short name T749
Test name
Test status
Simulation time 11207633424 ps
CPU time 104.67 seconds
Started Jan 10 01:27:04 PM PST 24
Finished Jan 10 01:28:59 PM PST 24
Peak memory 210420 kb
Host smart-e9d0d681-edcd-4db1-bdd2-bccc8bde915e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293417833 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_lc_es
calation.2293417833
Directory /workspace/25.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/25.sram_ctrl_max_throughput.3493801023
Short name T695
Test name
Test status
Simulation time 811334698 ps
CPU time 136.41 seconds
Started Jan 10 01:26:53 PM PST 24
Finished Jan 10 01:29:21 PM PST 24
Peak memory 372984 kb
Host smart-09859772-7b0a-458c-93b9-710eb877409c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493801023 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 25.sram_ctrl_max_throughput.3493801023
Directory /workspace/25.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/25.sram_ctrl_mem_partial_access.3312970463
Short name T82
Test name
Test status
Simulation time 9763892858 ps
CPU time 76.07 seconds
Started Jan 10 01:26:58 PM PST 24
Finished Jan 10 01:28:26 PM PST 24
Peak memory 211912 kb
Host smart-699e9506-5fe9-4ac8-9fb7-45d25a4cef35
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312970463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.sram_ctrl_mem_partial_access.3312970463
Directory /workspace/25.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/25.sram_ctrl_mem_walk.682394253
Short name T419
Test name
Test status
Simulation time 4036318870 ps
CPU time 117.9 seconds
Started Jan 10 01:27:16 PM PST 24
Finished Jan 10 01:29:16 PM PST 24
Peak memory 201404 kb
Host smart-73ce541a-5b56-427b-be08-a156b4eb84a2
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682394253 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl
_mem_walk.682394253
Directory /workspace/25.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/25.sram_ctrl_multiple_keys.3530557966
Short name T318
Test name
Test status
Simulation time 27640834181 ps
CPU time 1147.14 seconds
Started Jan 10 01:26:58 PM PST 24
Finished Jan 10 01:46:18 PM PST 24
Peak memory 380216 kb
Host smart-978cdfa1-148a-4d5b-b115-b4dede32014f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530557966 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multi
ple_keys.3530557966
Directory /workspace/25.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/25.sram_ctrl_partial_access.441314888
Short name T542
Test name
Test status
Simulation time 1181939284 ps
CPU time 22.06 seconds
Started Jan 10 01:26:56 PM PST 24
Finished Jan 10 01:27:31 PM PST 24
Peak memory 202092 kb
Host smart-88b92808-2144-440f-b56c-984f4b0a03af
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441314888 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.s
ram_ctrl_partial_access.441314888
Directory /workspace/25.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.2269247277
Short name T320
Test name
Test status
Simulation time 151539049590 ps
CPU time 656.38 seconds
Started Jan 10 01:27:08 PM PST 24
Finished Jan 10 01:38:12 PM PST 24
Peak memory 202244 kb
Host smart-89da9233-4919-4eb9-b704-3a9d9d530fe6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269247277 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 25.sram_ctrl_partial_access_b2b.2269247277
Directory /workspace/25.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/25.sram_ctrl_ram_cfg.154316946
Short name T439
Test name
Test status
Simulation time 1429601535 ps
CPU time 12.78 seconds
Started Jan 10 01:26:57 PM PST 24
Finished Jan 10 01:27:22 PM PST 24
Peak memory 202304 kb
Host smart-64aecd17-5685-4a07-9b93-ba9ee695a1af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154316946 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.154316946
Directory /workspace/25.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/25.sram_ctrl_regwen.4198478868
Short name T901
Test name
Test status
Simulation time 152211615816 ps
CPU time 932.28 seconds
Started Jan 10 01:27:01 PM PST 24
Finished Jan 10 01:42:46 PM PST 24
Peak memory 370916 kb
Host smart-fb876113-8983-4e7c-a8a9-33ee8b35da03
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198478868 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.4198478868
Directory /workspace/25.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/25.sram_ctrl_smoke.2909694959
Short name T656
Test name
Test status
Simulation time 490374336 ps
CPU time 17.32 seconds
Started Jan 10 01:27:02 PM PST 24
Finished Jan 10 01:27:31 PM PST 24
Peak memory 202036 kb
Host smart-299502cc-843b-4a01-9f23-bb743cf69864
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909694959 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.2909694959
Directory /workspace/25.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/25.sram_ctrl_stress_all.141549877
Short name T775
Test name
Test status
Simulation time 262596017577 ps
CPU time 2988.87 seconds
Started Jan 10 01:26:54 PM PST 24
Finished Jan 10 02:16:55 PM PST 24
Peak memory 377896 kb
Host smart-b0d0cc9c-d0aa-4760-90d5-933d770bd0d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141549877 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 25.sram_ctrl_stress_all.141549877
Directory /workspace/25.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.3204563655
Short name T250
Test name
Test status
Simulation time 1562197682 ps
CPU time 6231.74 seconds
Started Jan 10 01:27:16 PM PST 24
Finished Jan 10 03:11:11 PM PST 24
Peak memory 749412 kb
Host smart-01483ffe-4340-4807-8faf-291b3b20dd90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3204563655 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all_with_rand_reset.3204563655
Directory /workspace/25.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.sram_ctrl_stress_pipeline.2677224906
Short name T360
Test name
Test status
Simulation time 2834583958 ps
CPU time 201.47 seconds
Started Jan 10 01:27:00 PM PST 24
Finished Jan 10 01:30:34 PM PST 24
Peak memory 202256 kb
Host smart-2e973412-015a-471d-bf50-9eb9a1052483
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677224906 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.sram_ctrl_stress_pipeline.2677224906
Directory /workspace/25.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.4218877720
Short name T742
Test name
Test status
Simulation time 1460470184 ps
CPU time 36.6 seconds
Started Jan 10 01:26:54 PM PST 24
Finished Jan 10 01:27:43 PM PST 24
Peak memory 255504 kb
Host smart-823b52b2-92e7-4af0-b24b-8068028c8daf
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218877720 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 25.sram_ctrl_throughput_w_partial_write.4218877720
Directory /workspace/25.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/26.sram_ctrl_access_during_key_req.734243865
Short name T660
Test name
Test status
Simulation time 6920062477 ps
CPU time 760.96 seconds
Started Jan 10 01:27:34 PM PST 24
Finished Jan 10 01:40:44 PM PST 24
Peak memory 362836 kb
Host smart-971a0148-2933-45bb-adfc-5f429705cf00
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734243865 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 26.sram_ctrl_access_during_key_req.734243865
Directory /workspace/26.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/26.sram_ctrl_alert_test.1526216692
Short name T282
Test name
Test status
Simulation time 39255012 ps
CPU time 0.64 seconds
Started Jan 10 01:27:30 PM PST 24
Finished Jan 10 01:27:41 PM PST 24
Peak memory 201468 kb
Host smart-d4df4984-0c9f-420c-a26b-a8bd3f92206c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526216692 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.sram_ctrl_alert_test.1526216692
Directory /workspace/26.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.sram_ctrl_bijection.2828630231
Short name T681
Test name
Test status
Simulation time 117328276866 ps
CPU time 1934.85 seconds
Started Jan 10 01:26:57 PM PST 24
Finished Jan 10 01:59:25 PM PST 24
Peak memory 202112 kb
Host smart-03f99ecd-3f66-4860-82dc-2b35ab973ad7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828630231 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection
.2828630231
Directory /workspace/26.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/26.sram_ctrl_lc_escalation.3919033887
Short name T39
Test name
Test status
Simulation time 8839099408 ps
CPU time 203.52 seconds
Started Jan 10 01:27:31 PM PST 24
Finished Jan 10 01:31:06 PM PST 24
Peak memory 210416 kb
Host smart-ce07448d-5f58-4848-a18e-f3a9a0b48f3d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919033887 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_es
calation.3919033887
Directory /workspace/26.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/26.sram_ctrl_max_throughput.3585009657
Short name T262
Test name
Test status
Simulation time 733119427 ps
CPU time 40.12 seconds
Started Jan 10 01:27:41 PM PST 24
Finished Jan 10 01:28:50 PM PST 24
Peak memory 259984 kb
Host smart-88ed830c-ecec-46fe-9b19-f80b5717d0bb
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585009657 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 26.sram_ctrl_max_throughput.3585009657
Directory /workspace/26.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/26.sram_ctrl_mem_partial_access.1653343233
Short name T255
Test name
Test status
Simulation time 6442548138 ps
CPU time 133.55 seconds
Started Jan 10 01:27:25 PM PST 24
Finished Jan 10 01:29:40 PM PST 24
Peak memory 210272 kb
Host smart-85f4ae8b-46fc-48e2-bf14-b68b80c2649b
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653343233 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.sram_ctrl_mem_partial_access.1653343233
Directory /workspace/26.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/26.sram_ctrl_mem_walk.2169850899
Short name T586
Test name
Test status
Simulation time 229098327129 ps
CPU time 315.9 seconds
Started Jan 10 01:27:21 PM PST 24
Finished Jan 10 01:32:38 PM PST 24
Peak memory 202280 kb
Host smart-5bb9e379-697d-4953-be6b-570c3f8bdb4a
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169850899 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctr
l_mem_walk.2169850899
Directory /workspace/26.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/26.sram_ctrl_multiple_keys.2019851304
Short name T325
Test name
Test status
Simulation time 7818218289 ps
CPU time 837.31 seconds
Started Jan 10 01:27:16 PM PST 24
Finished Jan 10 01:41:16 PM PST 24
Peak memory 377916 kb
Host smart-51d02c67-4455-42ef-9c63-019806faef3d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019851304 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multi
ple_keys.2019851304
Directory /workspace/26.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/26.sram_ctrl_partial_access.1215186613
Short name T957
Test name
Test status
Simulation time 693940393 ps
CPU time 26.53 seconds
Started Jan 10 01:27:07 PM PST 24
Finished Jan 10 01:27:42 PM PST 24
Peak memory 202096 kb
Host smart-e5678c68-cb38-4df4-adf7-e3d319b5bb35
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215186613 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
sram_ctrl_partial_access.1215186613
Directory /workspace/26.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.528734836
Short name T685
Test name
Test status
Simulation time 36077567276 ps
CPU time 225.48 seconds
Started Jan 10 01:27:34 PM PST 24
Finished Jan 10 01:31:46 PM PST 24
Peak memory 202120 kb
Host smart-6812c277-c86c-4d60-ad42-0f79700196a3
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528734836 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.sram_ctrl_partial_access_b2b.528734836
Directory /workspace/26.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/26.sram_ctrl_ram_cfg.4214218745
Short name T366
Test name
Test status
Simulation time 1402580533 ps
CPU time 13.94 seconds
Started Jan 10 01:27:42 PM PST 24
Finished Jan 10 01:28:45 PM PST 24
Peak memory 202364 kb
Host smart-f85ead0e-498b-4eeb-b019-63eb5d826afa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214218745 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.4214218745
Directory /workspace/26.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/26.sram_ctrl_regwen.488480783
Short name T25
Test name
Test status
Simulation time 14808925740 ps
CPU time 194.95 seconds
Started Jan 10 01:27:20 PM PST 24
Finished Jan 10 01:30:36 PM PST 24
Peak memory 343976 kb
Host smart-707a7284-567c-4ebb-aa7d-c5b4606fbd57
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488480783 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.488480783
Directory /workspace/26.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/26.sram_ctrl_smoke.2123785776
Short name T486
Test name
Test status
Simulation time 814386660 ps
CPU time 35.96 seconds
Started Jan 10 01:27:16 PM PST 24
Finished Jan 10 01:27:54 PM PST 24
Peak memory 202008 kb
Host smart-f0af816b-e3a2-4be8-9c9c-d26b27c50e3d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123785776 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.2123785776
Directory /workspace/26.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.988181207
Short name T768
Test name
Test status
Simulation time 896360955 ps
CPU time 4631.33 seconds
Started Jan 10 01:27:25 PM PST 24
Finished Jan 10 02:44:39 PM PST 24
Peak memory 450928 kb
Host smart-8bd13302-9ef6-4d53-93e5-ce7b50907af6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=988181207 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all_with_rand_reset.988181207
Directory /workspace/26.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.sram_ctrl_stress_pipeline.1351924035
Short name T701
Test name
Test status
Simulation time 13414724745 ps
CPU time 177.77 seconds
Started Jan 10 01:26:57 PM PST 24
Finished Jan 10 01:30:07 PM PST 24
Peak memory 202152 kb
Host smart-8c52bcdb-d54a-4aa7-ab77-a9161e59c961
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351924035 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.sram_ctrl_stress_pipeline.1351924035
Directory /workspace/26.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.1227713189
Short name T774
Test name
Test status
Simulation time 816997306 ps
CPU time 113.34 seconds
Started Jan 10 01:27:45 PM PST 24
Finished Jan 10 01:30:44 PM PST 24
Peak memory 364692 kb
Host smart-32540047-ab4e-4cdc-97a7-3ab3af79770a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227713189 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 26.sram_ctrl_throughput_w_partial_write.1227713189
Directory /workspace/26.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/27.sram_ctrl_access_during_key_req.3457523967
Short name T888
Test name
Test status
Simulation time 53731903661 ps
CPU time 1701.74 seconds
Started Jan 10 01:28:13 PM PST 24
Finished Jan 10 01:57:26 PM PST 24
Peak memory 380024 kb
Host smart-6d5c8700-fc30-4447-a1ce-a3ebf387d241
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457523967 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 27.sram_ctrl_access_during_key_req.3457523967
Directory /workspace/27.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/27.sram_ctrl_alert_test.1447455122
Short name T212
Test name
Test status
Simulation time 99564229 ps
CPU time 0.64 seconds
Started Jan 10 01:28:15 PM PST 24
Finished Jan 10 01:29:11 PM PST 24
Peak memory 201848 kb
Host smart-a36f2bf4-24ca-403e-8afe-4d6e55962f3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447455122 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.sram_ctrl_alert_test.1447455122
Directory /workspace/27.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.sram_ctrl_bijection.1076457862
Short name T459
Test name
Test status
Simulation time 173771567455 ps
CPU time 654.18 seconds
Started Jan 10 01:27:30 PM PST 24
Finished Jan 10 01:38:35 PM PST 24
Peak memory 202180 kb
Host smart-fdfb663f-8848-4143-9427-e2ee460428cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076457862 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection
.1076457862
Directory /workspace/27.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/27.sram_ctrl_lc_escalation.1558182412
Short name T364
Test name
Test status
Simulation time 12809679801 ps
CPU time 113.43 seconds
Started Jan 10 01:27:58 PM PST 24
Finished Jan 10 01:30:49 PM PST 24
Peak memory 210416 kb
Host smart-ec8bdb75-0ed9-4108-92c7-d78294e31973
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558182412 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_lc_es
calation.1558182412
Directory /workspace/27.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/27.sram_ctrl_max_throughput.847684472
Short name T933
Test name
Test status
Simulation time 722205614 ps
CPU time 31.5 seconds
Started Jan 10 01:27:57 PM PST 24
Finished Jan 10 01:29:24 PM PST 24
Peak memory 234680 kb
Host smart-d9e7e163-a882-4556-be06-c98a0b505b14
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847684472 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.sram_ctrl_max_throughput.847684472
Directory /workspace/27.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/27.sram_ctrl_mem_partial_access.3579837468
Short name T493
Test name
Test status
Simulation time 992997648 ps
CPU time 73.89 seconds
Started Jan 10 01:28:17 PM PST 24
Finished Jan 10 01:30:21 PM PST 24
Peak memory 211204 kb
Host smart-ee5d0ddf-81b5-4268-bd53-7030bd40d072
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579837468 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.sram_ctrl_mem_partial_access.3579837468
Directory /workspace/27.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/27.sram_ctrl_mem_walk.2323530930
Short name T246
Test name
Test status
Simulation time 1998231635 ps
CPU time 121.74 seconds
Started Jan 10 01:27:45 PM PST 24
Finished Jan 10 01:30:53 PM PST 24
Peak memory 202052 kb
Host smart-106c4db3-5746-4368-8ba5-cf7da63edef3
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323530930 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctr
l_mem_walk.2323530930
Directory /workspace/27.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/27.sram_ctrl_multiple_keys.390358130
Short name T298
Test name
Test status
Simulation time 17820635361 ps
CPU time 406.3 seconds
Started Jan 10 01:27:56 PM PST 24
Finished Jan 10 01:35:41 PM PST 24
Peak memory 371904 kb
Host smart-b1a390c7-ec11-4c14-a3f0-8621d17c0d3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390358130 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multip
le_keys.390358130
Directory /workspace/27.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/27.sram_ctrl_partial_access.4908215
Short name T353
Test name
Test status
Simulation time 969046191 ps
CPU time 167.78 seconds
Started Jan 10 01:27:42 PM PST 24
Finished Jan 10 01:31:18 PM PST 24
Peak memory 370760 kb
Host smart-c71ee2f9-7b49-4c2b-b343-dfa9dc0aab6f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4908215 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sra
m_ctrl_partial_access.4908215
Directory /workspace/27.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.1284389762
Short name T806
Test name
Test status
Simulation time 52056382701 ps
CPU time 374.88 seconds
Started Jan 10 01:27:41 PM PST 24
Finished Jan 10 01:34:32 PM PST 24
Peak memory 202240 kb
Host smart-c502a355-b9f3-4fee-92d9-a27b4b59c42c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284389762 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 27.sram_ctrl_partial_access_b2b.1284389762
Directory /workspace/27.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/27.sram_ctrl_ram_cfg.359970930
Short name T952
Test name
Test status
Simulation time 1350649188 ps
CPU time 13.78 seconds
Started Jan 10 01:28:00 PM PST 24
Finished Jan 10 01:29:19 PM PST 24
Peak memory 202416 kb
Host smart-e985839f-00fd-46b0-ba5e-0d75eadd6d52
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359970930 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.359970930
Directory /workspace/27.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/27.sram_ctrl_regwen.1615495863
Short name T710
Test name
Test status
Simulation time 3722739054 ps
CPU time 797.17 seconds
Started Jan 10 01:28:08 PM PST 24
Finished Jan 10 01:42:25 PM PST 24
Peak memory 379156 kb
Host smart-d9678834-3f62-4948-96ff-18b4b8d4671c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615495863 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.1615495863
Directory /workspace/27.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/27.sram_ctrl_smoke.1240034097
Short name T859
Test name
Test status
Simulation time 2195456475 ps
CPU time 108.7 seconds
Started Jan 10 01:27:30 PM PST 24
Finished Jan 10 01:29:28 PM PST 24
Peak memory 371860 kb
Host smart-5c60601d-0002-48af-a218-0ababb038032
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240034097 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.1240034097
Directory /workspace/27.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/27.sram_ctrl_stress_all.3965664957
Short name T388
Test name
Test status
Simulation time 156715298495 ps
CPU time 2976.12 seconds
Started Jan 10 01:28:11 PM PST 24
Finished Jan 10 02:18:45 PM PST 24
Peak memory 382064 kb
Host smart-f723ada2-7582-4570-aa6e-c50a28a37a94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965664957 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 27.sram_ctrl_stress_all.3965664957
Directory /workspace/27.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.2135190832
Short name T922
Test name
Test status
Simulation time 574521434 ps
CPU time 5149.57 seconds
Started Jan 10 01:28:17 PM PST 24
Finished Jan 10 02:55:03 PM PST 24
Peak memory 735532 kb
Host smart-d0bc7351-2ca0-4247-8619-ee417f69de2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2135190832 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all_with_rand_reset.2135190832
Directory /workspace/27.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.sram_ctrl_stress_pipeline.3025468870
Short name T884
Test name
Test status
Simulation time 16377087410 ps
CPU time 307.78 seconds
Started Jan 10 01:27:41 PM PST 24
Finished Jan 10 01:33:38 PM PST 24
Peak memory 202072 kb
Host smart-7147f863-6cdd-4679-bcfa-6020e69b59a9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025468870 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.sram_ctrl_stress_pipeline.3025468870
Directory /workspace/27.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/28.sram_ctrl_access_during_key_req.2692833051
Short name T622
Test name
Test status
Simulation time 40371683791 ps
CPU time 1661.64 seconds
Started Jan 10 01:28:20 PM PST 24
Finished Jan 10 01:56:47 PM PST 24
Peak memory 381136 kb
Host smart-f9282f88-8365-430a-b94a-a31f00f08f38
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692833051 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 28.sram_ctrl_access_during_key_req.2692833051
Directory /workspace/28.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/28.sram_ctrl_alert_test.1489528826
Short name T21
Test name
Test status
Simulation time 18588143 ps
CPU time 0.63 seconds
Started Jan 10 01:29:00 PM PST 24
Finished Jan 10 01:29:23 PM PST 24
Peak memory 201388 kb
Host smart-e0315c7e-60d6-4e91-be4d-08d472276130
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489528826 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.sram_ctrl_alert_test.1489528826
Directory /workspace/28.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.sram_ctrl_bijection.3236133563
Short name T890
Test name
Test status
Simulation time 288132183998 ps
CPU time 1738.93 seconds
Started Jan 10 01:28:10 PM PST 24
Finished Jan 10 01:58:03 PM PST 24
Peak memory 202188 kb
Host smart-e3651782-973d-404a-a05e-cddc49b9db96
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236133563 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection
.3236133563
Directory /workspace/28.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/28.sram_ctrl_lc_escalation.1492330042
Short name T600
Test name
Test status
Simulation time 9824388952 ps
CPU time 234.07 seconds
Started Jan 10 01:28:14 PM PST 24
Finished Jan 10 01:33:04 PM PST 24
Peak memory 210420 kb
Host smart-0220e0a9-2cc4-4f66-bb4f-b4493abfb640
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492330042 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_lc_es
calation.1492330042
Directory /workspace/28.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/28.sram_ctrl_max_throughput.958346238
Short name T377
Test name
Test status
Simulation time 3053384263 ps
CPU time 99.38 seconds
Started Jan 10 01:28:19 PM PST 24
Finished Jan 10 01:30:48 PM PST 24
Peak memory 365616 kb
Host smart-d21a7967-e4dd-4504-9e30-7d88b7b2ebfe
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958346238 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.sram_ctrl_max_throughput.958346238
Directory /workspace/28.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/28.sram_ctrl_mem_partial_access.3019316706
Short name T953
Test name
Test status
Simulation time 2569138645 ps
CPU time 73.9 seconds
Started Jan 10 01:28:19 PM PST 24
Finished Jan 10 01:30:22 PM PST 24
Peak memory 211472 kb
Host smart-4459ab5a-2336-4ee1-9248-6c7b9c7d78cc
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019316706 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
8.sram_ctrl_mem_partial_access.3019316706
Directory /workspace/28.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/28.sram_ctrl_mem_walk.776617500
Short name T715
Test name
Test status
Simulation time 10641054994 ps
CPU time 153.68 seconds
Started Jan 10 01:28:19 PM PST 24
Finished Jan 10 01:31:42 PM PST 24
Peak memory 201932 kb
Host smart-f6f03c3b-698c-40f9-a32a-a29edc8d81ce
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776617500 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl
_mem_walk.776617500
Directory /workspace/28.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/28.sram_ctrl_multiple_keys.1546057636
Short name T323
Test name
Test status
Simulation time 84842383211 ps
CPU time 1797.13 seconds
Started Jan 10 01:28:17 PM PST 24
Finished Jan 10 01:59:01 PM PST 24
Peak memory 379392 kb
Host smart-d0dd3f1e-ca1c-47c7-83a8-b42e3b5efd1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546057636 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multi
ple_keys.1546057636
Directory /workspace/28.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/28.sram_ctrl_partial_access.2943348523
Short name T438
Test name
Test status
Simulation time 766362396 ps
CPU time 7.31 seconds
Started Jan 10 01:28:16 PM PST 24
Finished Jan 10 01:29:14 PM PST 24
Peak memory 202048 kb
Host smart-70d0d403-01a3-43b3-a8a4-31c6a0dc4916
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943348523 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
sram_ctrl_partial_access.2943348523
Directory /workspace/28.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.941660172
Short name T876
Test name
Test status
Simulation time 267399145346 ps
CPU time 447.23 seconds
Started Jan 10 01:28:16 PM PST 24
Finished Jan 10 01:36:33 PM PST 24
Peak memory 202168 kb
Host smart-a73dccb6-673c-4172-a8d4-fa0177c5bb7e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941660172 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.sram_ctrl_partial_access_b2b.941660172
Directory /workspace/28.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/28.sram_ctrl_ram_cfg.3446289739
Short name T633
Test name
Test status
Simulation time 1402848287 ps
CPU time 5.44 seconds
Started Jan 10 01:28:37 PM PST 24
Finished Jan 10 01:29:20 PM PST 24
Peak memory 202328 kb
Host smart-c4b88de6-e905-42a4-a578-664aa047d60d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446289739 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.3446289739
Directory /workspace/28.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/28.sram_ctrl_regwen.1253494830
Short name T604
Test name
Test status
Simulation time 108953821807 ps
CPU time 1098.12 seconds
Started Jan 10 01:28:19 PM PST 24
Finished Jan 10 01:47:26 PM PST 24
Peak memory 376892 kb
Host smart-3a8d12b5-21a8-4ec0-80c0-41e248cfa03a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253494830 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.1253494830
Directory /workspace/28.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/28.sram_ctrl_smoke.51483832
Short name T474
Test name
Test status
Simulation time 3914554949 ps
CPU time 12.87 seconds
Started Jan 10 01:28:13 PM PST 24
Finished Jan 10 01:29:18 PM PST 24
Peak memory 202172 kb
Host smart-5d148bc9-e75e-4090-b5ea-cf57fb9373da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51483832 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.51483832
Directory /workspace/28.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/28.sram_ctrl_stress_all.4120528210
Short name T965
Test name
Test status
Simulation time 1563740495405 ps
CPU time 4154.23 seconds
Started Jan 10 01:28:20 PM PST 24
Finished Jan 10 02:38:19 PM PST 24
Peak memory 380848 kb
Host smart-3a341afd-2df2-4785-b6f2-65860ae3e0fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120528210 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 28.sram_ctrl_stress_all.4120528210
Directory /workspace/28.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.886142283
Short name T468
Test name
Test status
Simulation time 1182928793 ps
CPU time 2153.7 seconds
Started Jan 10 01:28:53 PM PST 24
Finished Jan 10 02:05:13 PM PST 24
Peak memory 676492 kb
Host smart-437b45a0-64fd-44d4-a916-646ab5e93490
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=886142283 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all_with_rand_reset.886142283
Directory /workspace/28.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.sram_ctrl_stress_pipeline.520775816
Short name T944
Test name
Test status
Simulation time 3546674528 ps
CPU time 263.83 seconds
Started Jan 10 01:28:12 PM PST 24
Finished Jan 10 01:33:29 PM PST 24
Peak memory 202212 kb
Host smart-c8221be9-6c6e-43fb-b792-eab1b57d7772
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520775816 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.sram_ctrl_stress_pipeline.520775816
Directory /workspace/28.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.1878237785
Short name T499
Test name
Test status
Simulation time 1439691123 ps
CPU time 32.93 seconds
Started Jan 10 01:28:56 PM PST 24
Finished Jan 10 01:29:54 PM PST 24
Peak memory 234796 kb
Host smart-e8462dfc-b3ea-412f-914e-49b4d8aa2ab0
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878237785 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.sram_ctrl_throughput_w_partial_write.1878237785
Directory /workspace/28.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/29.sram_ctrl_access_during_key_req.3990479110
Short name T331
Test name
Test status
Simulation time 25912133593 ps
CPU time 610.63 seconds
Started Jan 10 01:27:29 PM PST 24
Finished Jan 10 01:37:50 PM PST 24
Peak memory 345360 kb
Host smart-9108f1c0-ec09-4e5a-b6fb-044e91ec4fab
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990479110 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 29.sram_ctrl_access_during_key_req.3990479110
Directory /workspace/29.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/29.sram_ctrl_alert_test.1547385268
Short name T211
Test name
Test status
Simulation time 14287234 ps
CPU time 0.65 seconds
Started Jan 10 01:27:44 PM PST 24
Finished Jan 10 01:28:54 PM PST 24
Peak memory 201804 kb
Host smart-72aca639-ae96-4841-9bfe-94233bfa6643
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547385268 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.sram_ctrl_alert_test.1547385268
Directory /workspace/29.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.sram_ctrl_bijection.2161508745
Short name T632
Test name
Test status
Simulation time 179587308402 ps
CPU time 1697.72 seconds
Started Jan 10 01:28:56 PM PST 24
Finished Jan 10 01:57:40 PM PST 24
Peak memory 202252 kb
Host smart-ac46a209-c9d0-4115-a0ae-7c5393efe051
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161508745 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection
.2161508745
Directory /workspace/29.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/29.sram_ctrl_executable.1421333557
Short name T334
Test name
Test status
Simulation time 16397852667 ps
CPU time 342.55 seconds
Started Jan 10 01:27:30 PM PST 24
Finished Jan 10 01:33:24 PM PST 24
Peak memory 354460 kb
Host smart-1a7eb0a9-ff10-426c-8d8b-5768759e27fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421333557 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_executab
le.1421333557
Directory /workspace/29.sram_ctrl_executable/latest

Test location /workspace/coverage/default/29.sram_ctrl_max_throughput.792191537
Short name T286
Test name
Test status
Simulation time 783546976 ps
CPU time 160.23 seconds
Started Jan 10 01:27:21 PM PST 24
Finished Jan 10 01:30:02 PM PST 24
Peak memory 363668 kb
Host smart-b41ffbd3-f3ba-4b7b-b1ce-6f31f660ce85
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792191537 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.sram_ctrl_max_throughput.792191537
Directory /workspace/29.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/29.sram_ctrl_mem_partial_access.393992826
Short name T539
Test name
Test status
Simulation time 6464568622 ps
CPU time 141.32 seconds
Started Jan 10 01:27:55 PM PST 24
Finished Jan 10 01:31:14 PM PST 24
Peak memory 211240 kb
Host smart-a55e2839-17f3-460c-8b77-d2e7a538f459
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393992826 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.sram_ctrl_mem_partial_access.393992826
Directory /workspace/29.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/29.sram_ctrl_mem_walk.1709990213
Short name T881
Test name
Test status
Simulation time 4699915666 ps
CPU time 124.87 seconds
Started Jan 10 01:27:46 PM PST 24
Finished Jan 10 01:30:56 PM PST 24
Peak memory 202120 kb
Host smart-8976d74e-304f-436a-bb9a-c91868c3df04
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709990213 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctr
l_mem_walk.1709990213
Directory /workspace/29.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/29.sram_ctrl_multiple_keys.885795490
Short name T877
Test name
Test status
Simulation time 16572080415 ps
CPU time 715.58 seconds
Started Jan 10 01:28:34 PM PST 24
Finished Jan 10 01:41:08 PM PST 24
Peak memory 374744 kb
Host smart-5ca907af-f27d-45bf-962b-1f601b37f1ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885795490 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multip
le_keys.885795490
Directory /workspace/29.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.2124773217
Short name T225
Test name
Test status
Simulation time 9877894325 ps
CPU time 177.62 seconds
Started Jan 10 01:27:31 PM PST 24
Finished Jan 10 01:30:39 PM PST 24
Peak memory 202140 kb
Host smart-a1a67665-f8de-4726-9e87-ee488f1652fb
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124773217 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 29.sram_ctrl_partial_access_b2b.2124773217
Directory /workspace/29.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/29.sram_ctrl_ram_cfg.2221937022
Short name T475
Test name
Test status
Simulation time 358509517 ps
CPU time 5.24 seconds
Started Jan 10 01:27:41 PM PST 24
Finished Jan 10 01:28:22 PM PST 24
Peak memory 202424 kb
Host smart-32b78690-a1e2-4f54-819f-9a0ee6944abc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221937022 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.2221937022
Directory /workspace/29.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/29.sram_ctrl_regwen.3782052014
Short name T628
Test name
Test status
Simulation time 64276461849 ps
CPU time 1177.68 seconds
Started Jan 10 01:27:37 PM PST 24
Finished Jan 10 01:47:42 PM PST 24
Peak memory 378104 kb
Host smart-edb3cf65-d3d0-4bf3-9263-24ddf025eaa2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782052014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.3782052014
Directory /workspace/29.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/29.sram_ctrl_smoke.2975832718
Short name T559
Test name
Test status
Simulation time 1786176305 ps
CPU time 57.22 seconds
Started Jan 10 01:28:35 PM PST 24
Finished Jan 10 01:30:10 PM PST 24
Peak memory 324840 kb
Host smart-191526fe-c049-410a-9ed9-9f424d78cfd8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975832718 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.2975832718
Directory /workspace/29.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.318408298
Short name T601
Test name
Test status
Simulation time 1201055950 ps
CPU time 3328.02 seconds
Started Jan 10 01:27:40 PM PST 24
Finished Jan 10 02:23:35 PM PST 24
Peak memory 521488 kb
Host smart-f81bcd2f-d775-4a34-ab02-6070f4540218
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=318408298 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all_with_rand_reset.318408298
Directory /workspace/29.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.sram_ctrl_stress_pipeline.217131859
Short name T461
Test name
Test status
Simulation time 25988668738 ps
CPU time 329.1 seconds
Started Jan 10 01:28:41 PM PST 24
Finished Jan 10 01:34:44 PM PST 24
Peak memory 202136 kb
Host smart-be7fa548-30a1-4d66-8003-e3df5f3d3450
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217131859 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.sram_ctrl_stress_pipeline.217131859
Directory /workspace/29.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.3999715436
Short name T329
Test name
Test status
Simulation time 1066164401 ps
CPU time 26.58 seconds
Started Jan 10 01:27:30 PM PST 24
Finished Jan 10 01:28:08 PM PST 24
Peak memory 210352 kb
Host smart-bd9dd80e-c8c8-41ba-bd49-1eaa176948f4
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999715436 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 29.sram_ctrl_throughput_w_partial_write.3999715436
Directory /workspace/29.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/3.sram_ctrl_access_during_key_req.2351247803
Short name T398
Test name
Test status
Simulation time 9269555190 ps
CPU time 1388.33 seconds
Started Jan 10 01:26:35 PM PST 24
Finished Jan 10 01:49:58 PM PST 24
Peak memory 369808 kb
Host smart-80bf9db3-7b26-4964-9a92-5a14c2268a55
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351247803 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.sram_ctrl_access_during_key_req.2351247803
Directory /workspace/3.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/3.sram_ctrl_alert_test.370442190
Short name T342
Test name
Test status
Simulation time 60020572 ps
CPU time 0.62 seconds
Started Jan 10 01:26:29 PM PST 24
Finished Jan 10 01:26:43 PM PST 24
Peak memory 201428 kb
Host smart-600b8e54-665d-4c53-880f-318f08432d8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370442190 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.sram_ctrl_alert_test.370442190
Directory /workspace/3.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.sram_ctrl_bijection.2639799854
Short name T772
Test name
Test status
Simulation time 579749270074 ps
CPU time 2485.72 seconds
Started Jan 10 01:26:09 PM PST 24
Finished Jan 10 02:07:58 PM PST 24
Peak memory 202288 kb
Host smart-601ea387-4ae7-41cd-a9fb-b91cab6ebc51
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639799854 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection.
2639799854
Directory /workspace/3.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/3.sram_ctrl_max_throughput.3004647255
Short name T639
Test name
Test status
Simulation time 757404285 ps
CPU time 79.18 seconds
Started Jan 10 01:26:09 PM PST 24
Finished Jan 10 01:27:51 PM PST 24
Peak memory 325844 kb
Host smart-a429a0bf-5eb6-40d4-802c-d91300331a24
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004647255 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 3.sram_ctrl_max_throughput.3004647255
Directory /workspace/3.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/3.sram_ctrl_mem_partial_access.4183319112
Short name T401
Test name
Test status
Simulation time 6439789303 ps
CPU time 138.24 seconds
Started Jan 10 01:26:25 PM PST 24
Finished Jan 10 01:28:59 PM PST 24
Peak memory 218556 kb
Host smart-2169ac83-e6af-4177-9ec6-cf420cab7239
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183319112 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.sram_ctrl_mem_partial_access.4183319112
Directory /workspace/3.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/3.sram_ctrl_mem_walk.1350958249
Short name T905
Test name
Test status
Simulation time 2058202756 ps
CPU time 123.01 seconds
Started Jan 10 01:26:26 PM PST 24
Finished Jan 10 01:28:43 PM PST 24
Peak memory 202084 kb
Host smart-ec1ca4d9-6d13-4086-89c5-05209c1a2cf6
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350958249 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl
_mem_walk.1350958249
Directory /workspace/3.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/3.sram_ctrl_multiple_keys.2878841785
Short name T330
Test name
Test status
Simulation time 15380001168 ps
CPU time 1036.82 seconds
Started Jan 10 01:26:05 PM PST 24
Finished Jan 10 01:43:40 PM PST 24
Peak memory 373980 kb
Host smart-074951ca-07f1-452e-8abc-04063585f35a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878841785 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multip
le_keys.2878841785
Directory /workspace/3.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/3.sram_ctrl_partial_access.3182680483
Short name T946
Test name
Test status
Simulation time 789930383 ps
CPU time 21.94 seconds
Started Jan 10 01:26:12 PM PST 24
Finished Jan 10 01:26:56 PM PST 24
Peak memory 245732 kb
Host smart-43be0c51-4c99-428d-92a9-e4c47c74b6e0
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182680483 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.s
ram_ctrl_partial_access.3182680483
Directory /workspace/3.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.3906274264
Short name T857
Test name
Test status
Simulation time 57992404414 ps
CPU time 592.07 seconds
Started Jan 10 01:26:08 PM PST 24
Finished Jan 10 01:36:22 PM PST 24
Peak memory 202164 kb
Host smart-1f638cff-b720-4e15-9e04-40df596862ad
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906274264 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 3.sram_ctrl_partial_access_b2b.3906274264
Directory /workspace/3.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/3.sram_ctrl_ram_cfg.3949859683
Short name T940
Test name
Test status
Simulation time 345899847 ps
CPU time 5.45 seconds
Started Jan 10 01:26:21 PM PST 24
Finished Jan 10 01:26:44 PM PST 24
Peak memory 202336 kb
Host smart-2f7a66a0-65a8-4c88-b452-39680abb8f48
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949859683 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.3949859683
Directory /workspace/3.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/3.sram_ctrl_regwen.1931107830
Short name T708
Test name
Test status
Simulation time 6953900283 ps
CPU time 233.48 seconds
Started Jan 10 01:26:33 PM PST 24
Finished Jan 10 01:30:40 PM PST 24
Peak memory 357568 kb
Host smart-ecf957fd-6ab5-4829-a173-fbc30d83e280
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931107830 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.1931107830
Directory /workspace/3.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/3.sram_ctrl_sec_cm.2390536649
Short name T24
Test name
Test status
Simulation time 1888335543 ps
CPU time 2.34 seconds
Started Jan 10 01:26:32 PM PST 24
Finished Jan 10 01:26:47 PM PST 24
Peak memory 232040 kb
Host smart-446d646e-c560-431c-beb7-2ae50109f8a0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390536649 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.sram_ctrl_sec_cm.2390536649
Directory /workspace/3.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.sram_ctrl_smoke.3759481848
Short name T947
Test name
Test status
Simulation time 3708561256 ps
CPU time 37.61 seconds
Started Jan 10 01:26:06 PM PST 24
Finished Jan 10 01:27:04 PM PST 24
Peak memory 202128 kb
Host smart-ff877db2-119b-404c-b4c4-549f94e816cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759481848 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.3759481848
Directory /workspace/3.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/3.sram_ctrl_stress_all.2185133959
Short name T652
Test name
Test status
Simulation time 26839686098 ps
CPU time 4435.86 seconds
Started Jan 10 01:26:19 PM PST 24
Finished Jan 10 02:40:34 PM PST 24
Peak memory 382112 kb
Host smart-4eb5c047-5f2a-43dc-af6e-845dccc1895c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185133959 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 3.sram_ctrl_stress_all.2185133959
Directory /workspace/3.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.176309594
Short name T731
Test name
Test status
Simulation time 2982164467 ps
CPU time 5163.01 seconds
Started Jan 10 01:26:25 PM PST 24
Finished Jan 10 02:52:44 PM PST 24
Peak memory 604344 kb
Host smart-8a2a0fc7-ec75-4031-92c4-50c148947c56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=176309594 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all_with_rand_reset.176309594
Directory /workspace/3.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.sram_ctrl_stress_pipeline.848577234
Short name T591
Test name
Test status
Simulation time 5528787436 ps
CPU time 436.49 seconds
Started Jan 10 01:26:10 PM PST 24
Finished Jan 10 01:33:49 PM PST 24
Peak memory 202172 kb
Host smart-794d005f-9f00-4f71-a80c-b2a6d0f99614
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848577234 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
sram_ctrl_stress_pipeline.848577234
Directory /workspace/3.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.1832911738
Short name T256
Test name
Test status
Simulation time 1571922918 ps
CPU time 127.06 seconds
Started Jan 10 01:26:11 PM PST 24
Finished Jan 10 01:28:40 PM PST 24
Peak memory 374964 kb
Host smart-17f3103d-ec88-4f2a-ba49-639c5b6d1a45
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832911738 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.sram_ctrl_throughput_w_partial_write.1832911738
Directory /workspace/3.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/30.sram_ctrl_access_during_key_req.1833461498
Short name T348
Test name
Test status
Simulation time 7604277552 ps
CPU time 709.09 seconds
Started Jan 10 01:28:14 PM PST 24
Finished Jan 10 01:40:58 PM PST 24
Peak memory 376032 kb
Host smart-37cae521-7c3a-476f-b724-3492d5a91c88
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833461498 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.sram_ctrl_access_during_key_req.1833461498
Directory /workspace/30.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/30.sram_ctrl_alert_test.2151389886
Short name T238
Test name
Test status
Simulation time 23042496 ps
CPU time 0.63 seconds
Started Jan 10 01:28:19 PM PST 24
Finished Jan 10 01:29:03 PM PST 24
Peak memory 201856 kb
Host smart-7b9b5db1-2899-401c-8163-b0198adc5fbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151389886 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.sram_ctrl_alert_test.2151389886
Directory /workspace/30.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.sram_ctrl_bijection.1661530820
Short name T389
Test name
Test status
Simulation time 163221036506 ps
CPU time 2643.85 seconds
Started Jan 10 01:27:45 PM PST 24
Finished Jan 10 02:12:57 PM PST 24
Peak memory 202168 kb
Host smart-2c5e1c9f-ad9f-48fb-97b5-89fe6ba2db88
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661530820 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection
.1661530820
Directory /workspace/30.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/30.sram_ctrl_executable.4122165611
Short name T871
Test name
Test status
Simulation time 17589293470 ps
CPU time 812.58 seconds
Started Jan 10 01:27:46 PM PST 24
Finished Jan 10 01:42:24 PM PST 24
Peak memory 377852 kb
Host smart-b50176fc-cb7a-4b06-8d67-a7e583811eb9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122165611 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_executab
le.4122165611
Directory /workspace/30.sram_ctrl_executable/latest

Test location /workspace/coverage/default/30.sram_ctrl_lc_escalation.2627006822
Short name T536
Test name
Test status
Simulation time 6514980595 ps
CPU time 75.1 seconds
Started Jan 10 01:27:20 PM PST 24
Finished Jan 10 01:28:36 PM PST 24
Peak memory 213980 kb
Host smart-49b56eb4-147e-4e3f-a0c8-b476955b54e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627006822 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_es
calation.2627006822
Directory /workspace/30.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/30.sram_ctrl_max_throughput.852632216
Short name T915
Test name
Test status
Simulation time 3047970225 ps
CPU time 42.11 seconds
Started Jan 10 01:28:11 PM PST 24
Finished Jan 10 01:29:46 PM PST 24
Peak memory 262632 kb
Host smart-c2ecbec8-447a-46d3-bf87-4a4066cfc9c1
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852632216 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.sram_ctrl_max_throughput.852632216
Directory /workspace/30.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/30.sram_ctrl_mem_partial_access.2928447601
Short name T838
Test name
Test status
Simulation time 7870771556 ps
CPU time 75.48 seconds
Started Jan 10 01:28:07 PM PST 24
Finished Jan 10 01:30:22 PM PST 24
Peak memory 211052 kb
Host smart-3896061e-4c2c-4a4c-b587-a1e0584fac27
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928447601 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.sram_ctrl_mem_partial_access.2928447601
Directory /workspace/30.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/30.sram_ctrl_mem_walk.2376189170
Short name T283
Test name
Test status
Simulation time 89931636349 ps
CPU time 313.08 seconds
Started Jan 10 01:28:09 PM PST 24
Finished Jan 10 01:34:16 PM PST 24
Peak memory 202204 kb
Host smart-e162493a-e028-4c2c-9a0e-f68eca9302a7
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376189170 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctr
l_mem_walk.2376189170
Directory /workspace/30.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/30.sram_ctrl_multiple_keys.1362509709
Short name T761
Test name
Test status
Simulation time 4455205180 ps
CPU time 650.28 seconds
Started Jan 10 01:27:55 PM PST 24
Finished Jan 10 01:39:43 PM PST 24
Peak memory 375012 kb
Host smart-b158cc89-ca5d-4aa0-bcdc-17bb14fc8773
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362509709 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multi
ple_keys.1362509709
Directory /workspace/30.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/30.sram_ctrl_partial_access.1328032215
Short name T960
Test name
Test status
Simulation time 2842912186 ps
CPU time 29.13 seconds
Started Jan 10 01:27:47 PM PST 24
Finished Jan 10 01:29:25 PM PST 24
Peak memory 209556 kb
Host smart-5f648a68-84b4-4422-827d-0a56ad9c512d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328032215 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
sram_ctrl_partial_access.1328032215
Directory /workspace/30.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.4170014303
Short name T751
Test name
Test status
Simulation time 48172437559 ps
CPU time 520.38 seconds
Started Jan 10 01:28:11 PM PST 24
Finished Jan 10 01:37:46 PM PST 24
Peak memory 202172 kb
Host smart-9a75b538-0dd5-471d-a441-f4aac69238b0
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170014303 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 30.sram_ctrl_partial_access_b2b.4170014303
Directory /workspace/30.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/30.sram_ctrl_ram_cfg.4279241667
Short name T757
Test name
Test status
Simulation time 353196514 ps
CPU time 6.81 seconds
Started Jan 10 01:28:17 PM PST 24
Finished Jan 10 01:29:19 PM PST 24
Peak memory 202480 kb
Host smart-9bd2eac8-6157-4d0d-bf91-44d6f49a6981
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279241667 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.4279241667
Directory /workspace/30.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/30.sram_ctrl_regwen.2938572667
Short name T113
Test name
Test status
Simulation time 4149578051 ps
CPU time 1035.92 seconds
Started Jan 10 01:27:59 PM PST 24
Finished Jan 10 01:46:12 PM PST 24
Peak memory 381188 kb
Host smart-37657805-5322-4ca4-81fa-dbab45f05a62
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938572667 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.2938572667
Directory /workspace/30.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/30.sram_ctrl_smoke.2200121686
Short name T706
Test name
Test status
Simulation time 2908592322 ps
CPU time 6.57 seconds
Started Jan 10 01:27:54 PM PST 24
Finished Jan 10 01:28:59 PM PST 24
Peak memory 202160 kb
Host smart-3e14a494-f97b-4d61-a665-23a81a231287
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200121686 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.2200121686
Directory /workspace/30.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/30.sram_ctrl_stress_all.1472731723
Short name T721
Test name
Test status
Simulation time 49145113923 ps
CPU time 3407.06 seconds
Started Jan 10 01:28:11 PM PST 24
Finished Jan 10 02:25:55 PM PST 24
Peak memory 382156 kb
Host smart-bedc3c27-d565-414a-9889-01704f1866e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472731723 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 30.sram_ctrl_stress_all.1472731723
Directory /workspace/30.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.2884458419
Short name T522
Test name
Test status
Simulation time 2319821717 ps
CPU time 4724.17 seconds
Started Jan 10 01:28:16 PM PST 24
Finished Jan 10 02:47:50 PM PST 24
Peak memory 521760 kb
Host smart-f839def7-7bfa-4128-b5c5-c7069b77456d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2884458419 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all_with_rand_reset.2884458419
Directory /workspace/30.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.sram_ctrl_stress_pipeline.2725905164
Short name T747
Test name
Test status
Simulation time 104625232985 ps
CPU time 420.37 seconds
Started Jan 10 01:27:49 PM PST 24
Finished Jan 10 01:35:52 PM PST 24
Peak memory 202168 kb
Host smart-0371697c-0752-4af6-b08e-3c9a7c7a1931
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725905164 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.sram_ctrl_stress_pipeline.2725905164
Directory /workspace/30.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.77944434
Short name T746
Test name
Test status
Simulation time 2798237697 ps
CPU time 29.3 seconds
Started Jan 10 01:28:10 PM PST 24
Finished Jan 10 01:29:35 PM PST 24
Peak memory 210416 kb
Host smart-db32d91a-774c-41d4-9887-b504136c1552
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77944434 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.sram_ctrl_throughput_w_partial_write.77944434
Directory /workspace/30.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/31.sram_ctrl_access_during_key_req.25062600
Short name T554
Test name
Test status
Simulation time 4546835175 ps
CPU time 506.82 seconds
Started Jan 10 01:28:38 PM PST 24
Finished Jan 10 01:37:42 PM PST 24
Peak memory 376048 kb
Host smart-eeb30e92-a78a-4ff1-a652-0a999f8578b1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25062600 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 31.sram_ctrl_access_during_key_req.25062600
Directory /workspace/31.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/31.sram_ctrl_alert_test.4116604957
Short name T511
Test name
Test status
Simulation time 19408065 ps
CPU time 0.64 seconds
Started Jan 10 01:27:42 PM PST 24
Finished Jan 10 01:28:31 PM PST 24
Peak memory 201876 kb
Host smart-70919fbb-b747-4f10-a551-76f3103ecbd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116604957 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.sram_ctrl_alert_test.4116604957
Directory /workspace/31.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.sram_ctrl_bijection.2976248421
Short name T234
Test name
Test status
Simulation time 153216693211 ps
CPU time 2561.58 seconds
Started Jan 10 01:28:19 PM PST 24
Finished Jan 10 02:11:46 PM PST 24
Peak memory 202380 kb
Host smart-701c9205-1646-4eb1-893a-e821b3f7afc1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976248421 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection
.2976248421
Directory /workspace/31.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/31.sram_ctrl_lc_escalation.2496434585
Short name T547
Test name
Test status
Simulation time 9388559664 ps
CPU time 82.1 seconds
Started Jan 10 01:28:56 PM PST 24
Finished Jan 10 01:30:44 PM PST 24
Peak memory 210328 kb
Host smart-9a08d569-bac0-4111-85be-94a0a5b281ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496434585 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_lc_es
calation.2496434585
Directory /workspace/31.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/31.sram_ctrl_max_throughput.3223207587
Short name T125
Test name
Test status
Simulation time 955348515 ps
CPU time 114.01 seconds
Started Jan 10 01:28:19 PM PST 24
Finished Jan 10 01:31:02 PM PST 24
Peak memory 358568 kb
Host smart-dc2281c2-285a-4688-a6b0-fbc5e4db857f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223207587 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 31.sram_ctrl_max_throughput.3223207587
Directory /workspace/31.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/31.sram_ctrl_mem_partial_access.3274365587
Short name T538
Test name
Test status
Simulation time 28944554582 ps
CPU time 142.54 seconds
Started Jan 10 01:28:20 PM PST 24
Finished Jan 10 01:31:28 PM PST 24
Peak memory 218488 kb
Host smart-96b63048-9c3f-44a3-8375-182269d56a33
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274365587 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.sram_ctrl_mem_partial_access.3274365587
Directory /workspace/31.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/31.sram_ctrl_mem_walk.3046194044
Short name T748
Test name
Test status
Simulation time 2127712093 ps
CPU time 121.26 seconds
Started Jan 10 01:29:01 PM PST 24
Finished Jan 10 01:31:24 PM PST 24
Peak memory 201708 kb
Host smart-f151675a-0a13-45fb-bce2-8a56a50b2abe
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046194044 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctr
l_mem_walk.3046194044
Directory /workspace/31.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/31.sram_ctrl_multiple_keys.448534120
Short name T450
Test name
Test status
Simulation time 24896864522 ps
CPU time 1442.4 seconds
Started Jan 10 01:28:12 PM PST 24
Finished Jan 10 01:53:08 PM PST 24
Peak memory 373080 kb
Host smart-0cbf4923-8bd3-4a0c-9225-82864e321e38
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448534120 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_multip
le_keys.448534120
Directory /workspace/31.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/31.sram_ctrl_partial_access.1223323341
Short name T210
Test name
Test status
Simulation time 2795999448 ps
CPU time 13.16 seconds
Started Jan 10 01:28:18 PM PST 24
Finished Jan 10 01:29:23 PM PST 24
Peak memory 202152 kb
Host smart-58245eb0-6ca4-4087-9bc0-a71db36e9bac
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223323341 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
sram_ctrl_partial_access.1223323341
Directory /workspace/31.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.3828541883
Short name T964
Test name
Test status
Simulation time 56102791101 ps
CPU time 398.75 seconds
Started Jan 10 01:28:57 PM PST 24
Finished Jan 10 01:36:00 PM PST 24
Peak memory 202156 kb
Host smart-065f3e38-1964-4db7-a751-0ecfaf8383a0
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828541883 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 31.sram_ctrl_partial_access_b2b.3828541883
Directory /workspace/31.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/31.sram_ctrl_ram_cfg.3850207681
Short name T750
Test name
Test status
Simulation time 363141961 ps
CPU time 6.1 seconds
Started Jan 10 01:28:55 PM PST 24
Finished Jan 10 01:29:27 PM PST 24
Peak memory 202440 kb
Host smart-de76c91c-7d98-49ef-8be7-aec4bd08c54d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850207681 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.3850207681
Directory /workspace/31.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/31.sram_ctrl_regwen.2018351002
Short name T596
Test name
Test status
Simulation time 15800372568 ps
CPU time 1008.43 seconds
Started Jan 10 01:28:56 PM PST 24
Finished Jan 10 01:46:10 PM PST 24
Peak memory 355240 kb
Host smart-b5dcd02d-41c8-4066-898d-28c423fd6e21
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018351002 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.2018351002
Directory /workspace/31.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/31.sram_ctrl_smoke.486456414
Short name T549
Test name
Test status
Simulation time 1989583681 ps
CPU time 24.57 seconds
Started Jan 10 01:28:11 PM PST 24
Finished Jan 10 01:29:34 PM PST 24
Peak memory 202104 kb
Host smart-fd70b0ef-7c34-463f-bb8c-bc976c4bc15f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486456414 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.486456414
Directory /workspace/31.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.2521514116
Short name T399
Test name
Test status
Simulation time 368136503 ps
CPU time 3520.4 seconds
Started Jan 10 01:27:33 PM PST 24
Finished Jan 10 02:26:40 PM PST 24
Peak memory 676352 kb
Host smart-546fa415-388e-445a-af4b-0e227f88cc31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2521514116 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all_with_rand_reset.2521514116
Directory /workspace/31.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.sram_ctrl_stress_pipeline.3322732783
Short name T910
Test name
Test status
Simulation time 9411401523 ps
CPU time 150.23 seconds
Started Jan 10 01:28:52 PM PST 24
Finished Jan 10 01:31:49 PM PST 24
Peak memory 202020 kb
Host smart-62a1317b-69e9-42bb-b9d0-dcd4af18fb91
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322732783 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.sram_ctrl_stress_pipeline.3322732783
Directory /workspace/31.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.241418521
Short name T832
Test name
Test status
Simulation time 826118513 ps
CPU time 124.8 seconds
Started Jan 10 01:28:56 PM PST 24
Finished Jan 10 01:31:26 PM PST 24
Peak memory 371876 kb
Host smart-92e3382c-5345-4f8c-8c41-b8774bec1f95
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241418521 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 31.sram_ctrl_throughput_w_partial_write.241418521
Directory /workspace/31.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/32.sram_ctrl_access_during_key_req.964477597
Short name T626
Test name
Test status
Simulation time 10730195062 ps
CPU time 1869.32 seconds
Started Jan 10 01:27:48 PM PST 24
Finished Jan 10 02:00:01 PM PST 24
Peak memory 379964 kb
Host smart-273830ed-92c2-47ed-ab67-a00f437f8b7f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964477597 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 32.sram_ctrl_access_during_key_req.964477597
Directory /workspace/32.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/32.sram_ctrl_alert_test.2599739522
Short name T392
Test name
Test status
Simulation time 52428253 ps
CPU time 0.63 seconds
Started Jan 10 01:27:55 PM PST 24
Finished Jan 10 01:28:52 PM PST 24
Peak memory 201776 kb
Host smart-029ad103-3204-41fd-a8e1-c124353b0884
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599739522 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.sram_ctrl_alert_test.2599739522
Directory /workspace/32.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.sram_ctrl_bijection.3723668095
Short name T393
Test name
Test status
Simulation time 898374965840 ps
CPU time 1689.47 seconds
Started Jan 10 01:28:51 PM PST 24
Finished Jan 10 01:57:28 PM PST 24
Peak memory 202192 kb
Host smart-b1c09f5f-699b-49ed-8bde-80bd97e7c72c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723668095 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection
.3723668095
Directory /workspace/32.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/32.sram_ctrl_lc_escalation.79250982
Short name T521
Test name
Test status
Simulation time 12385751493 ps
CPU time 43.68 seconds
Started Jan 10 01:27:22 PM PST 24
Finished Jan 10 01:28:07 PM PST 24
Peak memory 202092 kb
Host smart-1130d85f-df34-4c84-8606-6a2d48fa00d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79250982 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_esc
alation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_lc_esca
lation.79250982
Directory /workspace/32.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/32.sram_ctrl_max_throughput.2565839736
Short name T854
Test name
Test status
Simulation time 836396588 ps
CPU time 127.69 seconds
Started Jan 10 01:27:34 PM PST 24
Finished Jan 10 01:30:11 PM PST 24
Peak memory 345452 kb
Host smart-c52e66f4-80f0-4f40-acf8-a2540d2bd4a2
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565839736 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 32.sram_ctrl_max_throughput.2565839736
Directory /workspace/32.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/32.sram_ctrl_mem_walk.3720196785
Short name T673
Test name
Test status
Simulation time 57299781160 ps
CPU time 291.73 seconds
Started Jan 10 01:28:14 PM PST 24
Finished Jan 10 01:33:58 PM PST 24
Peak memory 202132 kb
Host smart-4e757887-cc25-4131-b677-169135e8cc67
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720196785 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctr
l_mem_walk.3720196785
Directory /workspace/32.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/32.sram_ctrl_multiple_keys.636983300
Short name T574
Test name
Test status
Simulation time 2542934760 ps
CPU time 137.87 seconds
Started Jan 10 01:27:33 PM PST 24
Finished Jan 10 01:30:04 PM PST 24
Peak memory 313728 kb
Host smart-2bdf8341-675f-426f-9192-192165848ea2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636983300 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multip
le_keys.636983300
Directory /workspace/32.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/32.sram_ctrl_partial_access.877637804
Short name T404
Test name
Test status
Simulation time 1758445837 ps
CPU time 112.4 seconds
Started Jan 10 01:27:28 PM PST 24
Finished Jan 10 01:29:24 PM PST 24
Peak memory 362452 kb
Host smart-4d628eed-5619-4fd2-98cf-d837842db067
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877637804 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.s
ram_ctrl_partial_access.877637804
Directory /workspace/32.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.3143829183
Short name T381
Test name
Test status
Simulation time 3450837041 ps
CPU time 202.54 seconds
Started Jan 10 01:27:25 PM PST 24
Finished Jan 10 01:30:49 PM PST 24
Peak memory 202188 kb
Host smart-245b7dc0-aa10-4814-985d-1daef82bb6ac
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143829183 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 32.sram_ctrl_partial_access_b2b.3143829183
Directory /workspace/32.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/32.sram_ctrl_ram_cfg.3894835504
Short name T508
Test name
Test status
Simulation time 370669949 ps
CPU time 6.61 seconds
Started Jan 10 01:27:47 PM PST 24
Finished Jan 10 01:29:00 PM PST 24
Peak memory 202464 kb
Host smart-0bcefeae-f246-4a80-b319-9ff3653fbb7d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894835504 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.3894835504
Directory /workspace/32.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/32.sram_ctrl_regwen.904198497
Short name T391
Test name
Test status
Simulation time 9889004198 ps
CPU time 758.4 seconds
Started Jan 10 01:27:22 PM PST 24
Finished Jan 10 01:40:01 PM PST 24
Peak memory 377716 kb
Host smart-d25fe02f-774e-496d-88c6-3d3a94674aac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904198497 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.904198497
Directory /workspace/32.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/32.sram_ctrl_smoke.3738094199
Short name T436
Test name
Test status
Simulation time 414698235 ps
CPU time 17.83 seconds
Started Jan 10 01:27:24 PM PST 24
Finished Jan 10 01:27:44 PM PST 24
Peak memory 202092 kb
Host smart-8f4f7bfa-12ea-4998-9a50-9134549a677a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738094199 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.3738094199
Directory /workspace/32.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.597639100
Short name T484
Test name
Test status
Simulation time 1329667813 ps
CPU time 2596.86 seconds
Started Jan 10 01:27:47 PM PST 24
Finished Jan 10 02:12:11 PM PST 24
Peak memory 422728 kb
Host smart-0b993dd1-b6cf-4958-ac0d-97d44c6addc6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=597639100 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all_with_rand_reset.597639100
Directory /workspace/32.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.sram_ctrl_stress_pipeline.2960136574
Short name T313
Test name
Test status
Simulation time 5276247891 ps
CPU time 384.01 seconds
Started Jan 10 01:27:28 PM PST 24
Finished Jan 10 01:33:56 PM PST 24
Peak memory 202076 kb
Host smart-2b6c1488-c8a5-421d-8e2c-68863756239a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960136574 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.sram_ctrl_stress_pipeline.2960136574
Directory /workspace/32.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.3862719764
Short name T937
Test name
Test status
Simulation time 3126897578 ps
CPU time 144.67 seconds
Started Jan 10 01:27:57 PM PST 24
Finished Jan 10 01:31:20 PM PST 24
Peak memory 365876 kb
Host smart-44f964d2-4cdd-4d5d-b02a-aab0c8f399c2
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862719764 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.sram_ctrl_throughput_w_partial_write.3862719764
Directory /workspace/32.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/33.sram_ctrl_access_during_key_req.1990576467
Short name T259
Test name
Test status
Simulation time 18526945394 ps
CPU time 585.85 seconds
Started Jan 10 01:28:08 PM PST 24
Finished Jan 10 01:38:56 PM PST 24
Peak memory 366060 kb
Host smart-a6e59c00-1a4a-4ea5-a666-c7dbca94a2ec
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990576467 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 33.sram_ctrl_access_during_key_req.1990576467
Directory /workspace/33.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/33.sram_ctrl_alert_test.558126376
Short name T620
Test name
Test status
Simulation time 37429173 ps
CPU time 0.61 seconds
Started Jan 10 01:28:13 PM PST 24
Finished Jan 10 01:29:05 PM PST 24
Peak memory 201900 kb
Host smart-24981180-49a8-494c-b7ef-bb0f5eb34318
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558126376 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.sram_ctrl_alert_test.558126376
Directory /workspace/33.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.sram_ctrl_bijection.2672577353
Short name T267
Test name
Test status
Simulation time 31795709996 ps
CPU time 2251.69 seconds
Started Jan 10 01:27:45 PM PST 24
Finished Jan 10 02:06:25 PM PST 24
Peak memory 202232 kb
Host smart-f9d88ba0-08d1-4481-94c6-8bc0f1d367cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672577353 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection
.2672577353
Directory /workspace/33.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/33.sram_ctrl_lc_escalation.3263150217
Short name T917
Test name
Test status
Simulation time 5643780246 ps
CPU time 50.61 seconds
Started Jan 10 01:27:59 PM PST 24
Finished Jan 10 01:29:47 PM PST 24
Peak memory 210388 kb
Host smart-e113ac7d-61d2-4c54-af73-777bbb32dd28
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263150217 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_es
calation.3263150217
Directory /workspace/33.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/33.sram_ctrl_max_throughput.729543179
Short name T903
Test name
Test status
Simulation time 3710853787 ps
CPU time 28.18 seconds
Started Jan 10 01:27:58 PM PST 24
Finished Jan 10 01:29:24 PM PST 24
Peak memory 212032 kb
Host smart-98f3be44-0683-4636-9ab7-3201657dd855
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729543179 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.sram_ctrl_max_throughput.729543179
Directory /workspace/33.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/33.sram_ctrl_mem_partial_access.1196556635
Short name T293
Test name
Test status
Simulation time 4903842128 ps
CPU time 78.83 seconds
Started Jan 10 01:28:17 PM PST 24
Finished Jan 10 01:30:23 PM PST 24
Peak memory 211708 kb
Host smart-8a5cc604-c14c-4cc7-9e22-5506d8ff4183
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196556635 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.sram_ctrl_mem_partial_access.1196556635
Directory /workspace/33.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/33.sram_ctrl_mem_walk.798576443
Short name T562
Test name
Test status
Simulation time 4150732376 ps
CPU time 244.27 seconds
Started Jan 10 01:28:12 PM PST 24
Finished Jan 10 01:33:10 PM PST 24
Peak memory 202220 kb
Host smart-6616abf5-cfe5-4f9c-a45f-215276d7c6ae
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798576443 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl
_mem_walk.798576443
Directory /workspace/33.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/33.sram_ctrl_multiple_keys.1840940766
Short name T276
Test name
Test status
Simulation time 95891775702 ps
CPU time 1261.57 seconds
Started Jan 10 01:28:09 PM PST 24
Finished Jan 10 01:50:06 PM PST 24
Peak memory 380240 kb
Host smart-6de7e397-8706-4504-bba6-f4acf6aa0205
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840940766 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multi
ple_keys.1840940766
Directory /workspace/33.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/33.sram_ctrl_partial_access.3121879549
Short name T527
Test name
Test status
Simulation time 1263478657 ps
CPU time 23.9 seconds
Started Jan 10 01:28:17 PM PST 24
Finished Jan 10 01:29:36 PM PST 24
Peak memory 202112 kb
Host smart-59c9ec42-21f1-40eb-80db-2404ffd59bf8
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121879549 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
sram_ctrl_partial_access.3121879549
Directory /workspace/33.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.478915772
Short name T900
Test name
Test status
Simulation time 32358503803 ps
CPU time 431.64 seconds
Started Jan 10 01:27:44 PM PST 24
Finished Jan 10 01:36:02 PM PST 24
Peak memory 202192 kb
Host smart-bc426e97-2f91-44c0-a96a-d0ec00ab341a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478915772 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.sram_ctrl_partial_access_b2b.478915772
Directory /workspace/33.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/33.sram_ctrl_ram_cfg.1413529573
Short name T228
Test name
Test status
Simulation time 423061150 ps
CPU time 13.32 seconds
Started Jan 10 01:28:17 PM PST 24
Finished Jan 10 01:29:18 PM PST 24
Peak memory 202444 kb
Host smart-6f78c392-30a4-49f9-ad11-02e3499315e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413529573 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.1413529573
Directory /workspace/33.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/33.sram_ctrl_regwen.365737389
Short name T717
Test name
Test status
Simulation time 8800515944 ps
CPU time 621.18 seconds
Started Jan 10 01:28:13 PM PST 24
Finished Jan 10 01:39:25 PM PST 24
Peak memory 377060 kb
Host smart-abd284e9-4093-444f-bf68-fcc683631f6d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365737389 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.365737389
Directory /workspace/33.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/33.sram_ctrl_smoke.3734974930
Short name T354
Test name
Test status
Simulation time 3248348223 ps
CPU time 6.12 seconds
Started Jan 10 01:27:55 PM PST 24
Finished Jan 10 01:28:59 PM PST 24
Peak memory 202192 kb
Host smart-1f7ac810-eeeb-4aef-84e5-67d692233b09
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734974930 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.3734974930
Directory /workspace/33.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.2816370446
Short name T535
Test name
Test status
Simulation time 2201400422 ps
CPU time 4538.25 seconds
Started Jan 10 01:28:16 PM PST 24
Finished Jan 10 02:44:44 PM PST 24
Peak memory 439348 kb
Host smart-d02ed506-5ad6-45a7-b2bc-2faa12b8656c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2816370446 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all_with_rand_reset.2816370446
Directory /workspace/33.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.sram_ctrl_stress_pipeline.1143933210
Short name T943
Test name
Test status
Simulation time 4238944503 ps
CPU time 366.46 seconds
Started Jan 10 01:28:10 PM PST 24
Finished Jan 10 01:35:09 PM PST 24
Peak memory 202156 kb
Host smart-9845bb33-41d4-43ea-aaec-1c07bee25bd7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143933210 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.sram_ctrl_stress_pipeline.1143933210
Directory /workspace/33.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/34.sram_ctrl_access_during_key_req.2935161534
Short name T357
Test name
Test status
Simulation time 7899635472 ps
CPU time 379.14 seconds
Started Jan 10 01:28:18 PM PST 24
Finished Jan 10 01:35:29 PM PST 24
Peak memory 346268 kb
Host smart-cae2a14f-adcc-4b01-b9f7-b12e5d819edb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935161534 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.sram_ctrl_access_during_key_req.2935161534
Directory /workspace/34.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/34.sram_ctrl_bijection.2293783399
Short name T437
Test name
Test status
Simulation time 88817668568 ps
CPU time 1538.56 seconds
Started Jan 10 01:28:19 PM PST 24
Finished Jan 10 01:54:43 PM PST 24
Peak memory 202240 kb
Host smart-471810d8-1ddc-4b72-a29a-fba4981dff42
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293783399 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection
.2293783399
Directory /workspace/34.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/34.sram_ctrl_lc_escalation.1070652111
Short name T765
Test name
Test status
Simulation time 36075155456 ps
CPU time 194.59 seconds
Started Jan 10 01:28:19 PM PST 24
Finished Jan 10 01:32:19 PM PST 24
Peak memory 210496 kb
Host smart-928b6ca5-b210-4b4d-9202-54b760b6785e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070652111 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_es
calation.1070652111
Directory /workspace/34.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/34.sram_ctrl_max_throughput.3194021721
Short name T661
Test name
Test status
Simulation time 1682625737 ps
CPU time 120.97 seconds
Started Jan 10 01:28:17 PM PST 24
Finished Jan 10 01:31:05 PM PST 24
Peak memory 351360 kb
Host smart-d47cab81-f280-45de-bcb4-821773321fa1
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194021721 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 34.sram_ctrl_max_throughput.3194021721
Directory /workspace/34.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/34.sram_ctrl_mem_partial_access.2808435721
Short name T963
Test name
Test status
Simulation time 7679822054 ps
CPU time 147.52 seconds
Started Jan 10 01:27:47 PM PST 24
Finished Jan 10 01:31:20 PM PST 24
Peak memory 211628 kb
Host smart-fe136305-d89a-4941-9589-c9be13b08630
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808435721 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
4.sram_ctrl_mem_partial_access.2808435721
Directory /workspace/34.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/34.sram_ctrl_mem_walk.311457370
Short name T781
Test name
Test status
Simulation time 2083489603 ps
CPU time 126.33 seconds
Started Jan 10 01:27:29 PM PST 24
Finished Jan 10 01:29:46 PM PST 24
Peak memory 202060 kb
Host smart-de7e3f8f-41d2-479d-aa42-8d59fced9b49
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311457370 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl
_mem_walk.311457370
Directory /workspace/34.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/34.sram_ctrl_multiple_keys.4088221181
Short name T414
Test name
Test status
Simulation time 7448565004 ps
CPU time 1136.67 seconds
Started Jan 10 01:28:17 PM PST 24
Finished Jan 10 01:48:01 PM PST 24
Peak memory 380148 kb
Host smart-340acdb0-b604-4597-85db-30745a849aa7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088221181 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multi
ple_keys.4088221181
Directory /workspace/34.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/34.sram_ctrl_partial_access.2997142526
Short name T830
Test name
Test status
Simulation time 1190704599 ps
CPU time 16.04 seconds
Started Jan 10 01:28:19 PM PST 24
Finished Jan 10 01:29:24 PM PST 24
Peak memory 202128 kb
Host smart-61a2af6c-779b-4de7-b9c0-404ee34760cd
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997142526 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
sram_ctrl_partial_access.2997142526
Directory /workspace/34.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.2013348068
Short name T722
Test name
Test status
Simulation time 66638948683 ps
CPU time 420.96 seconds
Started Jan 10 01:28:19 PM PST 24
Finished Jan 10 01:36:05 PM PST 24
Peak memory 202140 kb
Host smart-70279e4b-7f9b-4e10-a2d7-0447c2dbd14a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013348068 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 34.sram_ctrl_partial_access_b2b.2013348068
Directory /workspace/34.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/34.sram_ctrl_ram_cfg.1209969894
Short name T232
Test name
Test status
Simulation time 1412589440 ps
CPU time 13.1 seconds
Started Jan 10 01:29:01 PM PST 24
Finished Jan 10 01:29:36 PM PST 24
Peak memory 202444 kb
Host smart-97a35386-ffa9-42a6-8d5f-18847f178108
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209969894 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.1209969894
Directory /workspace/34.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/34.sram_ctrl_regwen.3596092251
Short name T299
Test name
Test status
Simulation time 32381076181 ps
CPU time 891.8 seconds
Started Jan 10 01:28:38 PM PST 24
Finished Jan 10 01:44:07 PM PST 24
Peak memory 378280 kb
Host smart-3675e28a-6a14-45af-96f8-6d9c9ce509cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596092251 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.3596092251
Directory /workspace/34.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/34.sram_ctrl_smoke.366933477
Short name T290
Test name
Test status
Simulation time 2651826968 ps
CPU time 17.98 seconds
Started Jan 10 01:28:21 PM PST 24
Finished Jan 10 01:29:24 PM PST 24
Peak memory 202196 kb
Host smart-f0488889-12d9-42df-acef-56f0bec5cd0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366933477 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.366933477
Directory /workspace/34.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/34.sram_ctrl_stress_all.3402299902
Short name T117
Test name
Test status
Simulation time 306714443002 ps
CPU time 4126.39 seconds
Started Jan 10 01:27:47 PM PST 24
Finished Jan 10 02:37:39 PM PST 24
Peak memory 381120 kb
Host smart-0952fc75-c4c8-4388-8bc9-e6e760007a5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402299902 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 34.sram_ctrl_stress_all.3402299902
Directory /workspace/34.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.241986086
Short name T818
Test name
Test status
Simulation time 4921585222 ps
CPU time 4788.82 seconds
Started Jan 10 01:27:42 PM PST 24
Finished Jan 10 02:48:21 PM PST 24
Peak memory 652620 kb
Host smart-be71ae95-f3e4-4c1c-887c-fb3858978e73
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=241986086 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all_with_rand_reset.241986086
Directory /workspace/34.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.sram_ctrl_stress_pipeline.1783491534
Short name T968
Test name
Test status
Simulation time 29516476030 ps
CPU time 372.16 seconds
Started Jan 10 01:28:18 PM PST 24
Finished Jan 10 01:35:22 PM PST 24
Peak memory 202176 kb
Host smart-8e6e578d-9528-4626-93dd-0b86c0f94005
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783491534 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
4.sram_ctrl_stress_pipeline.1783491534
Directory /workspace/34.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.348274194
Short name T572
Test name
Test status
Simulation time 1536037219 ps
CPU time 55.38 seconds
Started Jan 10 01:28:18 PM PST 24
Finished Jan 10 01:30:05 PM PST 24
Peak memory 297244 kb
Host smart-61f229f0-0abb-4a81-87c1-d4a59df7d450
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348274194 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 34.sram_ctrl_throughput_w_partial_write.348274194
Directory /workspace/34.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/35.sram_ctrl_access_during_key_req.1138661405
Short name T568
Test name
Test status
Simulation time 25139583047 ps
CPU time 369.86 seconds
Started Jan 10 01:27:42 PM PST 24
Finished Jan 10 01:34:41 PM PST 24
Peak memory 363576 kb
Host smart-cbb997e7-36f7-4c85-9610-1784072b633b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138661405 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.sram_ctrl_access_during_key_req.1138661405
Directory /workspace/35.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/35.sram_ctrl_alert_test.2617121735
Short name T278
Test name
Test status
Simulation time 15010599 ps
CPU time 0.65 seconds
Started Jan 10 01:27:48 PM PST 24
Finished Jan 10 01:28:52 PM PST 24
Peak memory 201656 kb
Host smart-4c3eb062-cef4-4f24-856d-cf7033fe4ba0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617121735 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.sram_ctrl_alert_test.2617121735
Directory /workspace/35.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.sram_ctrl_bijection.1889918756
Short name T302
Test name
Test status
Simulation time 16399712567 ps
CPU time 1095.97 seconds
Started Jan 10 01:27:48 PM PST 24
Finished Jan 10 01:47:08 PM PST 24
Peak memory 202000 kb
Host smart-197d2aa6-91dc-4e6f-94a9-e682e8b09217
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889918756 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection
.1889918756
Directory /workspace/35.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/35.sram_ctrl_lc_escalation.3770862547
Short name T441
Test name
Test status
Simulation time 5897749510 ps
CPU time 49.92 seconds
Started Jan 10 01:27:58 PM PST 24
Finished Jan 10 01:29:46 PM PST 24
Peak memory 210496 kb
Host smart-3feb97ce-2258-418c-9a59-9764c5c00746
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770862547 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_es
calation.3770862547
Directory /workspace/35.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/35.sram_ctrl_max_throughput.1811266775
Short name T551
Test name
Test status
Simulation time 2776037906 ps
CPU time 26.47 seconds
Started Jan 10 01:28:02 PM PST 24
Finished Jan 10 01:29:33 PM PST 24
Peak memory 210388 kb
Host smart-bda4919d-edc3-45ee-b244-e4f4e3aedac6
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811266775 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 35.sram_ctrl_max_throughput.1811266775
Directory /workspace/35.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/35.sram_ctrl_mem_partial_access.2748694453
Short name T279
Test name
Test status
Simulation time 4441433940 ps
CPU time 155.59 seconds
Started Jan 10 01:27:46 PM PST 24
Finished Jan 10 01:31:30 PM PST 24
Peak memory 214352 kb
Host smart-1c12490d-7b7e-455d-bc3f-e28fb732f502
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748694453 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.sram_ctrl_mem_partial_access.2748694453
Directory /workspace/35.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/35.sram_ctrl_mem_walk.4128307628
Short name T537
Test name
Test status
Simulation time 14492588873 ps
CPU time 285.87 seconds
Started Jan 10 01:27:41 PM PST 24
Finished Jan 10 01:33:02 PM PST 24
Peak memory 202196 kb
Host smart-d846819c-3ee4-411a-87d0-ab080ec19ed9
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128307628 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctr
l_mem_walk.4128307628
Directory /workspace/35.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/35.sram_ctrl_multiple_keys.2710913638
Short name T585
Test name
Test status
Simulation time 15287909470 ps
CPU time 583.26 seconds
Started Jan 10 01:27:46 PM PST 24
Finished Jan 10 01:38:38 PM PST 24
Peak memory 379060 kb
Host smart-a28eb21a-4acd-4cec-89d7-7134df5e612b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710913638 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multi
ple_keys.2710913638
Directory /workspace/35.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/35.sram_ctrl_partial_access.2992183586
Short name T344
Test name
Test status
Simulation time 1810727112 ps
CPU time 17.17 seconds
Started Jan 10 01:28:01 PM PST 24
Finished Jan 10 01:29:23 PM PST 24
Peak memory 202060 kb
Host smart-f87a9553-a8eb-4536-b8bf-f2cc664cd57c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992183586 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
sram_ctrl_partial_access.2992183586
Directory /workspace/35.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/35.sram_ctrl_partial_access_b2b.677745620
Short name T570
Test name
Test status
Simulation time 17823297321 ps
CPU time 373.57 seconds
Started Jan 10 01:27:42 PM PST 24
Finished Jan 10 01:34:45 PM PST 24
Peak memory 202088 kb
Host smart-37e69a45-5b87-43f0-8b41-8981caedd81a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677745620 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.sram_ctrl_partial_access_b2b.677745620
Directory /workspace/35.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/35.sram_ctrl_ram_cfg.981004512
Short name T295
Test name
Test status
Simulation time 1416302027 ps
CPU time 14.3 seconds
Started Jan 10 01:27:49 PM PST 24
Finished Jan 10 01:29:06 PM PST 24
Peak memory 202272 kb
Host smart-b1e2ab8d-9b8c-4e22-a461-85cbcb531e1c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981004512 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.981004512
Directory /workspace/35.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/35.sram_ctrl_regwen.218450923
Short name T914
Test name
Test status
Simulation time 2316852903 ps
CPU time 35.15 seconds
Started Jan 10 01:28:00 PM PST 24
Finished Jan 10 01:29:40 PM PST 24
Peak memory 202156 kb
Host smart-f2238276-ac99-4a4c-a0e4-a75e78b9d0d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218450923 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.218450923
Directory /workspace/35.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/35.sram_ctrl_smoke.2709786897
Short name T269
Test name
Test status
Simulation time 2783357403 ps
CPU time 118.12 seconds
Started Jan 10 01:27:45 PM PST 24
Finished Jan 10 01:30:49 PM PST 24
Peak memory 371932 kb
Host smart-3a5b653e-cb95-4ef6-92a0-d5f20e75b0d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709786897 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.2709786897
Directory /workspace/35.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/35.sram_ctrl_stress_all.1993682264
Short name T566
Test name
Test status
Simulation time 498113948417 ps
CPU time 6146.4 seconds
Started Jan 10 01:27:40 PM PST 24
Finished Jan 10 03:10:34 PM PST 24
Peak memory 380164 kb
Host smart-972b8d5e-2497-4c03-9f12-315b8b3b235f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993682264 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 35.sram_ctrl_stress_all.1993682264
Directory /workspace/35.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.4289782326
Short name T804
Test name
Test status
Simulation time 1137237398 ps
CPU time 3456.91 seconds
Started Jan 10 01:27:41 PM PST 24
Finished Jan 10 02:25:54 PM PST 24
Peak memory 679932 kb
Host smart-e9e31c01-bce0-49ab-ad79-5fdaa457c1d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4289782326 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all_with_rand_reset.4289782326
Directory /workspace/35.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.sram_ctrl_stress_pipeline.2276617411
Short name T94
Test name
Test status
Simulation time 7103000865 ps
CPU time 288.61 seconds
Started Jan 10 01:27:42 PM PST 24
Finished Jan 10 01:33:19 PM PST 24
Peak memory 202200 kb
Host smart-1431ee3d-1e79-48ae-ab9b-2943200be0ae
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276617411 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.sram_ctrl_stress_pipeline.2276617411
Directory /workspace/35.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.64179647
Short name T587
Test name
Test status
Simulation time 749084977 ps
CPU time 43.49 seconds
Started Jan 10 01:27:53 PM PST 24
Finished Jan 10 01:29:38 PM PST 24
Peak memory 267516 kb
Host smart-4fe00935-e2ef-4589-bf34-4614bd6bf8c8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64179647 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.sram_ctrl_throughput_w_partial_write.64179647
Directory /workspace/35.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/36.sram_ctrl_access_during_key_req.3488202188
Short name T281
Test name
Test status
Simulation time 23236175258 ps
CPU time 1243.22 seconds
Started Jan 10 01:27:59 PM PST 24
Finished Jan 10 01:49:49 PM PST 24
Peak memory 380152 kb
Host smart-1e7c9f37-b1e7-4065-a5b0-61712958d977
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488202188 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 36.sram_ctrl_access_during_key_req.3488202188
Directory /workspace/36.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/36.sram_ctrl_alert_test.2245341373
Short name T705
Test name
Test status
Simulation time 23373204 ps
CPU time 0.64 seconds
Started Jan 10 01:27:41 PM PST 24
Finished Jan 10 01:28:31 PM PST 24
Peak memory 201920 kb
Host smart-e10651a6-a1c6-47ce-9cfb-f8023c9fd7cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245341373 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.sram_ctrl_alert_test.2245341373
Directory /workspace/36.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.sram_ctrl_bijection.3160387715
Short name T452
Test name
Test status
Simulation time 85243455989 ps
CPU time 1538.26 seconds
Started Jan 10 01:27:58 PM PST 24
Finished Jan 10 01:54:34 PM PST 24
Peak memory 202264 kb
Host smart-2d88c133-24f2-4093-8610-3fe4daf895b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160387715 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection
.3160387715
Directory /workspace/36.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/36.sram_ctrl_executable.3241327938
Short name T261
Test name
Test status
Simulation time 861058235 ps
CPU time 25.78 seconds
Started Jan 10 01:27:41 PM PST 24
Finished Jan 10 01:28:32 PM PST 24
Peak memory 254568 kb
Host smart-251bc862-107f-4ddf-abfe-c7f3962d056d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241327938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executab
le.3241327938
Directory /workspace/36.sram_ctrl_executable/latest

Test location /workspace/coverage/default/36.sram_ctrl_lc_escalation.2797993624
Short name T99
Test name
Test status
Simulation time 54774672472 ps
CPU time 183.53 seconds
Started Jan 10 01:27:42 PM PST 24
Finished Jan 10 01:31:34 PM PST 24
Peak memory 202228 kb
Host smart-915103e4-981a-4771-9361-3820cd26556f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797993624 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_lc_es
calation.2797993624
Directory /workspace/36.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/36.sram_ctrl_max_throughput.4163960138
Short name T733
Test name
Test status
Simulation time 1529019161 ps
CPU time 160.33 seconds
Started Jan 10 01:27:47 PM PST 24
Finished Jan 10 01:31:33 PM PST 24
Peak memory 365624 kb
Host smart-0ea58927-43b3-4af0-aba8-d6b4d07fe13d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163960138 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 36.sram_ctrl_max_throughput.4163960138
Directory /workspace/36.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/36.sram_ctrl_mem_partial_access.572756380
Short name T833
Test name
Test status
Simulation time 6442052670 ps
CPU time 127.57 seconds
Started Jan 10 01:27:54 PM PST 24
Finished Jan 10 01:31:00 PM PST 24
Peak memory 210544 kb
Host smart-1d1ed088-df27-4309-9a95-5164728e56ae
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572756380 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.sram_ctrl_mem_partial_access.572756380
Directory /workspace/36.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/36.sram_ctrl_mem_walk.2951680034
Short name T828
Test name
Test status
Simulation time 28778985454 ps
CPU time 140.06 seconds
Started Jan 10 01:27:54 PM PST 24
Finished Jan 10 01:31:24 PM PST 24
Peak memory 202160 kb
Host smart-fa6b9b2b-c07d-4ee0-ae45-c63b2f2ea799
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951680034 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctr
l_mem_walk.2951680034
Directory /workspace/36.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/36.sram_ctrl_multiple_keys.1341705332
Short name T322
Test name
Test status
Simulation time 14080881496 ps
CPU time 608.75 seconds
Started Jan 10 01:27:42 PM PST 24
Finished Jan 10 01:38:40 PM PST 24
Peak memory 380036 kb
Host smart-a4d39f78-ccb4-46d6-99e1-9d49dde2459c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341705332 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multi
ple_keys.1341705332
Directory /workspace/36.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/36.sram_ctrl_partial_access.331365783
Short name T954
Test name
Test status
Simulation time 2851102120 ps
CPU time 153.46 seconds
Started Jan 10 01:27:58 PM PST 24
Finished Jan 10 01:31:29 PM PST 24
Peak memory 375204 kb
Host smart-60cf0e4a-e188-464f-913f-46c97be958f1
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331365783 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.s
ram_ctrl_partial_access.331365783
Directory /workspace/36.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.829718952
Short name T119
Test name
Test status
Simulation time 54916366193 ps
CPU time 316.54 seconds
Started Jan 10 01:27:53 PM PST 24
Finished Jan 10 01:34:11 PM PST 24
Peak memory 202136 kb
Host smart-59b41c5e-e719-4a4a-9fdb-af26a8cfad91
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829718952 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.sram_ctrl_partial_access_b2b.829718952
Directory /workspace/36.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/36.sram_ctrl_regwen.2131013866
Short name T466
Test name
Test status
Simulation time 6058547212 ps
CPU time 194.61 seconds
Started Jan 10 01:28:11 PM PST 24
Finished Jan 10 01:32:20 PM PST 24
Peak memory 360592 kb
Host smart-b3a962c7-25af-4b51-b5c4-b05ecb3d19a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131013866 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.2131013866
Directory /workspace/36.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/36.sram_ctrl_stress_all.2068479609
Short name T631
Test name
Test status
Simulation time 305520108620 ps
CPU time 4614.55 seconds
Started Jan 10 01:27:57 PM PST 24
Finished Jan 10 02:45:48 PM PST 24
Peak memory 380172 kb
Host smart-638f04d9-0813-4a5e-952d-2cdd18e4e0f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068479609 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 36.sram_ctrl_stress_all.2068479609
Directory /workspace/36.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.207034264
Short name T655
Test name
Test status
Simulation time 3387209049 ps
CPU time 3522.64 seconds
Started Jan 10 01:27:53 PM PST 24
Finished Jan 10 02:27:38 PM PST 24
Peak memory 460384 kb
Host smart-6efa132d-e3a1-459f-a3e6-6aa621ecd425
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=207034264 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all_with_rand_reset.207034264
Directory /workspace/36.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.sram_ctrl_stress_pipeline.3491545234
Short name T931
Test name
Test status
Simulation time 6451869153 ps
CPU time 278.62 seconds
Started Jan 10 01:27:45 PM PST 24
Finished Jan 10 01:33:30 PM PST 24
Peak memory 202180 kb
Host smart-79e3c9d3-874e-46b6-9067-ede2bcaed52f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491545234 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.sram_ctrl_stress_pipeline.3491545234
Directory /workspace/36.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.457591641
Short name T277
Test name
Test status
Simulation time 3421522285 ps
CPU time 144.01 seconds
Started Jan 10 01:27:40 PM PST 24
Finished Jan 10 01:30:31 PM PST 24
Peak memory 371992 kb
Host smart-ec629c82-d879-4361-b936-e3473ac9f8c1
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457591641 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 36.sram_ctrl_throughput_w_partial_write.457591641
Directory /workspace/36.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/37.sram_ctrl_access_during_key_req.3954801666
Short name T879
Test name
Test status
Simulation time 3902888272 ps
CPU time 430.48 seconds
Started Jan 10 01:28:17 PM PST 24
Finished Jan 10 01:36:17 PM PST 24
Peak memory 359776 kb
Host smart-49e46bc0-691d-4078-b4c5-fd683f3e5249
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954801666 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 37.sram_ctrl_access_during_key_req.3954801666
Directory /workspace/37.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/37.sram_ctrl_alert_test.177624385
Short name T336
Test name
Test status
Simulation time 14006420 ps
CPU time 0.63 seconds
Started Jan 10 01:28:21 PM PST 24
Finished Jan 10 01:29:10 PM PST 24
Peak memory 201440 kb
Host smart-24e3aca6-0b9d-4c6e-bfd6-61675eec91a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177624385 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.sram_ctrl_alert_test.177624385
Directory /workspace/37.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.sram_ctrl_bijection.3404178678
Short name T962
Test name
Test status
Simulation time 8637537622 ps
CPU time 568 seconds
Started Jan 10 01:27:58 PM PST 24
Finished Jan 10 01:38:24 PM PST 24
Peak memory 202084 kb
Host smart-75ce37b4-7790-42e6-a3a5-0991c0814af3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404178678 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection
.3404178678
Directory /workspace/37.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/37.sram_ctrl_lc_escalation.3791495366
Short name T925
Test name
Test status
Simulation time 20934295381 ps
CPU time 67.23 seconds
Started Jan 10 01:28:17 PM PST 24
Finished Jan 10 01:30:14 PM PST 24
Peak memory 210412 kb
Host smart-7009e96d-4bbb-4958-9c41-18cc353fe991
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791495366 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_lc_es
calation.3791495366
Directory /workspace/37.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/37.sram_ctrl_max_throughput.3971751874
Short name T841
Test name
Test status
Simulation time 7358017880 ps
CPU time 71.15 seconds
Started Jan 10 01:28:15 PM PST 24
Finished Jan 10 01:30:18 PM PST 24
Peak memory 326992 kb
Host smart-f12e789f-7fd3-4f64-a2c2-d65c684c702d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971751874 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 37.sram_ctrl_max_throughput.3971751874
Directory /workspace/37.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/37.sram_ctrl_mem_partial_access.2284303354
Short name T558
Test name
Test status
Simulation time 4979911139 ps
CPU time 156.13 seconds
Started Jan 10 01:28:17 PM PST 24
Finished Jan 10 01:31:49 PM PST 24
Peak memory 211240 kb
Host smart-589014ce-4a1b-424f-b614-15aceaf5c5af
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284303354 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.sram_ctrl_mem_partial_access.2284303354
Directory /workspace/37.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/37.sram_ctrl_mem_walk.2335381111
Short name T792
Test name
Test status
Simulation time 7166863689 ps
CPU time 138.84 seconds
Started Jan 10 01:28:17 PM PST 24
Finished Jan 10 01:31:26 PM PST 24
Peak memory 202176 kb
Host smart-c7717ea5-81aa-4c4e-97b7-4ec1da20a8f8
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335381111 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctr
l_mem_walk.2335381111
Directory /workspace/37.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/37.sram_ctrl_multiple_keys.320566998
Short name T675
Test name
Test status
Simulation time 9371604563 ps
CPU time 488.34 seconds
Started Jan 10 01:27:42 PM PST 24
Finished Jan 10 01:36:39 PM PST 24
Peak memory 366688 kb
Host smart-8855b4ab-32da-4f27-a56d-248c3d26220b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320566998 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multip
le_keys.320566998
Directory /workspace/37.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/37.sram_ctrl_partial_access.2204707569
Short name T36
Test name
Test status
Simulation time 2116044544 ps
CPU time 25.61 seconds
Started Jan 10 01:28:13 PM PST 24
Finished Jan 10 01:29:36 PM PST 24
Peak memory 201988 kb
Host smart-b3c77a07-7509-4c38-a6dc-de3c262c4df7
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204707569 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
sram_ctrl_partial_access.2204707569
Directory /workspace/37.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.1307705781
Short name T725
Test name
Test status
Simulation time 31207265239 ps
CPU time 358.43 seconds
Started Jan 10 01:27:50 PM PST 24
Finished Jan 10 01:34:50 PM PST 24
Peak memory 202144 kb
Host smart-899a88f1-1f5e-48a0-bb2a-b982c192ec8f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307705781 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 37.sram_ctrl_partial_access_b2b.1307705781
Directory /workspace/37.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/37.sram_ctrl_ram_cfg.1746924511
Short name T802
Test name
Test status
Simulation time 2391591834 ps
CPU time 13.89 seconds
Started Jan 10 01:28:18 PM PST 24
Finished Jan 10 01:29:24 PM PST 24
Peak memory 202472 kb
Host smart-d27e9b16-5460-4344-98a5-a58f4e9de342
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746924511 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.1746924511
Directory /workspace/37.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/37.sram_ctrl_regwen.366434596
Short name T457
Test name
Test status
Simulation time 2508373328 ps
CPU time 80.67 seconds
Started Jan 10 01:28:17 PM PST 24
Finished Jan 10 01:30:24 PM PST 24
Peak memory 318568 kb
Host smart-6c0c316e-89a1-4585-9760-956eb5b106b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366434596 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.366434596
Directory /workspace/37.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/37.sram_ctrl_smoke.3709880826
Short name T612
Test name
Test status
Simulation time 2064743297 ps
CPU time 20.38 seconds
Started Jan 10 01:27:42 PM PST 24
Finished Jan 10 01:28:51 PM PST 24
Peak memory 202040 kb
Host smart-e95238f0-f62d-4bba-85aa-b6dd6373821b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709880826 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.3709880826
Directory /workspace/37.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/37.sram_ctrl_stress_all.362173474
Short name T732
Test name
Test status
Simulation time 118748564839 ps
CPU time 402.51 seconds
Started Jan 10 01:28:46 PM PST 24
Finished Jan 10 01:35:59 PM PST 24
Peak memory 346324 kb
Host smart-ac934747-5f9f-4452-997a-690c75d51f67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362173474 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 37.sram_ctrl_stress_all.362173474
Directory /workspace/37.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.1252193614
Short name T273
Test name
Test status
Simulation time 1197338706 ps
CPU time 3508.58 seconds
Started Jan 10 01:28:19 PM PST 24
Finished Jan 10 02:27:33 PM PST 24
Peak memory 410332 kb
Host smart-ef22d63c-9657-4d70-bd73-ab7d310d7d62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1252193614 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all_with_rand_reset.1252193614
Directory /workspace/37.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.sram_ctrl_stress_pipeline.3102392845
Short name T825
Test name
Test status
Simulation time 20273185132 ps
CPU time 348.77 seconds
Started Jan 10 01:28:09 PM PST 24
Finished Jan 10 01:34:53 PM PST 24
Peak memory 202152 kb
Host smart-647f5a58-233c-45bb-8984-16d862d887fc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102392845 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.sram_ctrl_stress_pipeline.3102392845
Directory /workspace/37.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.1244328247
Short name T126
Test name
Test status
Simulation time 1485839923 ps
CPU time 64.74 seconds
Started Jan 10 01:28:15 PM PST 24
Finished Jan 10 01:30:15 PM PST 24
Peak memory 314756 kb
Host smart-0eada069-1a84-4e99-92a2-4eaf623f21d4
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244328247 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 37.sram_ctrl_throughput_w_partial_write.1244328247
Directory /workspace/37.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/38.sram_ctrl_access_during_key_req.1897639766
Short name T886
Test name
Test status
Simulation time 74126684616 ps
CPU time 1134.53 seconds
Started Jan 10 01:29:01 PM PST 24
Finished Jan 10 01:48:17 PM PST 24
Peak memory 366732 kb
Host smart-5fdec454-2639-4ef1-9627-48e4bee70500
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897639766 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.sram_ctrl_access_during_key_req.1897639766
Directory /workspace/38.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/38.sram_ctrl_alert_test.1503604782
Short name T782
Test name
Test status
Simulation time 36212078 ps
CPU time 0.63 seconds
Started Jan 10 01:28:44 PM PST 24
Finished Jan 10 01:29:17 PM PST 24
Peak memory 201712 kb
Host smart-acc0597c-87b0-4915-899f-88c39c7f8098
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503604782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.sram_ctrl_alert_test.1503604782
Directory /workspace/38.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.sram_ctrl_bijection.3202441648
Short name T848
Test name
Test status
Simulation time 24271628205 ps
CPU time 547.02 seconds
Started Jan 10 01:28:57 PM PST 24
Finished Jan 10 01:38:29 PM PST 24
Peak memory 202220 kb
Host smart-ca74c263-f1fc-4480-b281-633505862d66
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202441648 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection
.3202441648
Directory /workspace/38.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/38.sram_ctrl_lc_escalation.2874618217
Short name T425
Test name
Test status
Simulation time 6843913027 ps
CPU time 66.84 seconds
Started Jan 10 01:29:01 PM PST 24
Finished Jan 10 01:30:30 PM PST 24
Peak memory 210252 kb
Host smart-633c2614-ed59-4ee6-be74-1ed002ef1f87
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874618217 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_es
calation.2874618217
Directory /workspace/38.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/38.sram_ctrl_max_throughput.3049495559
Short name T373
Test name
Test status
Simulation time 1452401507 ps
CPU time 36.98 seconds
Started Jan 10 01:28:15 PM PST 24
Finished Jan 10 01:29:47 PM PST 24
Peak memory 243404 kb
Host smart-1f73c319-7a02-46ce-8686-899a17cef604
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049495559 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 38.sram_ctrl_max_throughput.3049495559
Directory /workspace/38.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/38.sram_ctrl_mem_partial_access.3222746826
Short name T759
Test name
Test status
Simulation time 5043270338 ps
CPU time 143.1 seconds
Started Jan 10 01:28:20 PM PST 24
Finished Jan 10 01:31:28 PM PST 24
Peak memory 218496 kb
Host smart-c06026c2-c4a0-4dfc-b9f1-39133143628d
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222746826 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.sram_ctrl_mem_partial_access.3222746826
Directory /workspace/38.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/38.sram_ctrl_mem_walk.420835896
Short name T692
Test name
Test status
Simulation time 8220559017 ps
CPU time 120.11 seconds
Started Jan 10 01:28:43 PM PST 24
Finished Jan 10 01:31:16 PM PST 24
Peak memory 202084 kb
Host smart-237372e7-b8b3-4139-9a9b-ca44467c8652
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420835896 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl
_mem_walk.420835896
Directory /workspace/38.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/38.sram_ctrl_multiple_keys.488945800
Short name T624
Test name
Test status
Simulation time 8448605691 ps
CPU time 856.76 seconds
Started Jan 10 01:28:19 PM PST 24
Finished Jan 10 01:43:25 PM PST 24
Peak memory 380176 kb
Host smart-d3888b73-4d14-409c-adbe-4606984cc971
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488945800 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multip
le_keys.488945800
Directory /workspace/38.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/38.sram_ctrl_partial_access.905695654
Short name T14
Test name
Test status
Simulation time 1254872266 ps
CPU time 21.52 seconds
Started Jan 10 01:28:21 PM PST 24
Finished Jan 10 01:29:31 PM PST 24
Peak memory 202092 kb
Host smart-7f49b51f-ca89-4d55-ab78-865f6638c815
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905695654 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.s
ram_ctrl_partial_access.905695654
Directory /workspace/38.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.2163714707
Short name T378
Test name
Test status
Simulation time 134363654402 ps
CPU time 452.98 seconds
Started Jan 10 01:28:55 PM PST 24
Finished Jan 10 01:36:54 PM PST 24
Peak memory 202184 kb
Host smart-fd367457-c90c-45d4-a27b-e9ab6cfc195c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163714707 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 38.sram_ctrl_partial_access_b2b.2163714707
Directory /workspace/38.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/38.sram_ctrl_ram_cfg.397478341
Short name T288
Test name
Test status
Simulation time 1408201859 ps
CPU time 7.05 seconds
Started Jan 10 01:28:34 PM PST 24
Finished Jan 10 01:29:19 PM PST 24
Peak memory 202136 kb
Host smart-be55bfcd-bd62-41c5-b2c7-84d45f761a11
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397478341 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.397478341
Directory /workspace/38.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/38.sram_ctrl_regwen.3053746852
Short name T707
Test name
Test status
Simulation time 58077152846 ps
CPU time 853.9 seconds
Started Jan 10 01:28:35 PM PST 24
Finished Jan 10 01:43:26 PM PST 24
Peak memory 380132 kb
Host smart-1854f528-9cb8-4215-be66-49b9e7e9e2ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053746852 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.3053746852
Directory /workspace/38.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/38.sram_ctrl_smoke.3527594147
Short name T650
Test name
Test status
Simulation time 745567749 ps
CPU time 32.09 seconds
Started Jan 10 01:28:14 PM PST 24
Finished Jan 10 01:29:41 PM PST 24
Peak memory 288916 kb
Host smart-59658b48-315c-453f-96d3-a956c0279b0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527594147 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.3527594147
Directory /workspace/38.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/38.sram_ctrl_stress_all.4258383388
Short name T5
Test name
Test status
Simulation time 1275452371427 ps
CPU time 5113.62 seconds
Started Jan 10 01:28:22 PM PST 24
Finished Jan 10 02:54:22 PM PST 24
Peak memory 203672 kb
Host smart-55732186-ce8f-4110-b968-8c1e4b251aec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258383388 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 38.sram_ctrl_stress_all.4258383388
Directory /workspace/38.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.2457814621
Short name T561
Test name
Test status
Simulation time 332233584 ps
CPU time 1632.7 seconds
Started Jan 10 01:28:44 PM PST 24
Finished Jan 10 01:56:29 PM PST 24
Peak memory 690284 kb
Host smart-a352ef50-83ca-4e7c-a69c-312d5c69f5ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2457814621 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all_with_rand_reset.2457814621
Directory /workspace/38.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.sram_ctrl_stress_pipeline.3497329526
Short name T311
Test name
Test status
Simulation time 20995884771 ps
CPU time 415.94 seconds
Started Jan 10 01:28:19 PM PST 24
Finished Jan 10 01:36:04 PM PST 24
Peak memory 202152 kb
Host smart-51845984-fe58-4548-8f5c-fccc8ea1e17a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497329526 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.sram_ctrl_stress_pipeline.3497329526
Directory /workspace/38.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.4152120460
Short name T866
Test name
Test status
Simulation time 3087348535 ps
CPU time 138.46 seconds
Started Jan 10 01:29:01 PM PST 24
Finished Jan 10 01:31:41 PM PST 24
Peak memory 353820 kb
Host smart-3eaf306e-49e0-4db4-932a-cf64ca4c9786
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152120460 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 38.sram_ctrl_throughput_w_partial_write.4152120460
Directory /workspace/38.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/39.sram_ctrl_access_during_key_req.3938454852
Short name T697
Test name
Test status
Simulation time 9142126716 ps
CPU time 1441.71 seconds
Started Jan 10 01:27:59 PM PST 24
Finished Jan 10 01:53:07 PM PST 24
Peak memory 379072 kb
Host smart-21101c1f-1871-45e4-a1e3-e558d3f350b7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938454852 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.sram_ctrl_access_during_key_req.3938454852
Directory /workspace/39.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/39.sram_ctrl_alert_test.385806727
Short name T605
Test name
Test status
Simulation time 42216231 ps
CPU time 0.63 seconds
Started Jan 10 01:27:57 PM PST 24
Finished Jan 10 01:28:56 PM PST 24
Peak memory 201488 kb
Host smart-5d93fe35-e0f1-4e11-aacf-0f306db636ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385806727 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.sram_ctrl_alert_test.385806727
Directory /workspace/39.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.sram_ctrl_bijection.3507941429
Short name T769
Test name
Test status
Simulation time 93108470995 ps
CPU time 2097.53 seconds
Started Jan 10 01:28:52 PM PST 24
Finished Jan 10 02:04:17 PM PST 24
Peak memory 202160 kb
Host smart-357578be-79aa-4385-8d4c-ef7ece1c17fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507941429 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection
.3507941429
Directory /workspace/39.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/39.sram_ctrl_executable.3472267652
Short name T111
Test name
Test status
Simulation time 34432999388 ps
CPU time 861.73 seconds
Started Jan 10 01:27:48 PM PST 24
Finished Jan 10 01:43:18 PM PST 24
Peak memory 375928 kb
Host smart-552dc60c-31d6-4001-85c6-cb40a05d6759
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472267652 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_executab
le.3472267652
Directory /workspace/39.sram_ctrl_executable/latest

Test location /workspace/coverage/default/39.sram_ctrl_lc_escalation.1206059087
Short name T447
Test name
Test status
Simulation time 23775494219 ps
CPU time 66.08 seconds
Started Jan 10 01:28:00 PM PST 24
Finished Jan 10 01:30:13 PM PST 24
Peak memory 210396 kb
Host smart-2de72bfe-5b03-4e46-a0c1-cd64f3fd8868
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206059087 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_es
calation.1206059087
Directory /workspace/39.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/39.sram_ctrl_max_throughput.1178071705
Short name T10
Test name
Test status
Simulation time 1474575771 ps
CPU time 67.45 seconds
Started Jan 10 01:28:52 PM PST 24
Finished Jan 10 01:30:26 PM PST 24
Peak memory 322684 kb
Host smart-02a0e8d2-1302-4bc7-917f-09ff8bd64c30
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178071705 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 39.sram_ctrl_max_throughput.1178071705
Directory /workspace/39.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/39.sram_ctrl_mem_partial_access.3102446954
Short name T530
Test name
Test status
Simulation time 11114658026 ps
CPU time 78.07 seconds
Started Jan 10 01:28:01 PM PST 24
Finished Jan 10 01:30:23 PM PST 24
Peak memory 211260 kb
Host smart-53bfc3f5-fe3e-4e4b-becf-33766a042de5
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102446954 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.sram_ctrl_mem_partial_access.3102446954
Directory /workspace/39.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/39.sram_ctrl_mem_walk.3514008932
Short name T345
Test name
Test status
Simulation time 8574385747 ps
CPU time 123.62 seconds
Started Jan 10 01:27:57 PM PST 24
Finished Jan 10 01:30:57 PM PST 24
Peak memory 202200 kb
Host smart-c0832e2f-e30a-48ef-a4f9-b87ffdb26c00
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514008932 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctr
l_mem_walk.3514008932
Directory /workspace/39.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/39.sram_ctrl_multiple_keys.3085881569
Short name T229
Test name
Test status
Simulation time 8339471981 ps
CPU time 549.8 seconds
Started Jan 10 01:28:52 PM PST 24
Finished Jan 10 01:38:29 PM PST 24
Peak memory 369960 kb
Host smart-485a673c-232b-4cd7-b69c-53840a14858e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085881569 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multi
ple_keys.3085881569
Directory /workspace/39.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/39.sram_ctrl_partial_access.1464315059
Short name T598
Test name
Test status
Simulation time 629833349 ps
CPU time 21.98 seconds
Started Jan 10 01:28:52 PM PST 24
Finished Jan 10 01:29:41 PM PST 24
Peak memory 261400 kb
Host smart-229d606c-ebfa-4faf-80ae-1d33a6a2a57c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464315059 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
sram_ctrl_partial_access.1464315059
Directory /workspace/39.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.3307103193
Short name T958
Test name
Test status
Simulation time 6983994010 ps
CPU time 449.23 seconds
Started Jan 10 01:28:53 PM PST 24
Finished Jan 10 01:36:48 PM PST 24
Peak memory 201892 kb
Host smart-ec578f2e-7541-4fec-8b01-905fc757dc20
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307103193 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 39.sram_ctrl_partial_access_b2b.3307103193
Directory /workspace/39.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/39.sram_ctrl_ram_cfg.1927413628
Short name T670
Test name
Test status
Simulation time 1794258745 ps
CPU time 13.4 seconds
Started Jan 10 01:27:41 PM PST 24
Finished Jan 10 01:28:23 PM PST 24
Peak memory 202460 kb
Host smart-d9a71f94-72a0-4ec7-9354-cfc29753fd93
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927413628 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.1927413628
Directory /workspace/39.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/39.sram_ctrl_smoke.3576409363
Short name T284
Test name
Test status
Simulation time 1588061788 ps
CPU time 56.96 seconds
Started Jan 10 01:28:20 PM PST 24
Finished Jan 10 01:30:01 PM PST 24
Peak memory 324944 kb
Host smart-ff226021-f616-4c51-a979-a2160f76b89f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576409363 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.3576409363
Directory /workspace/39.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/39.sram_ctrl_stress_all.664122932
Short name T752
Test name
Test status
Simulation time 162379764842 ps
CPU time 1747.27 seconds
Started Jan 10 01:28:12 PM PST 24
Finished Jan 10 01:58:15 PM PST 24
Peak memory 361688 kb
Host smart-41943bb0-69c9-4389-b1cd-101baf449d44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664122932 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 39.sram_ctrl_stress_all.664122932
Directory /workspace/39.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.2059613234
Short name T230
Test name
Test status
Simulation time 2233028588 ps
CPU time 5593.25 seconds
Started Jan 10 01:28:01 PM PST 24
Finished Jan 10 03:02:20 PM PST 24
Peak memory 632352 kb
Host smart-9a3357e6-2d7a-49f1-9b10-fe7425d73648
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2059613234 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all_with_rand_reset.2059613234
Directory /workspace/39.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.sram_ctrl_stress_pipeline.3858144949
Short name T412
Test name
Test status
Simulation time 9929437696 ps
CPU time 375.8 seconds
Started Jan 10 01:28:51 PM PST 24
Finished Jan 10 01:35:34 PM PST 24
Peak memory 202192 kb
Host smart-dd27c690-1613-429a-bade-054086aa64fd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858144949 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.sram_ctrl_stress_pipeline.3858144949
Directory /workspace/39.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.2649841103
Short name T326
Test name
Test status
Simulation time 1496009675 ps
CPU time 72.14 seconds
Started Jan 10 01:27:49 PM PST 24
Finished Jan 10 01:30:04 PM PST 24
Peak memory 310492 kb
Host smart-06db0f03-cfce-4426-b1fe-859c34417c37
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649841103 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 39.sram_ctrl_throughput_w_partial_write.2649841103
Directory /workspace/39.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/4.sram_ctrl_access_during_key_req.1564233663
Short name T700
Test name
Test status
Simulation time 35009499365 ps
CPU time 458.45 seconds
Started Jan 10 01:26:25 PM PST 24
Finished Jan 10 01:34:19 PM PST 24
Peak memory 375972 kb
Host smart-fd0998b7-8beb-491c-86e2-dad24768e032
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564233663 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.sram_ctrl_access_during_key_req.1564233663
Directory /workspace/4.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/4.sram_ctrl_alert_test.1464443253
Short name T560
Test name
Test status
Simulation time 49829044 ps
CPU time 0.63 seconds
Started Jan 10 01:26:31 PM PST 24
Finished Jan 10 01:26:44 PM PST 24
Peak memory 201836 kb
Host smart-7e1a838c-a3d9-4d1d-bfc9-c1bf0a98d6f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464443253 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.sram_ctrl_alert_test.1464443253
Directory /workspace/4.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.sram_ctrl_bijection.2880850672
Short name T397
Test name
Test status
Simulation time 161894144828 ps
CPU time 2690.84 seconds
Started Jan 10 01:26:36 PM PST 24
Finished Jan 10 02:11:42 PM PST 24
Peak memory 202136 kb
Host smart-a5e9f7f6-5461-4efc-97c2-ae8ed580d7d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880850672 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection.
2880850672
Directory /workspace/4.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/4.sram_ctrl_executable.1372906861
Short name T109
Test name
Test status
Simulation time 51292167754 ps
CPU time 1330.8 seconds
Started Jan 10 01:26:41 PM PST 24
Finished Jan 10 01:49:07 PM PST 24
Peak memory 378932 kb
Host smart-fa20e962-ecd9-4890-b613-8c758802a78e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372906861 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_executabl
e.1372906861
Directory /workspace/4.sram_ctrl_executable/latest

Test location /workspace/coverage/default/4.sram_ctrl_lc_escalation.3952625699
Short name T644
Test name
Test status
Simulation time 62980040522 ps
CPU time 159.84 seconds
Started Jan 10 01:26:27 PM PST 24
Finished Jan 10 01:29:21 PM PST 24
Peak memory 202168 kb
Host smart-2f404fe9-e2fc-44ec-b586-fed0cd4473ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952625699 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_esc
alation.3952625699
Directory /workspace/4.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/4.sram_ctrl_max_throughput.1899384425
Short name T827
Test name
Test status
Simulation time 755500279 ps
CPU time 61.83 seconds
Started Jan 10 01:26:34 PM PST 24
Finished Jan 10 01:27:50 PM PST 24
Peak memory 291656 kb
Host smart-78bf08b1-b46b-418b-bd20-1a331da072b6
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899384425 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 4.sram_ctrl_max_throughput.1899384425
Directory /workspace/4.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/4.sram_ctrl_mem_partial_access.829118536
Short name T683
Test name
Test status
Simulation time 52229781115 ps
CPU time 88.96 seconds
Started Jan 10 01:26:32 PM PST 24
Finished Jan 10 01:28:14 PM PST 24
Peak memory 211324 kb
Host smart-7bce7339-9436-40bc-bcf8-c48437784761
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829118536 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
sram_ctrl_mem_partial_access.829118536
Directory /workspace/4.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/4.sram_ctrl_mem_walk.2274407911
Short name T966
Test name
Test status
Simulation time 178806540575 ps
CPU time 178.37 seconds
Started Jan 10 01:26:36 PM PST 24
Finished Jan 10 01:29:50 PM PST 24
Peak memory 202228 kb
Host smart-a819f518-ee90-4d29-8d53-123569145df5
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274407911 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl
_mem_walk.2274407911
Directory /workspace/4.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/4.sram_ctrl_multiple_keys.1363433748
Short name T934
Test name
Test status
Simulation time 16499414273 ps
CPU time 1341.12 seconds
Started Jan 10 01:26:32 PM PST 24
Finished Jan 10 01:49:06 PM PST 24
Peak memory 380144 kb
Host smart-ed711d11-3a9a-4d7a-93eb-7ab8fe47b99f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363433748 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multip
le_keys.1363433748
Directory /workspace/4.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/4.sram_ctrl_partial_access.3456352601
Short name T649
Test name
Test status
Simulation time 1616892832 ps
CPU time 17.95 seconds
Started Jan 10 01:26:27 PM PST 24
Finished Jan 10 01:26:59 PM PST 24
Peak memory 202044 kb
Host smart-5423025f-7acc-4fb9-b498-1f02c73e03d4
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456352601 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.s
ram_ctrl_partial_access.3456352601
Directory /workspace/4.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.1569697934
Short name T248
Test name
Test status
Simulation time 79517059937 ps
CPU time 327.65 seconds
Started Jan 10 01:26:37 PM PST 24
Finished Jan 10 01:32:20 PM PST 24
Peak memory 202216 kb
Host smart-8a990a18-a42c-46b1-bdf2-da8afca8348e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569697934 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 4.sram_ctrl_partial_access_b2b.1569697934
Directory /workspace/4.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/4.sram_ctrl_ram_cfg.4043483364
Short name T533
Test name
Test status
Simulation time 4817091601 ps
CPU time 7.78 seconds
Started Jan 10 01:26:26 PM PST 24
Finished Jan 10 01:26:49 PM PST 24
Peak memory 202452 kb
Host smart-e70952b2-2d94-4845-9d69-418998eee42c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043483364 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.4043483364
Directory /workspace/4.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/4.sram_ctrl_regwen.434111943
Short name T502
Test name
Test status
Simulation time 48717633773 ps
CPU time 983.01 seconds
Started Jan 10 01:26:22 PM PST 24
Finished Jan 10 01:43:02 PM PST 24
Peak memory 377808 kb
Host smart-ab661f6e-3727-4001-99d0-93cc7f9f4adb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434111943 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.434111943
Directory /workspace/4.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/4.sram_ctrl_sec_cm.2681049922
Short name T23
Test name
Test status
Simulation time 142571365 ps
CPU time 2 seconds
Started Jan 10 01:26:27 PM PST 24
Finished Jan 10 01:26:43 PM PST 24
Peak memory 232116 kb
Host smart-e3828b00-51dc-47f4-985b-74e5e05e7530
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681049922 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.sram_ctrl_sec_cm.2681049922
Directory /workspace/4.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.sram_ctrl_smoke.4166648034
Short name T417
Test name
Test status
Simulation time 5060192692 ps
CPU time 23.73 seconds
Started Jan 10 01:26:24 PM PST 24
Finished Jan 10 01:27:03 PM PST 24
Peak memory 202164 kb
Host smart-de49d192-f29b-48a2-9175-615fca636390
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166648034 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.4166648034
Directory /workspace/4.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/4.sram_ctrl_stress_all.2849024540
Short name T477
Test name
Test status
Simulation time 260651934719 ps
CPU time 7492.09 seconds
Started Jan 10 01:26:34 PM PST 24
Finished Jan 10 03:31:41 PM PST 24
Peak memory 380448 kb
Host smart-39d70d40-6805-45d0-99af-93ff5a1d32d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849024540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 4.sram_ctrl_stress_all.2849024540
Directory /workspace/4.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.1534225461
Short name T602
Test name
Test status
Simulation time 1160180704 ps
CPU time 663.93 seconds
Started Jan 10 01:26:25 PM PST 24
Finished Jan 10 01:37:44 PM PST 24
Peak memory 390184 kb
Host smart-369371b0-676b-4b36-98d5-ca2248c3681c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1534225461 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all_with_rand_reset.1534225461
Directory /workspace/4.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.sram_ctrl_stress_pipeline.4020184304
Short name T723
Test name
Test status
Simulation time 7643015782 ps
CPU time 299.04 seconds
Started Jan 10 01:26:21 PM PST 24
Finished Jan 10 01:31:37 PM PST 24
Peak memory 202108 kb
Host smart-ac42a020-9973-473a-bfc1-8718f0dce271
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020184304 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.sram_ctrl_stress_pipeline.4020184304
Directory /workspace/4.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.640010387
Short name T704
Test name
Test status
Simulation time 2820010745 ps
CPU time 28.98 seconds
Started Jan 10 01:26:20 PM PST 24
Finished Jan 10 01:27:07 PM PST 24
Peak memory 217532 kb
Host smart-7befb793-a0d5-4b7d-bd79-5676f1ffdc95
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640010387 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 4.sram_ctrl_throughput_w_partial_write.640010387
Directory /workspace/4.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/40.sram_ctrl_access_during_key_req.890984131
Short name T939
Test name
Test status
Simulation time 6089203625 ps
CPU time 1267.92 seconds
Started Jan 10 01:27:59 PM PST 24
Finished Jan 10 01:50:13 PM PST 24
Peak memory 380148 kb
Host smart-dc7222a1-9579-4ec5-8ead-2c09fa40c627
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890984131 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 40.sram_ctrl_access_during_key_req.890984131
Directory /workspace/40.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/40.sram_ctrl_alert_test.676977542
Short name T220
Test name
Test status
Simulation time 14748258 ps
CPU time 0.64 seconds
Started Jan 10 01:28:08 PM PST 24
Finished Jan 10 01:29:10 PM PST 24
Peak memory 201768 kb
Host smart-024472bc-56fd-48c6-a058-986e9cef1802
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676977542 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.sram_ctrl_alert_test.676977542
Directory /workspace/40.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.sram_ctrl_bijection.4173358064
Short name T516
Test name
Test status
Simulation time 27870464787 ps
CPU time 603.62 seconds
Started Jan 10 01:28:10 PM PST 24
Finished Jan 10 01:39:07 PM PST 24
Peak memory 202092 kb
Host smart-bff2fd94-d9e7-48a1-a84e-b2011b65e81a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173358064 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection
.4173358064
Directory /workspace/40.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/40.sram_ctrl_executable.2212900095
Short name T355
Test name
Test status
Simulation time 29436168415 ps
CPU time 231.04 seconds
Started Jan 10 01:28:17 PM PST 24
Finished Jan 10 01:33:03 PM PST 24
Peak memory 375992 kb
Host smart-4d837b70-a230-4f23-8f83-e8347e473535
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212900095 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_executab
le.2212900095
Directory /workspace/40.sram_ctrl_executable/latest

Test location /workspace/coverage/default/40.sram_ctrl_lc_escalation.824136267
Short name T463
Test name
Test status
Simulation time 42538342549 ps
CPU time 354.97 seconds
Started Jan 10 01:28:09 PM PST 24
Finished Jan 10 01:35:03 PM PST 24
Peak memory 202232 kb
Host smart-a5a69cdc-6ae5-498f-8840-c1f99e27bbd2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824136267 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_esc
alation.824136267
Directory /workspace/40.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/40.sram_ctrl_max_throughput.2416374031
Short name T247
Test name
Test status
Simulation time 833825764 ps
CPU time 98.37 seconds
Started Jan 10 01:28:12 PM PST 24
Finished Jan 10 01:30:44 PM PST 24
Peak memory 327936 kb
Host smart-e9f61a64-35f3-4d7b-88dc-7a0ba2f7e243
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416374031 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 40.sram_ctrl_max_throughput.2416374031
Directory /workspace/40.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/40.sram_ctrl_mem_partial_access.4289511764
Short name T38
Test name
Test status
Simulation time 37302621748 ps
CPU time 85.04 seconds
Started Jan 10 01:28:16 PM PST 24
Finished Jan 10 01:30:30 PM PST 24
Peak memory 211360 kb
Host smart-d01482bb-80df-44bd-8b72-abb8ca907b2f
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289511764 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.sram_ctrl_mem_partial_access.4289511764
Directory /workspace/40.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/40.sram_ctrl_mem_walk.3725887525
Short name T790
Test name
Test status
Simulation time 86154543591 ps
CPU time 340.3 seconds
Started Jan 10 01:28:17 PM PST 24
Finished Jan 10 01:34:47 PM PST 24
Peak memory 202224 kb
Host smart-e68fc62a-1c01-4b8c-9242-5855137033a9
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725887525 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctr
l_mem_walk.3725887525
Directory /workspace/40.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/40.sram_ctrl_multiple_keys.1948636835
Short name T235
Test name
Test status
Simulation time 1688316972 ps
CPU time 64.79 seconds
Started Jan 10 01:28:16 PM PST 24
Finished Jan 10 01:30:11 PM PST 24
Peak memory 307324 kb
Host smart-0fb725bf-10da-4d4b-b081-9682412ab956
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948636835 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multi
ple_keys.1948636835
Directory /workspace/40.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/40.sram_ctrl_partial_access.3714334800
Short name T226
Test name
Test status
Simulation time 3942004556 ps
CPU time 43.49 seconds
Started Jan 10 01:28:07 PM PST 24
Finished Jan 10 01:29:48 PM PST 24
Peak memory 202068 kb
Host smart-5cb25332-183e-4d45-a209-b497fe38b1f9
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714334800 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
sram_ctrl_partial_access.3714334800
Directory /workspace/40.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.2281795465
Short name T829
Test name
Test status
Simulation time 26824657970 ps
CPU time 416.43 seconds
Started Jan 10 01:28:01 PM PST 24
Finished Jan 10 01:36:02 PM PST 24
Peak memory 202212 kb
Host smart-9ee38980-0a79-463b-a83d-089930855130
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281795465 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 40.sram_ctrl_partial_access_b2b.2281795465
Directory /workspace/40.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/40.sram_ctrl_ram_cfg.2046112153
Short name T770
Test name
Test status
Simulation time 1553544639 ps
CPU time 5.65 seconds
Started Jan 10 01:28:13 PM PST 24
Finished Jan 10 01:29:10 PM PST 24
Peak memory 202396 kb
Host smart-5ca937bb-d815-44ac-86d7-cb1f117b8cce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046112153 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.2046112153
Directory /workspace/40.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/40.sram_ctrl_regwen.3717264159
Short name T470
Test name
Test status
Simulation time 9013390027 ps
CPU time 596.29 seconds
Started Jan 10 01:27:59 PM PST 24
Finished Jan 10 01:38:53 PM PST 24
Peak memory 378004 kb
Host smart-3fbaf63c-d80d-4218-bb65-15b8048f1976
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717264159 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.3717264159
Directory /workspace/40.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/40.sram_ctrl_smoke.2155238110
Short name T479
Test name
Test status
Simulation time 1348722013 ps
CPU time 131.95 seconds
Started Jan 10 01:28:10 PM PST 24
Finished Jan 10 01:31:16 PM PST 24
Peak memory 371836 kb
Host smart-7b23ad90-989a-4154-9c4d-b1948c0ee7ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155238110 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.2155238110
Directory /workspace/40.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.1049026032
Short name T264
Test name
Test status
Simulation time 1077784336 ps
CPU time 4288.26 seconds
Started Jan 10 01:28:15 PM PST 24
Finished Jan 10 02:40:39 PM PST 24
Peak memory 461892 kb
Host smart-3fc774bb-816a-44ec-b786-013e58d58e56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1049026032 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all_with_rand_reset.1049026032
Directory /workspace/40.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.sram_ctrl_stress_pipeline.3657348734
Short name T56
Test name
Test status
Simulation time 7756236598 ps
CPU time 435.08 seconds
Started Jan 10 01:28:01 PM PST 24
Finished Jan 10 01:36:21 PM PST 24
Peak memory 202180 kb
Host smart-22ac3aa8-9f11-4065-b717-a757c98c6030
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657348734 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.sram_ctrl_stress_pipeline.3657348734
Directory /workspace/40.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.3552329549
Short name T797
Test name
Test status
Simulation time 745108539 ps
CPU time 37.74 seconds
Started Jan 10 01:28:14 PM PST 24
Finished Jan 10 01:29:47 PM PST 24
Peak memory 261364 kb
Host smart-c8474e6d-4c20-4a71-89ed-179674ad3202
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552329549 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 40.sram_ctrl_throughput_w_partial_write.3552329549
Directory /workspace/40.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/41.sram_ctrl_access_during_key_req.411964290
Short name T567
Test name
Test status
Simulation time 36267067188 ps
CPU time 1224.1 seconds
Started Jan 10 01:27:59 PM PST 24
Finished Jan 10 01:49:21 PM PST 24
Peak memory 373984 kb
Host smart-9e61059c-8a93-494d-9fc5-ab5b64a90534
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411964290 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 41.sram_ctrl_access_during_key_req.411964290
Directory /workspace/41.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/41.sram_ctrl_alert_test.420595367
Short name T950
Test name
Test status
Simulation time 26141382 ps
CPU time 0.63 seconds
Started Jan 10 01:28:16 PM PST 24
Finished Jan 10 01:29:06 PM PST 24
Peak memory 201880 kb
Host smart-034246b7-f21c-46d3-924f-66b4f2c857e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420595367 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.sram_ctrl_alert_test.420595367
Directory /workspace/41.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.sram_ctrl_bijection.4072966788
Short name T834
Test name
Test status
Simulation time 132503631347 ps
CPU time 2257.02 seconds
Started Jan 10 01:28:01 PM PST 24
Finished Jan 10 02:06:43 PM PST 24
Peak memory 202196 kb
Host smart-be92eaaf-4149-47d4-89d3-e002740094fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072966788 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection
.4072966788
Directory /workspace/41.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/41.sram_ctrl_lc_escalation.2493061824
Short name T852
Test name
Test status
Simulation time 25830646154 ps
CPU time 59.63 seconds
Started Jan 10 01:28:17 PM PST 24
Finished Jan 10 01:30:12 PM PST 24
Peak memory 210308 kb
Host smart-de5933cb-6ec4-4c4f-97db-a645eb58102d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493061824 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_es
calation.2493061824
Directory /workspace/41.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/41.sram_ctrl_max_throughput.1076115578
Short name T464
Test name
Test status
Simulation time 2834178931 ps
CPU time 42.22 seconds
Started Jan 10 01:28:11 PM PST 24
Finished Jan 10 01:29:50 PM PST 24
Peak memory 272764 kb
Host smart-eb02752c-fb2a-447a-9d1c-3411e1017546
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076115578 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 41.sram_ctrl_max_throughput.1076115578
Directory /workspace/41.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/41.sram_ctrl_mem_partial_access.973205116
Short name T938
Test name
Test status
Simulation time 3762363598 ps
CPU time 73.99 seconds
Started Jan 10 01:28:01 PM PST 24
Finished Jan 10 01:30:18 PM PST 24
Peak memory 211204 kb
Host smart-337c87a7-dc76-4577-b8fa-a834cda00778
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973205116 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.sram_ctrl_mem_partial_access.973205116
Directory /workspace/41.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/41.sram_ctrl_mem_walk.4212046665
Short name T528
Test name
Test status
Simulation time 7182423432 ps
CPU time 143.47 seconds
Started Jan 10 01:28:09 PM PST 24
Finished Jan 10 01:31:31 PM PST 24
Peak memory 202248 kb
Host smart-c0f17bcd-6478-49ef-b8fd-9b7c8e91641e
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212046665 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctr
l_mem_walk.4212046665
Directory /workspace/41.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/41.sram_ctrl_multiple_keys.2457375626
Short name T908
Test name
Test status
Simulation time 11932589216 ps
CPU time 982.48 seconds
Started Jan 10 01:28:00 PM PST 24
Finished Jan 10 01:45:28 PM PST 24
Peak memory 376040 kb
Host smart-7c1d7e8b-979d-4e56-bf75-172afcde673c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457375626 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multi
ple_keys.2457375626
Directory /workspace/41.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/41.sram_ctrl_partial_access.2462134368
Short name T895
Test name
Test status
Simulation time 767227677 ps
CPU time 17.52 seconds
Started Jan 10 01:28:14 PM PST 24
Finished Jan 10 01:29:27 PM PST 24
Peak memory 243420 kb
Host smart-ea7dbd2e-3669-4cf1-95c7-c2a2d1ede6df
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462134368 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
sram_ctrl_partial_access.2462134368
Directory /workspace/41.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.1401620122
Short name T314
Test name
Test status
Simulation time 181106542864 ps
CPU time 476.51 seconds
Started Jan 10 01:28:01 PM PST 24
Finished Jan 10 01:37:03 PM PST 24
Peak memory 202108 kb
Host smart-0f12f9a5-1bfb-4538-a2e9-ccde39a8db00
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401620122 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 41.sram_ctrl_partial_access_b2b.1401620122
Directory /workspace/41.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/41.sram_ctrl_ram_cfg.3903638897
Short name T445
Test name
Test status
Simulation time 1354286103 ps
CPU time 13.67 seconds
Started Jan 10 01:28:17 PM PST 24
Finished Jan 10 01:29:20 PM PST 24
Peak memory 202324 kb
Host smart-d028b97d-6990-4352-a089-4d37950fb91e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903638897 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.3903638897
Directory /workspace/41.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/41.sram_ctrl_regwen.3553687631
Short name T108
Test name
Test status
Simulation time 4145631388 ps
CPU time 1190.32 seconds
Started Jan 10 01:28:18 PM PST 24
Finished Jan 10 01:48:59 PM PST 24
Peak memory 380060 kb
Host smart-0889b1b9-9f20-492e-a0d7-fe0534f9f9bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553687631 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.3553687631
Directory /workspace/41.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/41.sram_ctrl_smoke.4083788528
Short name T253
Test name
Test status
Simulation time 369677316 ps
CPU time 19.47 seconds
Started Jan 10 01:28:11 PM PST 24
Finished Jan 10 01:29:25 PM PST 24
Peak memory 232940 kb
Host smart-667fa6b3-b482-4321-bc97-d10d2b71f8c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083788528 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.4083788528
Directory /workspace/41.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.1792983028
Short name T443
Test name
Test status
Simulation time 1306795085 ps
CPU time 4569.67 seconds
Started Jan 10 01:28:10 PM PST 24
Finished Jan 10 02:45:15 PM PST 24
Peak memory 633468 kb
Host smart-f3abc542-b766-4526-ba91-c3d138f0d86c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1792983028 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all_with_rand_reset.1792983028
Directory /workspace/41.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.sram_ctrl_stress_pipeline.591051384
Short name T842
Test name
Test status
Simulation time 61784313947 ps
CPU time 411.34 seconds
Started Jan 10 01:28:17 PM PST 24
Finished Jan 10 01:35:58 PM PST 24
Peak memory 202148 kb
Host smart-966439ec-b7e2-4157-9175-f9b352be32de
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591051384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.sram_ctrl_stress_pipeline.591051384
Directory /workspace/41.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.120047030
Short name T409
Test name
Test status
Simulation time 818148474 ps
CPU time 113.19 seconds
Started Jan 10 01:27:58 PM PST 24
Finished Jan 10 01:30:49 PM PST 24
Peak memory 366768 kb
Host smart-47a06053-93f7-4404-b6f0-30a0bff7c640
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120047030 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 41.sram_ctrl_throughput_w_partial_write.120047030
Directory /workspace/41.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/42.sram_ctrl_access_during_key_req.65176839
Short name T375
Test name
Test status
Simulation time 16596541372 ps
CPU time 1146 seconds
Started Jan 10 01:28:16 PM PST 24
Finished Jan 10 01:48:11 PM PST 24
Peak memory 380380 kb
Host smart-e08186fd-9363-4ff0-9459-1f445558bb91
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65176839 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 42.sram_ctrl_access_during_key_req.65176839
Directory /workspace/42.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/42.sram_ctrl_alert_test.3666646189
Short name T227
Test name
Test status
Simulation time 14570893 ps
CPU time 0.63 seconds
Started Jan 10 01:28:20 PM PST 24
Finished Jan 10 01:29:06 PM PST 24
Peak memory 201852 kb
Host smart-f0c05799-5170-4f7a-8d0f-5d5c88daac44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666646189 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.sram_ctrl_alert_test.3666646189
Directory /workspace/42.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.sram_ctrl_executable.279335220
Short name T665
Test name
Test status
Simulation time 18517229562 ps
CPU time 1051.26 seconds
Started Jan 10 01:28:17 PM PST 24
Finished Jan 10 01:46:44 PM PST 24
Peak memory 374952 kb
Host smart-7387362f-40b6-4d93-abe1-a25529af061a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279335220 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_executabl
e.279335220
Directory /workspace/42.sram_ctrl_executable/latest

Test location /workspace/coverage/default/42.sram_ctrl_lc_escalation.619916096
Short name T4
Test name
Test status
Simulation time 39178940460 ps
CPU time 127.58 seconds
Started Jan 10 01:28:21 PM PST 24
Finished Jan 10 01:31:17 PM PST 24
Peak memory 210444 kb
Host smart-992810e3-a5e8-4950-b10c-f8ddbe759256
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619916096 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_esc
alation.619916096
Directory /workspace/42.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/42.sram_ctrl_max_throughput.558433406
Short name T951
Test name
Test status
Simulation time 906953207 ps
CPU time 166.24 seconds
Started Jan 10 01:28:13 PM PST 24
Finished Jan 10 01:31:56 PM PST 24
Peak memory 366752 kb
Host smart-66e2f9f7-be0e-4cc1-9087-efd37bd78a23
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558433406 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.sram_ctrl_max_throughput.558433406
Directory /workspace/42.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/42.sram_ctrl_mem_partial_access.397937169
Short name T904
Test name
Test status
Simulation time 1569230908 ps
CPU time 132.34 seconds
Started Jan 10 01:28:17 PM PST 24
Finished Jan 10 01:31:16 PM PST 24
Peak memory 211108 kb
Host smart-9dfa6b6c-5f4b-4543-8f7d-a27d53343b54
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397937169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.sram_ctrl_mem_partial_access.397937169
Directory /workspace/42.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/42.sram_ctrl_mem_walk.1789644738
Short name T593
Test name
Test status
Simulation time 4117283198 ps
CPU time 122.75 seconds
Started Jan 10 01:28:18 PM PST 24
Finished Jan 10 01:31:10 PM PST 24
Peak memory 202200 kb
Host smart-1afb12e0-8918-4eb4-ade7-f3a32907f029
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789644738 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctr
l_mem_walk.1789644738
Directory /workspace/42.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/42.sram_ctrl_multiple_keys.1511119798
Short name T13
Test name
Test status
Simulation time 22797011548 ps
CPU time 1532.81 seconds
Started Jan 10 01:28:01 PM PST 24
Finished Jan 10 01:54:39 PM PST 24
Peak memory 378112 kb
Host smart-08d6bb5e-48d8-4932-a02e-06f67a6da633
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511119798 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multi
ple_keys.1511119798
Directory /workspace/42.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/42.sram_ctrl_partial_access.3187339185
Short name T328
Test name
Test status
Simulation time 15638281493 ps
CPU time 141.3 seconds
Started Jan 10 01:28:12 PM PST 24
Finished Jan 10 01:31:27 PM PST 24
Peak memory 376012 kb
Host smart-f303d91c-9928-4b3d-a8c2-948fcaa0e236
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187339185 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
sram_ctrl_partial_access.3187339185
Directory /workspace/42.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.1873227776
Short name T932
Test name
Test status
Simulation time 16378747233 ps
CPU time 545.51 seconds
Started Jan 10 01:28:21 PM PST 24
Finished Jan 10 01:38:10 PM PST 24
Peak memory 202224 kb
Host smart-8f0d2c34-231b-457b-9186-4b7fd9e97bb8
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873227776 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 42.sram_ctrl_partial_access_b2b.1873227776
Directory /workspace/42.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/42.sram_ctrl_ram_cfg.888935740
Short name T485
Test name
Test status
Simulation time 1360510419 ps
CPU time 6.82 seconds
Started Jan 10 01:28:11 PM PST 24
Finished Jan 10 01:29:16 PM PST 24
Peak memory 202428 kb
Host smart-7a202691-a44c-4c92-8efd-9645d1394fcf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888935740 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.888935740
Directory /workspace/42.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/42.sram_ctrl_regwen.3103750916
Short name T310
Test name
Test status
Simulation time 4310234127 ps
CPU time 60.44 seconds
Started Jan 10 01:28:20 PM PST 24
Finished Jan 10 01:30:05 PM PST 24
Peak memory 331304 kb
Host smart-837afd4c-ecf9-4410-861a-cf8559d2a9c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103750916 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.3103750916
Directory /workspace/42.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/42.sram_ctrl_smoke.1876476084
Short name T835
Test name
Test status
Simulation time 1592128041 ps
CPU time 16.69 seconds
Started Jan 10 01:27:59 PM PST 24
Finished Jan 10 01:29:22 PM PST 24
Peak memory 202052 kb
Host smart-65b2a9aa-5e59-4b94-b084-c400c33e8760
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876476084 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.1876476084
Directory /workspace/42.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/42.sram_ctrl_stress_all.2548379005
Short name T820
Test name
Test status
Simulation time 778873462067 ps
CPU time 3054.87 seconds
Started Jan 10 01:28:18 PM PST 24
Finished Jan 10 02:20:03 PM PST 24
Peak memory 382200 kb
Host smart-306169bc-61f7-4684-9e31-05881523044e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548379005 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 42.sram_ctrl_stress_all.2548379005
Directory /workspace/42.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.4107903851
Short name T421
Test name
Test status
Simulation time 1117613122 ps
CPU time 2559.86 seconds
Started Jan 10 01:28:19 PM PST 24
Finished Jan 10 02:11:48 PM PST 24
Peak memory 490764 kb
Host smart-632a3684-e749-4485-948f-6a5d7d78595c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4107903851 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all_with_rand_reset.4107903851
Directory /workspace/42.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.sram_ctrl_stress_pipeline.1282180527
Short name T41
Test name
Test status
Simulation time 54201323751 ps
CPU time 252.4 seconds
Started Jan 10 01:28:12 PM PST 24
Finished Jan 10 01:33:20 PM PST 24
Peak memory 202104 kb
Host smart-8f6c3f4f-54fb-46c0-bfd1-663e2c03114e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282180527 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.sram_ctrl_stress_pipeline.1282180527
Directory /workspace/42.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.666184453
Short name T688
Test name
Test status
Simulation time 753085937 ps
CPU time 44.95 seconds
Started Jan 10 01:28:12 PM PST 24
Finished Jan 10 01:29:50 PM PST 24
Peak memory 273004 kb
Host smart-feb6dee1-2d0f-4221-b70e-c367858cea83
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666184453 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 42.sram_ctrl_throughput_w_partial_write.666184453
Directory /workspace/42.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/43.sram_ctrl_access_during_key_req.1460446533
Short name T724
Test name
Test status
Simulation time 28355889775 ps
CPU time 872.46 seconds
Started Jan 10 01:28:21 PM PST 24
Finished Jan 10 01:43:38 PM PST 24
Peak memory 346160 kb
Host smart-94ba9b97-809a-41c6-8086-fdab56cafec3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460446533 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.sram_ctrl_access_during_key_req.1460446533
Directory /workspace/43.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/43.sram_ctrl_alert_test.2357114023
Short name T807
Test name
Test status
Simulation time 13029675 ps
CPU time 0.62 seconds
Started Jan 10 01:28:13 PM PST 24
Finished Jan 10 01:29:05 PM PST 24
Peak memory 201848 kb
Host smart-28ef56b7-0207-481e-951f-2cf8c9e4b7d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357114023 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.sram_ctrl_alert_test.2357114023
Directory /workspace/43.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.sram_ctrl_bijection.2576538014
Short name T213
Test name
Test status
Simulation time 211936161922 ps
CPU time 1129.17 seconds
Started Jan 10 01:28:19 PM PST 24
Finished Jan 10 01:47:53 PM PST 24
Peak memory 202116 kb
Host smart-0329fa8a-9e4e-4b3f-a819-ba872a5b341f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576538014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection
.2576538014
Directory /workspace/43.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/43.sram_ctrl_executable.1363000232
Short name T823
Test name
Test status
Simulation time 2599449895 ps
CPU time 428.57 seconds
Started Jan 10 01:28:21 PM PST 24
Finished Jan 10 01:36:18 PM PST 24
Peak memory 369888 kb
Host smart-7163c1d3-0487-4828-9f31-128858ca91fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363000232 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_executab
le.1363000232
Directory /workspace/43.sram_ctrl_executable/latest

Test location /workspace/coverage/default/43.sram_ctrl_lc_escalation.1690110368
Short name T268
Test name
Test status
Simulation time 14106573650 ps
CPU time 186.72 seconds
Started Jan 10 01:28:16 PM PST 24
Finished Jan 10 01:32:13 PM PST 24
Peak memory 210744 kb
Host smart-ec326e74-872b-4655-8960-77ede1f40674
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690110368 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_es
calation.1690110368
Directory /workspace/43.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/43.sram_ctrl_max_throughput.2173464199
Short name T492
Test name
Test status
Simulation time 2778120961 ps
CPU time 27.51 seconds
Started Jan 10 01:28:18 PM PST 24
Finished Jan 10 01:29:38 PM PST 24
Peak memory 210428 kb
Host smart-6df1befd-e3a7-45ff-b75d-464d7d43a454
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173464199 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 43.sram_ctrl_max_throughput.2173464199
Directory /workspace/43.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/43.sram_ctrl_mem_partial_access.40326232
Short name T440
Test name
Test status
Simulation time 2646844669 ps
CPU time 76.3 seconds
Started Jan 10 01:28:34 PM PST 24
Finished Jan 10 01:30:29 PM PST 24
Peak memory 211136 kb
Host smart-fc061c3f-1ffa-4972-9913-31bac5d03111
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40326232 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
sram_ctrl_mem_partial_access.40326232
Directory /workspace/43.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/43.sram_ctrl_mem_walk.2908960895
Short name T783
Test name
Test status
Simulation time 13757222651 ps
CPU time 274.66 seconds
Started Jan 10 01:28:34 PM PST 24
Finished Jan 10 01:33:47 PM PST 24
Peak memory 202188 kb
Host smart-bac2f962-8b32-474d-811e-d3a5aca67d27
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908960895 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctr
l_mem_walk.2908960895
Directory /workspace/43.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/43.sram_ctrl_multiple_keys.3729458226
Short name T495
Test name
Test status
Simulation time 6465522261 ps
CPU time 496.15 seconds
Started Jan 10 01:28:19 PM PST 24
Finished Jan 10 01:37:20 PM PST 24
Peak memory 377056 kb
Host smart-2c842d4c-8f38-4b79-96d9-90e160be8aae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729458226 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multi
ple_keys.3729458226
Directory /workspace/43.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/43.sram_ctrl_partial_access.2074882346
Short name T874
Test name
Test status
Simulation time 1649226835 ps
CPU time 30.65 seconds
Started Jan 10 01:28:18 PM PST 24
Finished Jan 10 01:29:39 PM PST 24
Peak memory 202084 kb
Host smart-be6d1bb7-9572-415c-a842-b19d5edad52e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074882346 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
sram_ctrl_partial_access.2074882346
Directory /workspace/43.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.142545906
Short name T929
Test name
Test status
Simulation time 25916214362 ps
CPU time 401.34 seconds
Started Jan 10 01:28:56 PM PST 24
Finished Jan 10 01:36:03 PM PST 24
Peak memory 201848 kb
Host smart-0291e32f-03a2-4d83-bd86-a696a6fdf750
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142545906 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.sram_ctrl_partial_access_b2b.142545906
Directory /workspace/43.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/43.sram_ctrl_ram_cfg.780308844
Short name T451
Test name
Test status
Simulation time 700165897 ps
CPU time 12.95 seconds
Started Jan 10 01:28:42 PM PST 24
Finished Jan 10 01:29:29 PM PST 24
Peak memory 202404 kb
Host smart-7f8b413c-4697-4262-bed4-0fa5c852c6d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780308844 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.780308844
Directory /workspace/43.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/43.sram_ctrl_regwen.2794575893
Short name T301
Test name
Test status
Simulation time 44702805009 ps
CPU time 1086.66 seconds
Started Jan 10 01:28:34 PM PST 24
Finished Jan 10 01:47:19 PM PST 24
Peak memory 380172 kb
Host smart-8d3bd7f8-5b86-4455-a38b-bcc353aec038
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794575893 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.2794575893
Directory /workspace/43.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/43.sram_ctrl_smoke.3337926996
Short name T949
Test name
Test status
Simulation time 1121346374 ps
CPU time 23.3 seconds
Started Jan 10 01:28:17 PM PST 24
Finished Jan 10 01:29:27 PM PST 24
Peak memory 202080 kb
Host smart-da642cc7-0657-456d-ac9d-7e98ca99229c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337926996 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.3337926996
Directory /workspace/43.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.1259512677
Short name T434
Test name
Test status
Simulation time 3717467815 ps
CPU time 3550.4 seconds
Started Jan 10 01:28:15 PM PST 24
Finished Jan 10 02:28:21 PM PST 24
Peak memory 450156 kb
Host smart-2afb8c09-44d4-4dad-b09a-90acef0ec731
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1259512677 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all_with_rand_reset.1259512677
Directory /workspace/43.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.sram_ctrl_stress_pipeline.336703565
Short name T1
Test name
Test status
Simulation time 14057055653 ps
CPU time 252.7 seconds
Started Jan 10 01:28:18 PM PST 24
Finished Jan 10 01:33:23 PM PST 24
Peak memory 202156 kb
Host smart-ab4bf7a7-ce39-4154-a38d-8f33ed305eef
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336703565 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.sram_ctrl_stress_pipeline.336703565
Directory /workspace/43.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.2827797675
Short name T343
Test name
Test status
Simulation time 708382284 ps
CPU time 28.11 seconds
Started Jan 10 01:28:16 PM PST 24
Finished Jan 10 01:29:35 PM PST 24
Peak memory 214948 kb
Host smart-9f50dbf4-91a4-4c70-9863-c92882741686
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827797675 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.sram_ctrl_throughput_w_partial_write.2827797675
Directory /workspace/43.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/44.sram_ctrl_access_during_key_req.4196921057
Short name T743
Test name
Test status
Simulation time 2821349801 ps
CPU time 288.12 seconds
Started Jan 10 01:28:17 PM PST 24
Finished Jan 10 01:33:52 PM PST 24
Peak memory 322788 kb
Host smart-06d54ff3-c8c9-427e-8dea-c68a825aa390
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196921057 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 44.sram_ctrl_access_during_key_req.4196921057
Directory /workspace/44.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/44.sram_ctrl_alert_test.223414636
Short name T410
Test name
Test status
Simulation time 13827808 ps
CPU time 0.65 seconds
Started Jan 10 01:28:52 PM PST 24
Finished Jan 10 01:29:19 PM PST 24
Peak memory 201440 kb
Host smart-1ae245b0-f27a-488b-a96e-3a88aa68749d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223414636 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.sram_ctrl_alert_test.223414636
Directory /workspace/44.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.sram_ctrl_bijection.1867114770
Short name T544
Test name
Test status
Simulation time 48120351362 ps
CPU time 1068.83 seconds
Started Jan 10 01:28:20 PM PST 24
Finished Jan 10 01:46:54 PM PST 24
Peak memory 202164 kb
Host smart-d7f33a47-ca59-4994-b07e-317d5dc5e476
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867114770 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection
.1867114770
Directory /workspace/44.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/44.sram_ctrl_lc_escalation.3354179909
Short name T367
Test name
Test status
Simulation time 51162908718 ps
CPU time 129.55 seconds
Started Jan 10 01:28:19 PM PST 24
Finished Jan 10 01:31:17 PM PST 24
Peak memory 210404 kb
Host smart-0b7fbf35-d68a-432e-b72c-88c4f5c7b870
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354179909 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_es
calation.3354179909
Directory /workspace/44.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/44.sram_ctrl_max_throughput.4085043688
Short name T352
Test name
Test status
Simulation time 1009896587 ps
CPU time 41.86 seconds
Started Jan 10 01:28:18 PM PST 24
Finished Jan 10 01:29:52 PM PST 24
Peak memory 269692 kb
Host smart-ab5d0737-a476-4616-95d7-28b16f60eb57
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085043688 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 44.sram_ctrl_max_throughput.4085043688
Directory /workspace/44.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/44.sram_ctrl_mem_partial_access.4109514757
Short name T927
Test name
Test status
Simulation time 9526632061 ps
CPU time 155.67 seconds
Started Jan 10 01:28:17 PM PST 24
Finished Jan 10 01:31:48 PM PST 24
Peak memory 214672 kb
Host smart-59724649-efd2-4072-a603-0d884536afad
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109514757 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.sram_ctrl_mem_partial_access.4109514757
Directory /workspace/44.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/44.sram_ctrl_mem_walk.3948499146
Short name T480
Test name
Test status
Simulation time 7176698865 ps
CPU time 136.3 seconds
Started Jan 10 01:28:14 PM PST 24
Finished Jan 10 01:31:26 PM PST 24
Peak memory 202252 kb
Host smart-f5bb7319-3057-4500-8b69-cd1ab634f64c
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948499146 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctr
l_mem_walk.3948499146
Directory /workspace/44.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/44.sram_ctrl_multiple_keys.2256402620
Short name T642
Test name
Test status
Simulation time 8708625767 ps
CPU time 1691.14 seconds
Started Jan 10 01:28:12 PM PST 24
Finished Jan 10 01:57:16 PM PST 24
Peak memory 378124 kb
Host smart-ba71de28-e8de-47a3-ab50-55e08fb8e735
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256402620 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multi
ple_keys.2256402620
Directory /workspace/44.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/44.sram_ctrl_partial_access.1081748093
Short name T236
Test name
Test status
Simulation time 5361933269 ps
CPU time 25.21 seconds
Started Jan 10 01:28:46 PM PST 24
Finished Jan 10 01:29:41 PM PST 24
Peak memory 202160 kb
Host smart-ee6dc2f6-8033-4d84-a7f4-6162b4eaf05c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081748093 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
sram_ctrl_partial_access.1081748093
Directory /workspace/44.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.2407086181
Short name T351
Test name
Test status
Simulation time 23512420322 ps
CPU time 531.04 seconds
Started Jan 10 01:28:19 PM PST 24
Finished Jan 10 01:37:59 PM PST 24
Peak memory 210388 kb
Host smart-2743233c-d6b6-4433-a12d-6b5df34939ab
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407086181 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 44.sram_ctrl_partial_access_b2b.2407086181
Directory /workspace/44.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/44.sram_ctrl_ram_cfg.1933294374
Short name T785
Test name
Test status
Simulation time 1289647823 ps
CPU time 14.49 seconds
Started Jan 10 01:28:19 PM PST 24
Finished Jan 10 01:29:19 PM PST 24
Peak memory 202408 kb
Host smart-151a8d86-ba6b-4116-bebc-ee8d2f4726a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933294374 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.1933294374
Directory /workspace/44.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/44.sram_ctrl_regwen.192590665
Short name T112
Test name
Test status
Simulation time 14613473460 ps
CPU time 798 seconds
Started Jan 10 01:28:19 PM PST 24
Finished Jan 10 01:42:21 PM PST 24
Peak memory 371936 kb
Host smart-de31ccb8-aac9-4e06-af06-46b89569bef5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192590665 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.192590665
Directory /workspace/44.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/44.sram_ctrl_smoke.670312515
Short name T753
Test name
Test status
Simulation time 1443116016 ps
CPU time 12.52 seconds
Started Jan 10 01:28:18 PM PST 24
Finished Jan 10 01:29:20 PM PST 24
Peak memory 202092 kb
Host smart-edc50121-5641-4925-9bf6-53db38e93016
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670312515 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.670312515
Directory /workspace/44.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.1609755944
Short name T763
Test name
Test status
Simulation time 2647829089 ps
CPU time 3899.48 seconds
Started Jan 10 01:28:14 PM PST 24
Finished Jan 10 02:34:06 PM PST 24
Peak memory 579956 kb
Host smart-a7bc237f-a53f-424a-9382-fca12d8cc937
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1609755944 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_all_with_rand_reset.1609755944
Directory /workspace/44.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.sram_ctrl_stress_pipeline.1280715771
Short name T294
Test name
Test status
Simulation time 2616882608 ps
CPU time 200.65 seconds
Started Jan 10 01:28:16 PM PST 24
Finished Jan 10 01:32:26 PM PST 24
Peak memory 202172 kb
Host smart-ca7a4447-7fc4-442b-a573-ce22fb5c9825
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280715771 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.sram_ctrl_stress_pipeline.1280715771
Directory /workspace/44.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.877984908
Short name T428
Test name
Test status
Simulation time 819352980 ps
CPU time 142.92 seconds
Started Jan 10 01:28:17 PM PST 24
Finished Jan 10 01:31:27 PM PST 24
Peak memory 369824 kb
Host smart-bae7a264-a014-4c25-9c60-fa3cea729769
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877984908 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 44.sram_ctrl_throughput_w_partial_write.877984908
Directory /workspace/44.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/45.sram_ctrl_access_during_key_req.1933237316
Short name T565
Test name
Test status
Simulation time 1026120054 ps
CPU time 306.52 seconds
Started Jan 10 01:28:55 PM PST 24
Finished Jan 10 01:34:28 PM PST 24
Peak memory 364760 kb
Host smart-bb2b9bbb-287b-4d7c-a91c-d7605bc49caf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933237316 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.sram_ctrl_access_during_key_req.1933237316
Directory /workspace/45.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/45.sram_ctrl_alert_test.3036593321
Short name T518
Test name
Test status
Simulation time 14447041 ps
CPU time 0.7 seconds
Started Jan 10 01:28:21 PM PST 24
Finished Jan 10 01:29:05 PM PST 24
Peak memory 201856 kb
Host smart-e249c33a-baca-4766-9dc6-6139df18aa93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036593321 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.sram_ctrl_alert_test.3036593321
Directory /workspace/45.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.sram_ctrl_bijection.2357168239
Short name T839
Test name
Test status
Simulation time 21745294971 ps
CPU time 711 seconds
Started Jan 10 01:28:18 PM PST 24
Finished Jan 10 01:40:57 PM PST 24
Peak memory 202160 kb
Host smart-1bafb7ba-e265-4df7-a23c-94498a508fea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357168239 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection
.2357168239
Directory /workspace/45.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/45.sram_ctrl_max_throughput.1251781402
Short name T671
Test name
Test status
Simulation time 790054712 ps
CPU time 139.99 seconds
Started Jan 10 01:28:16 PM PST 24
Finished Jan 10 01:31:25 PM PST 24
Peak memory 366108 kb
Host smart-1f91c36d-2944-47e3-85ea-eac28f3692f1
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251781402 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 45.sram_ctrl_max_throughput.1251781402
Directory /workspace/45.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/45.sram_ctrl_mem_partial_access.2889284011
Short name T458
Test name
Test status
Simulation time 9361070012 ps
CPU time 74.39 seconds
Started Jan 10 01:28:16 PM PST 24
Finished Jan 10 01:30:20 PM PST 24
Peak memory 218492 kb
Host smart-9942c483-6264-4ec1-adc6-4c76aca30d87
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889284011 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.sram_ctrl_mem_partial_access.2889284011
Directory /workspace/45.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/45.sram_ctrl_mem_walk.351344675
Short name T240
Test name
Test status
Simulation time 57403489119 ps
CPU time 150.95 seconds
Started Jan 10 01:28:38 PM PST 24
Finished Jan 10 01:31:45 PM PST 24
Peak memory 202228 kb
Host smart-c642eaf1-c3bc-4aa0-afcf-887f662dda0c
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351344675 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl
_mem_walk.351344675
Directory /workspace/45.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/45.sram_ctrl_multiple_keys.2968845569
Short name T580
Test name
Test status
Simulation time 24513868246 ps
CPU time 1292.43 seconds
Started Jan 10 01:28:52 PM PST 24
Finished Jan 10 01:50:51 PM PST 24
Peak memory 379940 kb
Host smart-17327fa8-0f7a-4572-a585-03aef7b17187
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968845569 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multi
ple_keys.2968845569
Directory /workspace/45.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/45.sram_ctrl_partial_access.3796382768
Short name T897
Test name
Test status
Simulation time 1269711651 ps
CPU time 73.89 seconds
Started Jan 10 01:28:37 PM PST 24
Finished Jan 10 01:30:28 PM PST 24
Peak memory 320892 kb
Host smart-bf126dba-fa4d-4c55-bc2a-fefaa4209a33
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796382768 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
sram_ctrl_partial_access.3796382768
Directory /workspace/45.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.3380943480
Short name T579
Test name
Test status
Simulation time 6703479000 ps
CPU time 422.72 seconds
Started Jan 10 01:28:13 PM PST 24
Finished Jan 10 01:36:06 PM PST 24
Peak memory 202092 kb
Host smart-e904f331-eafe-474e-b2c3-7434d3b06a8f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380943480 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 45.sram_ctrl_partial_access_b2b.3380943480
Directory /workspace/45.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/45.sram_ctrl_ram_cfg.4066542957
Short name T712
Test name
Test status
Simulation time 1348450365 ps
CPU time 5.77 seconds
Started Jan 10 01:28:20 PM PST 24
Finished Jan 10 01:29:11 PM PST 24
Peak memory 202416 kb
Host smart-c1545972-68e6-4a97-bee4-9e265776796a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066542957 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.4066542957
Directory /workspace/45.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/45.sram_ctrl_regwen.2519740616
Short name T678
Test name
Test status
Simulation time 6982511367 ps
CPU time 349.56 seconds
Started Jan 10 01:28:21 PM PST 24
Finished Jan 10 01:34:57 PM PST 24
Peak memory 358128 kb
Host smart-d5eceed3-aa48-4b73-9bf8-b6b9f8d74faa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519740616 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.2519740616
Directory /workspace/45.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/45.sram_ctrl_smoke.1479747973
Short name T942
Test name
Test status
Simulation time 710066301 ps
CPU time 15.39 seconds
Started Jan 10 01:28:14 PM PST 24
Finished Jan 10 01:29:21 PM PST 24
Peak memory 202084 kb
Host smart-0eacdd12-1513-46c7-bd92-862c803cb9f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479747973 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.1479747973
Directory /workspace/45.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/45.sram_ctrl_stress_all.1205329105
Short name T497
Test name
Test status
Simulation time 198371002135 ps
CPU time 3620.48 seconds
Started Jan 10 01:29:01 PM PST 24
Finished Jan 10 02:29:44 PM PST 24
Peak memory 380136 kb
Host smart-a9c53fa3-c6f8-4303-845c-4dc56a63e0f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205329105 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 45.sram_ctrl_stress_all.1205329105
Directory /workspace/45.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.3659465522
Short name T96
Test name
Test status
Simulation time 2149573954 ps
CPU time 4140.45 seconds
Started Jan 10 01:29:01 PM PST 24
Finished Jan 10 02:38:24 PM PST 24
Peak memory 631024 kb
Host smart-b55b344a-5fff-452f-90a1-a68dd72e3984
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3659465522 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all_with_rand_reset.3659465522
Directory /workspace/45.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.sram_ctrl_stress_pipeline.3297612932
Short name T478
Test name
Test status
Simulation time 5027450811 ps
CPU time 372.04 seconds
Started Jan 10 01:28:12 PM PST 24
Finished Jan 10 01:35:17 PM PST 24
Peak memory 202216 kb
Host smart-0bb96a63-d5b2-4d40-b455-a00ccdc58fcf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297612932 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.sram_ctrl_stress_pipeline.3297612932
Directory /workspace/45.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.648813015
Short name T550
Test name
Test status
Simulation time 1397677677 ps
CPU time 29.46 seconds
Started Jan 10 01:28:18 PM PST 24
Finished Jan 10 01:29:38 PM PST 24
Peak memory 224192 kb
Host smart-510e8216-40c8-464e-bdb3-00d142dc10f0
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648813015 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 45.sram_ctrl_throughput_w_partial_write.648813015
Directory /workspace/45.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/46.sram_ctrl_access_during_key_req.1066712795
Short name T736
Test name
Test status
Simulation time 35370922005 ps
CPU time 1358.28 seconds
Started Jan 10 01:28:51 PM PST 24
Finished Jan 10 01:51:57 PM PST 24
Peak memory 380104 kb
Host smart-790c3e90-4f35-4444-93c6-5329da517016
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066712795 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 46.sram_ctrl_access_during_key_req.1066712795
Directory /workspace/46.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/46.sram_ctrl_alert_test.1636460566
Short name T557
Test name
Test status
Simulation time 42211274 ps
CPU time 0.62 seconds
Started Jan 10 01:28:22 PM PST 24
Finished Jan 10 01:29:08 PM PST 24
Peak memory 201456 kb
Host smart-44e0664d-7a0a-4de2-b807-93e1fbd86be0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636460566 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.sram_ctrl_alert_test.1636460566
Directory /workspace/46.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.sram_ctrl_bijection.2194833615
Short name T625
Test name
Test status
Simulation time 26028459220 ps
CPU time 1777.84 seconds
Started Jan 10 01:28:34 PM PST 24
Finished Jan 10 01:58:51 PM PST 24
Peak memory 202112 kb
Host smart-b3e1c3a4-ce43-4d3f-bcbe-09bc6d4ec75d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194833615 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection
.2194833615
Directory /workspace/46.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/46.sram_ctrl_executable.3029450977
Short name T744
Test name
Test status
Simulation time 67768406151 ps
CPU time 885.04 seconds
Started Jan 10 01:28:52 PM PST 24
Finished Jan 10 01:44:04 PM PST 24
Peak memory 371916 kb
Host smart-242c2fbe-90ed-4e84-a19c-0b427c303e80
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029450977 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_executab
le.3029450977
Directory /workspace/46.sram_ctrl_executable/latest

Test location /workspace/coverage/default/46.sram_ctrl_lc_escalation.2981538695
Short name T864
Test name
Test status
Simulation time 2290453226 ps
CPU time 27.25 seconds
Started Jan 10 01:28:42 PM PST 24
Finished Jan 10 01:29:43 PM PST 24
Peak memory 210268 kb
Host smart-31545040-eea9-4493-83e3-f2484f1dfd15
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981538695 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_es
calation.2981538695
Directory /workspace/46.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/46.sram_ctrl_max_throughput.3428941748
Short name T907
Test name
Test status
Simulation time 801672252 ps
CPU time 123.62 seconds
Started Jan 10 01:28:43 PM PST 24
Finished Jan 10 01:31:20 PM PST 24
Peak memory 351376 kb
Host smart-b3ef1608-9ab3-4e23-ae8d-a0b2b9cde4f6
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428941748 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 46.sram_ctrl_max_throughput.3428941748
Directory /workspace/46.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/46.sram_ctrl_mem_partial_access.1128628750
Short name T662
Test name
Test status
Simulation time 31217950192 ps
CPU time 160.76 seconds
Started Jan 10 01:28:53 PM PST 24
Finished Jan 10 01:32:00 PM PST 24
Peak memory 211236 kb
Host smart-1e1a544f-0dfd-47ab-b199-9dfaf12a2067
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128628750 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.sram_ctrl_mem_partial_access.1128628750
Directory /workspace/46.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/46.sram_ctrl_mem_walk.2700813670
Short name T862
Test name
Test status
Simulation time 35833082613 ps
CPU time 162.06 seconds
Started Jan 10 01:28:22 PM PST 24
Finished Jan 10 01:31:50 PM PST 24
Peak memory 202272 kb
Host smart-c7987e14-aa22-4db3-80b7-4ed84c32e51f
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700813670 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctr
l_mem_walk.2700813670
Directory /workspace/46.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/46.sram_ctrl_multiple_keys.2890826222
Short name T403
Test name
Test status
Simulation time 19938173934 ps
CPU time 397.12 seconds
Started Jan 10 01:28:21 PM PST 24
Finished Jan 10 01:35:41 PM PST 24
Peak memory 373848 kb
Host smart-d1439952-8877-4edc-96cd-cdb6dbb00250
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890826222 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multi
ple_keys.2890826222
Directory /workspace/46.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/46.sram_ctrl_partial_access.3822997840
Short name T2
Test name
Test status
Simulation time 3897823582 ps
CPU time 31.84 seconds
Started Jan 10 01:28:52 PM PST 24
Finished Jan 10 01:29:51 PM PST 24
Peak memory 280500 kb
Host smart-791edfab-c0cd-447b-8ece-64329ff58e88
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822997840 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
sram_ctrl_partial_access.3822997840
Directory /workspace/46.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.1315834746
Short name T444
Test name
Test status
Simulation time 19144611435 ps
CPU time 475.47 seconds
Started Jan 10 01:28:52 PM PST 24
Finished Jan 10 01:37:14 PM PST 24
Peak memory 202156 kb
Host smart-5f446566-7e37-4ffd-a08b-da1b95ef1079
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315834746 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 46.sram_ctrl_partial_access_b2b.1315834746
Directory /workspace/46.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/46.sram_ctrl_ram_cfg.3352617199
Short name T251
Test name
Test status
Simulation time 1406617646 ps
CPU time 6.58 seconds
Started Jan 10 01:28:20 PM PST 24
Finished Jan 10 01:29:12 PM PST 24
Peak memory 202412 kb
Host smart-caf994cf-a441-4881-b21e-895355c875be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352617199 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.3352617199
Directory /workspace/46.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/46.sram_ctrl_regwen.1770163993
Short name T514
Test name
Test status
Simulation time 181142564315 ps
CPU time 1637.28 seconds
Started Jan 10 01:28:21 PM PST 24
Finished Jan 10 01:56:27 PM PST 24
Peak memory 381096 kb
Host smart-48a1cc08-684a-49b4-870e-30fb2d2c183c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770163993 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.1770163993
Directory /workspace/46.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/46.sram_ctrl_smoke.3219056332
Short name T872
Test name
Test status
Simulation time 4052056933 ps
CPU time 28.23 seconds
Started Jan 10 01:28:20 PM PST 24
Finished Jan 10 01:29:32 PM PST 24
Peak memory 202148 kb
Host smart-2e340726-e189-4b96-8b94-388f9465d20c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219056332 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.3219056332
Directory /workspace/46.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3172723502
Short name T906
Test name
Test status
Simulation time 228917922 ps
CPU time 2732.58 seconds
Started Jan 10 01:28:53 PM PST 24
Finished Jan 10 02:14:52 PM PST 24
Peak memory 390236 kb
Host smart-c5a46d3d-1887-4f80-a161-421d384f0f5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3172723502 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all_with_rand_reset.3172723502
Directory /workspace/46.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.sram_ctrl_stress_pipeline.421086552
Short name T309
Test name
Test status
Simulation time 20080332587 ps
CPU time 378.69 seconds
Started Jan 10 01:28:52 PM PST 24
Finished Jan 10 01:35:37 PM PST 24
Peak memory 202176 kb
Host smart-e750bab6-cc98-4e5e-8278-08c29967522a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421086552 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.sram_ctrl_stress_pipeline.421086552
Directory /workspace/46.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.2588309235
Short name T613
Test name
Test status
Simulation time 5660994824 ps
CPU time 62.41 seconds
Started Jan 10 01:28:43 PM PST 24
Finished Jan 10 01:30:18 PM PST 24
Peak memory 300284 kb
Host smart-a6ccf34a-b5e6-4b7e-9b08-80b77dfa8bf8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588309235 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.sram_ctrl_throughput_w_partial_write.2588309235
Directory /workspace/46.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/47.sram_ctrl_access_during_key_req.1770501024
Short name T460
Test name
Test status
Simulation time 38635538945 ps
CPU time 1328.42 seconds
Started Jan 10 01:30:42 PM PST 24
Finished Jan 10 01:52:52 PM PST 24
Peak memory 377064 kb
Host smart-ea72c79b-61d5-4ab1-b097-f106b6eb28a5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770501024 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 47.sram_ctrl_access_during_key_req.1770501024
Directory /workspace/47.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/47.sram_ctrl_alert_test.3645947948
Short name T727
Test name
Test status
Simulation time 39472733 ps
CPU time 0.63 seconds
Started Jan 10 01:30:46 PM PST 24
Finished Jan 10 01:30:47 PM PST 24
Peak memory 201816 kb
Host smart-18a9a55d-8369-4d01-94af-7004369811a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645947948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.sram_ctrl_alert_test.3645947948
Directory /workspace/47.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.sram_ctrl_bijection.3934273913
Short name T534
Test name
Test status
Simulation time 124285762038 ps
CPU time 2211.72 seconds
Started Jan 10 01:28:19 PM PST 24
Finished Jan 10 02:05:56 PM PST 24
Peak memory 202172 kb
Host smart-cad434d1-a8ae-41bc-886a-454465a01a95
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934273913 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection
.3934273913
Directory /workspace/47.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/47.sram_ctrl_lc_escalation.1582656911
Short name T416
Test name
Test status
Simulation time 47596301358 ps
CPU time 143.32 seconds
Started Jan 10 01:30:45 PM PST 24
Finished Jan 10 01:33:09 PM PST 24
Peak memory 210344 kb
Host smart-80386cde-2349-4740-88f3-e59d056298dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582656911 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_es
calation.1582656911
Directory /workspace/47.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/47.sram_ctrl_max_throughput.1722351477
Short name T423
Test name
Test status
Simulation time 10331117018 ps
CPU time 61.47 seconds
Started Jan 10 01:30:43 PM PST 24
Finished Jan 10 01:31:46 PM PST 24
Peak memory 301524 kb
Host smart-893c1dde-fbd2-4b18-996f-84ef432d09bf
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722351477 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 47.sram_ctrl_max_throughput.1722351477
Directory /workspace/47.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/47.sram_ctrl_mem_partial_access.3890530624
Short name T955
Test name
Test status
Simulation time 4609997553 ps
CPU time 161.17 seconds
Started Jan 10 01:30:43 PM PST 24
Finished Jan 10 01:33:26 PM PST 24
Peak memory 211048 kb
Host smart-f88430db-fb49-46b0-9169-f64ddccc48d7
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890530624 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.sram_ctrl_mem_partial_access.3890530624
Directory /workspace/47.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/47.sram_ctrl_mem_walk.915028102
Short name T816
Test name
Test status
Simulation time 35847089788 ps
CPU time 153.74 seconds
Started Jan 10 01:30:43 PM PST 24
Finished Jan 10 01:33:19 PM PST 24
Peak memory 202208 kb
Host smart-6893d310-c22a-4dd7-8b7b-dfda95d9d58a
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915028102 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl
_mem_walk.915028102
Directory /workspace/47.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/47.sram_ctrl_multiple_keys.878153429
Short name T889
Test name
Test status
Simulation time 78866169907 ps
CPU time 251.03 seconds
Started Jan 10 01:28:46 PM PST 24
Finished Jan 10 01:33:27 PM PST 24
Peak memory 353544 kb
Host smart-ee573cd3-a87d-4aff-88ac-64b993503fea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878153429 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multip
le_keys.878153429
Directory /workspace/47.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/47.sram_ctrl_partial_access.87470455
Short name T658
Test name
Test status
Simulation time 3049789455 ps
CPU time 15.81 seconds
Started Jan 10 01:30:41 PM PST 24
Finished Jan 10 01:30:57 PM PST 24
Peak memory 221056 kb
Host smart-edd0da69-a42e-403e-8a04-8391908b0459
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87470455 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sr
am_ctrl_partial_access.87470455
Directory /workspace/47.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.2624607583
Short name T615
Test name
Test status
Simulation time 28508706814 ps
CPU time 494.32 seconds
Started Jan 10 01:30:45 PM PST 24
Finished Jan 10 01:39:00 PM PST 24
Peak memory 202168 kb
Host smart-d37d19c8-1cb9-4aab-8974-76ac851d6cf1
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624607583 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 47.sram_ctrl_partial_access_b2b.2624607583
Directory /workspace/47.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/47.sram_ctrl_ram_cfg.2133254368
Short name T386
Test name
Test status
Simulation time 1255332854 ps
CPU time 6.41 seconds
Started Jan 10 01:30:43 PM PST 24
Finished Jan 10 01:30:51 PM PST 24
Peak memory 202432 kb
Host smart-83c410f3-9462-42a7-adc4-a3e2069ed69d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133254368 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.2133254368
Directory /workspace/47.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/47.sram_ctrl_regwen.404571054
Short name T970
Test name
Test status
Simulation time 16906401534 ps
CPU time 798.48 seconds
Started Jan 10 01:30:42 PM PST 24
Finished Jan 10 01:44:01 PM PST 24
Peak memory 378064 kb
Host smart-91d8d3e9-59d8-48d5-9b51-ba778a19f00c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404571054 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.404571054
Directory /workspace/47.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/47.sram_ctrl_smoke.3212811195
Short name T217
Test name
Test status
Simulation time 697012908 ps
CPU time 11.01 seconds
Started Jan 10 01:28:19 PM PST 24
Finished Jan 10 01:29:15 PM PST 24
Peak memory 202088 kb
Host smart-aeb68297-826c-458d-a408-2e97af2e0629
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212811195 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.3212811195
Directory /workspace/47.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/47.sram_ctrl_stress_all.4094124573
Short name T883
Test name
Test status
Simulation time 388845942076 ps
CPU time 5806.85 seconds
Started Jan 10 01:30:41 PM PST 24
Finished Jan 10 03:07:29 PM PST 24
Peak memory 381112 kb
Host smart-eb682252-f919-4532-84f6-e3b209c0bee5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094124573 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 47.sram_ctrl_stress_all.4094124573
Directory /workspace/47.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.2129403675
Short name T641
Test name
Test status
Simulation time 2599193277 ps
CPU time 4606.68 seconds
Started Jan 10 01:30:42 PM PST 24
Finished Jan 10 02:47:31 PM PST 24
Peak memory 594576 kb
Host smart-bedd1c98-0f56-4515-901a-6735f88d4de4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2129403675 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all_with_rand_reset.2129403675
Directory /workspace/47.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.sram_ctrl_stress_pipeline.2004186627
Short name T779
Test name
Test status
Simulation time 14864051465 ps
CPU time 287.98 seconds
Started Jan 10 01:30:43 PM PST 24
Finished Jan 10 01:35:33 PM PST 24
Peak memory 202208 kb
Host smart-6b2b1123-4553-4351-a3fd-b8d40d256809
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004186627 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.sram_ctrl_stress_pipeline.2004186627
Directory /workspace/47.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.1596065353
Short name T880
Test name
Test status
Simulation time 3218563835 ps
CPU time 143.16 seconds
Started Jan 10 01:30:45 PM PST 24
Finished Jan 10 01:33:09 PM PST 24
Peak memory 357524 kb
Host smart-9f9d9253-9107-4c86-8799-57761ee6265e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596065353 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 47.sram_ctrl_throughput_w_partial_write.1596065353
Directory /workspace/47.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/48.sram_ctrl_access_during_key_req.2204280685
Short name T588
Test name
Test status
Simulation time 8179387478 ps
CPU time 797.89 seconds
Started Jan 10 01:30:46 PM PST 24
Finished Jan 10 01:44:04 PM PST 24
Peak memory 364788 kb
Host smart-1af06f24-015a-4a88-b9fb-baa0c81f1d3b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204280685 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 48.sram_ctrl_access_during_key_req.2204280685
Directory /workspace/48.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/48.sram_ctrl_alert_test.2888400549
Short name T948
Test name
Test status
Simulation time 24281265 ps
CPU time 0.64 seconds
Started Jan 10 01:31:00 PM PST 24
Finished Jan 10 01:31:02 PM PST 24
Peak memory 201456 kb
Host smart-d85add31-4f02-4057-be8d-f8fa243823ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888400549 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.sram_ctrl_alert_test.2888400549
Directory /workspace/48.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.sram_ctrl_bijection.383520085
Short name T55
Test name
Test status
Simulation time 30496991685 ps
CPU time 2314.68 seconds
Started Jan 10 01:30:44 PM PST 24
Finished Jan 10 02:09:20 PM PST 24
Peak memory 202256 kb
Host smart-f4b986a3-147e-499c-bf59-bb944a38526e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383520085 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection.
383520085
Directory /workspace/48.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/48.sram_ctrl_executable.2304971775
Short name T766
Test name
Test status
Simulation time 4689245333 ps
CPU time 528.11 seconds
Started Jan 10 01:30:44 PM PST 24
Finished Jan 10 01:39:33 PM PST 24
Peak memory 355560 kb
Host smart-fbc78e7f-a55d-4793-bb05-0c3e2337a8bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304971775 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_executab
le.2304971775
Directory /workspace/48.sram_ctrl_executable/latest

Test location /workspace/coverage/default/48.sram_ctrl_lc_escalation.1229629004
Short name T315
Test name
Test status
Simulation time 28590501871 ps
CPU time 77.23 seconds
Started Jan 10 01:30:47 PM PST 24
Finished Jan 10 01:32:05 PM PST 24
Peak memory 210400 kb
Host smart-f86e15e8-7a4d-4968-9d9b-a5f481231eb2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229629004 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_es
calation.1229629004
Directory /workspace/48.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/48.sram_ctrl_max_throughput.2961463217
Short name T72
Test name
Test status
Simulation time 734165410 ps
CPU time 58.68 seconds
Started Jan 10 01:30:42 PM PST 24
Finished Jan 10 01:31:43 PM PST 24
Peak memory 295656 kb
Host smart-e95231cb-9d58-4de7-adf9-61363351a56f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961463217 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 48.sram_ctrl_max_throughput.2961463217
Directory /workspace/48.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/48.sram_ctrl_mem_partial_access.4284403857
Short name T911
Test name
Test status
Simulation time 16846313798 ps
CPU time 155.18 seconds
Started Jan 10 01:30:45 PM PST 24
Finished Jan 10 01:33:21 PM PST 24
Peak memory 211148 kb
Host smart-89dba419-8d91-4282-ac23-60534af0aabe
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284403857 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.sram_ctrl_mem_partial_access.4284403857
Directory /workspace/48.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/48.sram_ctrl_mem_walk.2789904799
Short name T543
Test name
Test status
Simulation time 2059582295 ps
CPU time 121.63 seconds
Started Jan 10 01:30:47 PM PST 24
Finished Jan 10 01:32:49 PM PST 24
Peak memory 202068 kb
Host smart-6bf61db8-a537-4578-96ab-f27f93e55573
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789904799 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctr
l_mem_walk.2789904799
Directory /workspace/48.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/48.sram_ctrl_multiple_keys.1077972270
Short name T11
Test name
Test status
Simulation time 92873955696 ps
CPU time 1652.01 seconds
Started Jan 10 01:30:46 PM PST 24
Finished Jan 10 01:58:19 PM PST 24
Peak memory 379288 kb
Host smart-df9731d1-051c-4227-adba-88e18abab1be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077972270 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multi
ple_keys.1077972270
Directory /workspace/48.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/48.sram_ctrl_partial_access.1184078715
Short name T767
Test name
Test status
Simulation time 2788703730 ps
CPU time 23.61 seconds
Started Jan 10 01:30:42 PM PST 24
Finished Jan 10 01:31:08 PM PST 24
Peak memory 202156 kb
Host smart-771fab5e-69d4-45c1-9833-ee284c5d169e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184078715 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
sram_ctrl_partial_access.1184078715
Directory /workspace/48.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.955519033
Short name T224
Test name
Test status
Simulation time 12781214062 ps
CPU time 282.85 seconds
Started Jan 10 01:30:44 PM PST 24
Finished Jan 10 01:35:28 PM PST 24
Peak memory 202136 kb
Host smart-3d23e82d-35c1-4402-b052-feca22f882df
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955519033 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.sram_ctrl_partial_access_b2b.955519033
Directory /workspace/48.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/48.sram_ctrl_ram_cfg.2355917381
Short name T33
Test name
Test status
Simulation time 1546368950 ps
CPU time 6.61 seconds
Started Jan 10 01:30:43 PM PST 24
Finished Jan 10 01:30:51 PM PST 24
Peak memory 202444 kb
Host smart-e9e8b10e-6322-43d3-ab68-ce84ccfd246f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355917381 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.2355917381
Directory /workspace/48.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/48.sram_ctrl_regwen.2863581583
Short name T312
Test name
Test status
Simulation time 8817789954 ps
CPU time 1094.01 seconds
Started Jan 10 01:30:43 PM PST 24
Finished Jan 10 01:48:59 PM PST 24
Peak memory 379048 kb
Host smart-ca5e9110-e484-41b5-b336-5cc8a6271b1a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863581583 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.2863581583
Directory /workspace/48.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/48.sram_ctrl_smoke.2898205234
Short name T490
Test name
Test status
Simulation time 851745175 ps
CPU time 21.38 seconds
Started Jan 10 01:30:42 PM PST 24
Finished Jan 10 01:31:04 PM PST 24
Peak memory 202032 kb
Host smart-3a4ead4d-0168-43db-ac0f-400195576fb3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898205234 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.2898205234
Directory /workspace/48.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/48.sram_ctrl_stress_all.1953927979
Short name T969
Test name
Test status
Simulation time 192737709186 ps
CPU time 5361.28 seconds
Started Jan 10 01:31:01 PM PST 24
Finished Jan 10 03:00:27 PM PST 24
Peak memory 381172 kb
Host smart-0e8d1012-cea2-4225-8696-19a45bbd328f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953927979 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 48.sram_ctrl_stress_all.1953927979
Directory /workspace/48.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.321599353
Short name T869
Test name
Test status
Simulation time 518550953 ps
CPU time 1228.06 seconds
Started Jan 10 01:31:04 PM PST 24
Finished Jan 10 01:51:36 PM PST 24
Peak memory 389220 kb
Host smart-1f605e66-d5d0-4633-a453-c081b22496e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=321599353 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all_with_rand_reset.321599353
Directory /workspace/48.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.sram_ctrl_stress_pipeline.41027166
Short name T390
Test name
Test status
Simulation time 45624799264 ps
CPU time 401.9 seconds
Started Jan 10 01:30:45 PM PST 24
Finished Jan 10 01:37:28 PM PST 24
Peak memory 202160 kb
Host smart-895b79c6-0374-4e3d-9d8c-c9188a41614d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41027166 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
sram_ctrl_stress_pipeline.41027166
Directory /workspace/48.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.1745079014
Short name T674
Test name
Test status
Simulation time 3484429927 ps
CPU time 67.68 seconds
Started Jan 10 01:30:44 PM PST 24
Finished Jan 10 01:31:53 PM PST 24
Peak memory 295344 kb
Host smart-9f42141b-90f0-4e87-8c65-e8ec93856340
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745079014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 48.sram_ctrl_throughput_w_partial_write.1745079014
Directory /workspace/48.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/49.sram_ctrl_access_during_key_req.1806808755
Short name T19
Test name
Test status
Simulation time 18621360186 ps
CPU time 1176.1 seconds
Started Jan 10 01:31:01 PM PST 24
Finished Jan 10 01:50:40 PM PST 24
Peak memory 379096 kb
Host smart-3a09776b-411b-4d8c-bcba-b66b31213927
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806808755 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 49.sram_ctrl_access_during_key_req.1806808755
Directory /workspace/49.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/49.sram_ctrl_alert_test.666935029
Short name T607
Test name
Test status
Simulation time 12249286 ps
CPU time 0.65 seconds
Started Jan 10 01:31:00 PM PST 24
Finished Jan 10 01:31:03 PM PST 24
Peak memory 201372 kb
Host smart-28e137ae-0af7-45bb-a5fe-7b30d564a0bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666935029 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.sram_ctrl_alert_test.666935029
Directory /workspace/49.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.sram_ctrl_lc_escalation.2211618253
Short name T519
Test name
Test status
Simulation time 193106498893 ps
CPU time 264.42 seconds
Started Jan 10 01:31:00 PM PST 24
Finished Jan 10 01:35:26 PM PST 24
Peak memory 202224 kb
Host smart-9c37420c-a1bb-47f0-8fd6-597e142c9074
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211618253 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_es
calation.2211618253
Directory /workspace/49.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/49.sram_ctrl_max_throughput.1913624795
Short name T491
Test name
Test status
Simulation time 5871481861 ps
CPU time 169.58 seconds
Started Jan 10 01:31:00 PM PST 24
Finished Jan 10 01:33:51 PM PST 24
Peak memory 366756 kb
Host smart-3aabce0d-d6c3-4b9f-8542-5e84126fd2d7
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913624795 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 49.sram_ctrl_max_throughput.1913624795
Directory /workspace/49.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/49.sram_ctrl_mem_partial_access.345219656
Short name T465
Test name
Test status
Simulation time 4734488705 ps
CPU time 76.09 seconds
Started Jan 10 01:31:00 PM PST 24
Finished Jan 10 01:32:19 PM PST 24
Peak memory 211228 kb
Host smart-b4d71111-83f8-485f-9b05-a7305d71d23a
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345219656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.sram_ctrl_mem_partial_access.345219656
Directory /workspace/49.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/49.sram_ctrl_mem_walk.2160696703
Short name T893
Test name
Test status
Simulation time 32824311886 ps
CPU time 255.68 seconds
Started Jan 10 01:31:03 PM PST 24
Finished Jan 10 01:35:22 PM PST 24
Peak memory 202216 kb
Host smart-1f1c309f-c347-4cb6-93de-0e6aeeb3f08a
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160696703 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctr
l_mem_walk.2160696703
Directory /workspace/49.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/49.sram_ctrl_multiple_keys.1481080848
Short name T930
Test name
Test status
Simulation time 40886636075 ps
CPU time 830.83 seconds
Started Jan 10 01:31:01 PM PST 24
Finished Jan 10 01:44:55 PM PST 24
Peak memory 380088 kb
Host smart-9287dc7d-19b2-4383-a489-9fe8530c2305
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481080848 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multi
ple_keys.1481080848
Directory /workspace/49.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/49.sram_ctrl_partial_access.3471243028
Short name T317
Test name
Test status
Simulation time 5449824438 ps
CPU time 35.13 seconds
Started Jan 10 01:31:02 PM PST 24
Finished Jan 10 01:31:41 PM PST 24
Peak memory 271716 kb
Host smart-4f312682-0b60-4e26-9da9-482567ba5c69
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471243028 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
sram_ctrl_partial_access.3471243028
Directory /workspace/49.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.3095454630
Short name T335
Test name
Test status
Simulation time 13732653822 ps
CPU time 350.96 seconds
Started Jan 10 01:31:01 PM PST 24
Finished Jan 10 01:36:55 PM PST 24
Peak memory 202172 kb
Host smart-8bc5e797-67e9-4a6c-bf3b-068f964b2e4c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095454630 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 49.sram_ctrl_partial_access_b2b.3095454630
Directory /workspace/49.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/49.sram_ctrl_ram_cfg.1860474506
Short name T482
Test name
Test status
Simulation time 377109209 ps
CPU time 6.34 seconds
Started Jan 10 01:31:01 PM PST 24
Finished Jan 10 01:31:11 PM PST 24
Peak memory 202400 kb
Host smart-5f71dd6b-c454-4429-acf5-d563620c13a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860474506 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.1860474506
Directory /workspace/49.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/49.sram_ctrl_regwen.2985268413
Short name T713
Test name
Test status
Simulation time 2186183177 ps
CPU time 53.43 seconds
Started Jan 10 01:31:02 PM PST 24
Finished Jan 10 01:31:59 PM PST 24
Peak memory 202076 kb
Host smart-58bdc7f3-9d3c-4916-96bc-b5d8718fcf64
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985268413 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.2985268413
Directory /workspace/49.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/49.sram_ctrl_smoke.3235034900
Short name T333
Test name
Test status
Simulation time 381318203 ps
CPU time 14.74 seconds
Started Jan 10 01:31:00 PM PST 24
Finished Jan 10 01:31:17 PM PST 24
Peak memory 202096 kb
Host smart-a60fa2f3-1b4b-470e-b6fe-94277d506622
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235034900 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.3235034900
Directory /workspace/49.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.214571261
Short name T873
Test name
Test status
Simulation time 4406147562 ps
CPU time 2387.72 seconds
Started Jan 10 01:31:00 PM PST 24
Finished Jan 10 02:10:51 PM PST 24
Peak memory 472276 kb
Host smart-65121150-2e9a-4c8f-93b8-52437d06c704
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=214571261 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all_with_rand_reset.214571261
Directory /workspace/49.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.sram_ctrl_stress_pipeline.720679141
Short name T589
Test name
Test status
Simulation time 9546755500 ps
CPU time 213.62 seconds
Started Jan 10 01:31:02 PM PST 24
Finished Jan 10 01:34:39 PM PST 24
Peak memory 202152 kb
Host smart-d85c26f1-1bba-4337-90c7-52756aaf6471
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720679141 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.sram_ctrl_stress_pipeline.720679141
Directory /workspace/49.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.4031177241
Short name T616
Test name
Test status
Simulation time 796098189 ps
CPU time 127.7 seconds
Started Jan 10 01:30:59 PM PST 24
Finished Jan 10 01:33:09 PM PST 24
Peak memory 370856 kb
Host smart-4ba5370d-8557-42cb-ad57-8547306bba9d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031177241 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.sram_ctrl_throughput_w_partial_write.4031177241
Directory /workspace/49.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/5.sram_ctrl_access_during_key_req.1704792105
Short name T578
Test name
Test status
Simulation time 7946906325 ps
CPU time 1333.5 seconds
Started Jan 10 01:26:33 PM PST 24
Finished Jan 10 01:49:01 PM PST 24
Peak memory 377048 kb
Host smart-d62dfebe-39c6-4893-bf52-c6a994b92502
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704792105 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.sram_ctrl_access_during_key_req.1704792105
Directory /workspace/5.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/5.sram_ctrl_alert_test.2369161571
Short name T815
Test name
Test status
Simulation time 44517538 ps
CPU time 0.64 seconds
Started Jan 10 01:26:36 PM PST 24
Finished Jan 10 01:26:52 PM PST 24
Peak memory 201856 kb
Host smart-ca9d6eaa-1ec9-45d9-9a20-b9e141fb99fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369161571 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.sram_ctrl_alert_test.2369161571
Directory /workspace/5.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.sram_ctrl_bijection.3441995019
Short name T341
Test name
Test status
Simulation time 58418726695 ps
CPU time 1273.14 seconds
Started Jan 10 01:26:44 PM PST 24
Finished Jan 10 01:48:12 PM PST 24
Peak memory 202160 kb
Host smart-8a1931e0-d2d1-4ef2-b4c0-8acf2f3be5a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441995019 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection.
3441995019
Directory /workspace/5.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/5.sram_ctrl_max_throughput.389635410
Short name T300
Test name
Test status
Simulation time 1125223249 ps
CPU time 28.16 seconds
Started Jan 10 01:26:33 PM PST 24
Finished Jan 10 01:27:14 PM PST 24
Peak memory 211108 kb
Host smart-10d56ef7-c7fb-4640-ac51-97d5ad122956
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389635410 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.sram_ctrl_max_throughput.389635410
Directory /workspace/5.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/5.sram_ctrl_mem_partial_access.4140206340
Short name T896
Test name
Test status
Simulation time 4673273655 ps
CPU time 76.22 seconds
Started Jan 10 01:26:27 PM PST 24
Finished Jan 10 01:27:57 PM PST 24
Peak memory 211244 kb
Host smart-05d5740c-e855-4d61-9bdc-ea831c02bc71
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140206340 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.sram_ctrl_mem_partial_access.4140206340
Directory /workspace/5.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/5.sram_ctrl_mem_walk.2856365282
Short name T374
Test name
Test status
Simulation time 21515706386 ps
CPU time 158.52 seconds
Started Jan 10 01:26:29 PM PST 24
Finished Jan 10 01:29:21 PM PST 24
Peak memory 202176 kb
Host smart-74925ff7-75d8-4300-bc8b-9f23a463584c
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856365282 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl
_mem_walk.2856365282
Directory /workspace/5.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/5.sram_ctrl_multiple_keys.2588062483
Short name T677
Test name
Test status
Simulation time 75426486858 ps
CPU time 1319.98 seconds
Started Jan 10 01:26:26 PM PST 24
Finished Jan 10 01:48:41 PM PST 24
Peak memory 380224 kb
Host smart-79439b75-c576-4c26-9cfc-8bffd18c7b5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588062483 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multip
le_keys.2588062483
Directory /workspace/5.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/5.sram_ctrl_partial_access.2686231217
Short name T603
Test name
Test status
Simulation time 1110462935 ps
CPU time 25.17 seconds
Started Jan 10 01:26:29 PM PST 24
Finished Jan 10 01:27:07 PM PST 24
Peak memory 202084 kb
Host smart-5e294d3c-8d77-4176-91ac-05041f9d8e27
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686231217 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.s
ram_ctrl_partial_access.2686231217
Directory /workspace/5.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.3220951993
Short name T545
Test name
Test status
Simulation time 144750316112 ps
CPU time 373.29 seconds
Started Jan 10 01:26:39 PM PST 24
Finished Jan 10 01:33:08 PM PST 24
Peak memory 210360 kb
Host smart-a08ee6b0-4529-4650-b49b-558af345ce1d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220951993 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 5.sram_ctrl_partial_access_b2b.3220951993
Directory /workspace/5.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/5.sram_ctrl_ram_cfg.1806227739
Short name T12
Test name
Test status
Simulation time 684779426 ps
CPU time 5.39 seconds
Started Jan 10 01:26:29 PM PST 24
Finished Jan 10 01:26:48 PM PST 24
Peak memory 202316 kb
Host smart-eb3ba742-dba3-46a2-96f6-a90dff7d578d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806227739 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.1806227739
Directory /workspace/5.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/5.sram_ctrl_regwen.372010396
Short name T489
Test name
Test status
Simulation time 14560021447 ps
CPU time 175.48 seconds
Started Jan 10 01:26:27 PM PST 24
Finished Jan 10 01:29:37 PM PST 24
Peak memory 361668 kb
Host smart-4e484720-7bc1-4d01-99f8-6009137e7c8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372010396 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.372010396
Directory /workspace/5.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/5.sram_ctrl_smoke.1555618485
Short name T548
Test name
Test status
Simulation time 1647271534 ps
CPU time 30.11 seconds
Started Jan 10 01:26:21 PM PST 24
Finished Jan 10 01:27:08 PM PST 24
Peak memory 202084 kb
Host smart-15a8b347-485d-4032-9a0b-d436ea676b83
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555618485 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.1555618485
Directory /workspace/5.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.4218954054
Short name T793
Test name
Test status
Simulation time 2352298125 ps
CPU time 4855.1 seconds
Started Jan 10 01:26:20 PM PST 24
Finished Jan 10 02:47:34 PM PST 24
Peak memory 439104 kb
Host smart-ddcd1413-9c84-4514-bc86-512afe283882
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4218954054 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all_with_rand_reset.4218954054
Directory /workspace/5.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.sram_ctrl_stress_pipeline.4018727553
Short name T784
Test name
Test status
Simulation time 3092205765 ps
CPU time 166.66 seconds
Started Jan 10 01:26:29 PM PST 24
Finished Jan 10 01:29:29 PM PST 24
Peak memory 202140 kb
Host smart-b659b8af-dc0f-420f-bee9-a01039185040
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018727553 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.sram_ctrl_stress_pipeline.4018727553
Directory /workspace/5.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.915472782
Short name T372
Test name
Test status
Simulation time 1569070728 ps
CPU time 148.01 seconds
Started Jan 10 01:26:25 PM PST 24
Finished Jan 10 01:29:08 PM PST 24
Peak memory 365764 kb
Host smart-f1b89813-37ec-4872-b6e8-705f914f03b2
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915472782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 5.sram_ctrl_throughput_w_partial_write.915472782
Directory /workspace/5.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/6.sram_ctrl_access_during_key_req.341895051
Short name T812
Test name
Test status
Simulation time 31058888990 ps
CPU time 1169.13 seconds
Started Jan 10 01:26:30 PM PST 24
Finished Jan 10 01:46:12 PM PST 24
Peak memory 378080 kb
Host smart-bd9d771f-ccaa-4e75-b845-ae2f7f5954f4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341895051 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 6.sram_ctrl_access_during_key_req.341895051
Directory /workspace/6.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/6.sram_ctrl_alert_test.603748026
Short name T584
Test name
Test status
Simulation time 12039510 ps
CPU time 0.63 seconds
Started Jan 10 01:26:54 PM PST 24
Finished Jan 10 01:27:06 PM PST 24
Peak memory 201920 kb
Host smart-4489a1b9-04d7-43f3-8d1a-a0db527bd5bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603748026 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.sram_ctrl_alert_test.603748026
Directory /workspace/6.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.sram_ctrl_bijection.541873981
Short name T741
Test name
Test status
Simulation time 634892088467 ps
CPU time 1170.79 seconds
Started Jan 10 01:26:25 PM PST 24
Finished Jan 10 01:46:11 PM PST 24
Peak memory 202108 kb
Host smart-19700c53-52b5-4932-a5ea-dbd8ebdacea7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541873981 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection.541873981
Directory /workspace/6.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/6.sram_ctrl_lc_escalation.66391422
Short name T332
Test name
Test status
Simulation time 28009778708 ps
CPU time 191.33 seconds
Started Jan 10 01:26:42 PM PST 24
Finished Jan 10 01:30:08 PM PST 24
Peak memory 214376 kb
Host smart-4dd0effd-4796-4cf8-bbbe-1d5c4cc613e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66391422 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_esc
alation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_lc_escal
ation.66391422
Directory /workspace/6.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/6.sram_ctrl_max_throughput.3608730531
Short name T258
Test name
Test status
Simulation time 5416827049 ps
CPU time 110.76 seconds
Started Jan 10 01:26:33 PM PST 24
Finished Jan 10 01:28:38 PM PST 24
Peak memory 356644 kb
Host smart-7514a54f-396d-4cc9-9359-67ce9a4dd3dd
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608730531 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 6.sram_ctrl_max_throughput.3608730531
Directory /workspace/6.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/6.sram_ctrl_mem_partial_access.3507945047
Short name T66
Test name
Test status
Simulation time 4800864320 ps
CPU time 76.32 seconds
Started Jan 10 01:26:32 PM PST 24
Finished Jan 10 01:28:01 PM PST 24
Peak memory 210660 kb
Host smart-03b6affc-e742-4e03-b498-96c378d03c18
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507945047 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.sram_ctrl_mem_partial_access.3507945047
Directory /workspace/6.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/6.sram_ctrl_mem_walk.3455863196
Short name T427
Test name
Test status
Simulation time 47475244662 ps
CPU time 281.99 seconds
Started Jan 10 01:26:32 PM PST 24
Finished Jan 10 01:31:27 PM PST 24
Peak memory 202312 kb
Host smart-bf1b5970-7f41-4bd6-9a15-f78b99913edc
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455863196 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl
_mem_walk.3455863196
Directory /workspace/6.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/6.sram_ctrl_multiple_keys.1797652454
Short name T483
Test name
Test status
Simulation time 8397425930 ps
CPU time 852.84 seconds
Started Jan 10 01:26:24 PM PST 24
Finished Jan 10 01:40:52 PM PST 24
Peak memory 378148 kb
Host smart-188c1093-c8ba-4e80-bcb5-bf6680f5bc86
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797652454 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multip
le_keys.1797652454
Directory /workspace/6.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/6.sram_ctrl_partial_access.2849531262
Short name T595
Test name
Test status
Simulation time 1380507863 ps
CPU time 13.63 seconds
Started Jan 10 01:26:26 PM PST 24
Finished Jan 10 01:26:54 PM PST 24
Peak memory 202068 kb
Host smart-47a0a0df-0629-4656-ba49-556d7eac159c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849531262 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.s
ram_ctrl_partial_access.2849531262
Directory /workspace/6.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.1117017383
Short name T856
Test name
Test status
Simulation time 11370788146 ps
CPU time 355.97 seconds
Started Jan 10 01:26:34 PM PST 24
Finished Jan 10 01:32:44 PM PST 24
Peak memory 202100 kb
Host smart-b921842c-6b61-49d4-9e95-089da9473672
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117017383 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 6.sram_ctrl_partial_access_b2b.1117017383
Directory /workspace/6.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/6.sram_ctrl_ram_cfg.2679322594
Short name T714
Test name
Test status
Simulation time 762120745 ps
CPU time 13.74 seconds
Started Jan 10 01:26:42 PM PST 24
Finished Jan 10 01:27:12 PM PST 24
Peak memory 202456 kb
Host smart-23d21cf9-7e68-4362-b413-ecb932dd8aa0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679322594 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.2679322594
Directory /workspace/6.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/6.sram_ctrl_regwen.948510193
Short name T777
Test name
Test status
Simulation time 24568280749 ps
CPU time 771.72 seconds
Started Jan 10 01:26:35 PM PST 24
Finished Jan 10 01:39:41 PM PST 24
Peak memory 375920 kb
Host smart-66f5022a-6002-4279-95e2-37995086bcc0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948510193 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.948510193
Directory /workspace/6.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/6.sram_ctrl_smoke.3856496586
Short name T808
Test name
Test status
Simulation time 5417995991 ps
CPU time 41.6 seconds
Started Jan 10 01:26:33 PM PST 24
Finished Jan 10 01:27:28 PM PST 24
Peak memory 259756 kb
Host smart-f4e5a093-8ab0-4b9f-b978-1a0de6f91cf5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856496586 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.3856496586
Directory /workspace/6.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/6.sram_ctrl_stress_all.3750991697
Short name T654
Test name
Test status
Simulation time 72910458237 ps
CPU time 2115.4 seconds
Started Jan 10 01:26:41 PM PST 24
Finished Jan 10 02:02:12 PM PST 24
Peak memory 376756 kb
Host smart-8ad3ea4b-db41-422d-8829-9ed7c9adf791
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750991697 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 6.sram_ctrl_stress_all.3750991697
Directory /workspace/6.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.1623031368
Short name T648
Test name
Test status
Simulation time 739642564 ps
CPU time 2982.8 seconds
Started Jan 10 01:26:26 PM PST 24
Finished Jan 10 02:16:24 PM PST 24
Peak memory 433788 kb
Host smart-95518c5d-e82f-49a5-999a-cb99525fe73e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1623031368 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all_with_rand_reset.1623031368
Directory /workspace/6.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.sram_ctrl_stress_pipeline.3834076715
Short name T223
Test name
Test status
Simulation time 6043341621 ps
CPU time 432.87 seconds
Started Jan 10 01:26:38 PM PST 24
Finished Jan 10 01:34:06 PM PST 24
Peak memory 210384 kb
Host smart-8252a55a-2bf7-4293-8027-7ef9a53eecfe
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834076715 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.sram_ctrl_stress_pipeline.3834076715
Directory /workspace/6.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.1239654970
Short name T564
Test name
Test status
Simulation time 752105324 ps
CPU time 72.78 seconds
Started Jan 10 01:26:31 PM PST 24
Finished Jan 10 01:27:56 PM PST 24
Peak memory 308576 kb
Host smart-81dbd1ad-ceae-4d45-8c51-735220382df7
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239654970 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.sram_ctrl_throughput_w_partial_write.1239654970
Directory /workspace/6.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/7.sram_ctrl_access_during_key_req.3649932855
Short name T526
Test name
Test status
Simulation time 3573838165 ps
CPU time 405.98 seconds
Started Jan 10 01:26:47 PM PST 24
Finished Jan 10 01:33:47 PM PST 24
Peak memory 373976 kb
Host smart-36a0380b-9a22-4879-b8bc-a570aab5ea91
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649932855 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.sram_ctrl_access_during_key_req.3649932855
Directory /workspace/7.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/7.sram_ctrl_alert_test.694952824
Short name T382
Test name
Test status
Simulation time 13431091 ps
CPU time 0.64 seconds
Started Jan 10 01:26:28 PM PST 24
Finished Jan 10 01:26:42 PM PST 24
Peak memory 201456 kb
Host smart-3d3e94d4-1c0b-41f3-b3a3-dba4b8b9fa26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694952824 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.sram_ctrl_alert_test.694952824
Directory /workspace/7.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.sram_ctrl_bijection.1491353660
Short name T902
Test name
Test status
Simulation time 34491089547 ps
CPU time 925.89 seconds
Started Jan 10 01:26:42 PM PST 24
Finished Jan 10 01:42:24 PM PST 24
Peak memory 202088 kb
Host smart-c6a1da3b-1caf-4a46-ac46-b7df048f381f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491353660 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection.
1491353660
Directory /workspace/7.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/7.sram_ctrl_lc_escalation.2940569686
Short name T821
Test name
Test status
Simulation time 10043251386 ps
CPU time 99.76 seconds
Started Jan 10 01:26:55 PM PST 24
Finished Jan 10 01:28:47 PM PST 24
Peak memory 210376 kb
Host smart-f3514900-344b-484f-ace7-6ef77bf78516
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940569686 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_lc_esc
alation.2940569686
Directory /workspace/7.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/7.sram_ctrl_max_throughput.2030229319
Short name T786
Test name
Test status
Simulation time 4413852792 ps
CPU time 45.5 seconds
Started Jan 10 01:26:48 PM PST 24
Finished Jan 10 01:27:47 PM PST 24
Peak memory 267616 kb
Host smart-8f92f916-d775-4f91-96e5-d7f0cfe77112
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030229319 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 7.sram_ctrl_max_throughput.2030229319
Directory /workspace/7.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/7.sram_ctrl_mem_partial_access.792872457
Short name T870
Test name
Test status
Simulation time 2698620096 ps
CPU time 81.08 seconds
Started Jan 10 01:26:38 PM PST 24
Finished Jan 10 01:28:14 PM PST 24
Peak memory 211012 kb
Host smart-daf515f9-f604-456c-861b-cd60124de225
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792872457 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
sram_ctrl_mem_partial_access.792872457
Directory /workspace/7.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/7.sram_ctrl_mem_walk.2350801636
Short name T719
Test name
Test status
Simulation time 3944468294 ps
CPU time 236.04 seconds
Started Jan 10 01:26:36 PM PST 24
Finished Jan 10 01:30:48 PM PST 24
Peak memory 202180 kb
Host smart-2252a29a-ca00-4015-901a-b38861c82f6f
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350801636 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl
_mem_walk.2350801636
Directory /workspace/7.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/7.sram_ctrl_multiple_keys.3948868132
Short name T795
Test name
Test status
Simulation time 42181219336 ps
CPU time 627.21 seconds
Started Jan 10 01:26:43 PM PST 24
Finished Jan 10 01:37:26 PM PST 24
Peak memory 379140 kb
Host smart-9238aa0f-1bc9-40f9-9d3a-c80fe792c6ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948868132 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multip
le_keys.3948868132
Directory /workspace/7.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/7.sram_ctrl_partial_access.2831912743
Short name T385
Test name
Test status
Simulation time 1139350449 ps
CPU time 13.21 seconds
Started Jan 10 01:26:42 PM PST 24
Finished Jan 10 01:27:11 PM PST 24
Peak memory 232664 kb
Host smart-03fa55c7-06ac-4b86-8340-fb8a1c40a5da
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831912743 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.s
ram_ctrl_partial_access.2831912743
Directory /workspace/7.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.4040513980
Short name T467
Test name
Test status
Simulation time 79349228817 ps
CPU time 474.81 seconds
Started Jan 10 01:26:44 PM PST 24
Finished Jan 10 01:34:54 PM PST 24
Peak memory 210392 kb
Host smart-db619e83-ac16-4df4-9917-0ede858d92ac
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040513980 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 7.sram_ctrl_partial_access_b2b.4040513980
Directory /workspace/7.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/7.sram_ctrl_ram_cfg.3402089152
Short name T638
Test name
Test status
Simulation time 362399840 ps
CPU time 12.67 seconds
Started Jan 10 01:26:51 PM PST 24
Finished Jan 10 01:27:16 PM PST 24
Peak memory 202392 kb
Host smart-2bd1b4ae-47d5-481c-a6cf-e6d42ba140a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402089152 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.3402089152
Directory /workspace/7.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/7.sram_ctrl_regwen.1979547101
Short name T31
Test name
Test status
Simulation time 1632580704 ps
CPU time 451.79 seconds
Started Jan 10 01:26:55 PM PST 24
Finished Jan 10 01:34:39 PM PST 24
Peak memory 370844 kb
Host smart-236398ef-776e-4c04-a4c7-562bc6e306b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979547101 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.1979547101
Directory /workspace/7.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/7.sram_ctrl_smoke.2416454643
Short name T265
Test name
Test status
Simulation time 1105409183 ps
CPU time 62.49 seconds
Started Jan 10 01:26:25 PM PST 24
Finished Jan 10 01:27:43 PM PST 24
Peak memory 307412 kb
Host smart-26fb74bd-0ef8-4cf6-a847-996a2fc5c070
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416454643 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.2416454643
Directory /workspace/7.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.1010595551
Short name T488
Test name
Test status
Simulation time 694787648 ps
CPU time 5340.11 seconds
Started Jan 10 01:26:31 PM PST 24
Finished Jan 10 02:55:44 PM PST 24
Peak memory 772744 kb
Host smart-8cbca52b-2ac2-4200-9021-8c5d3b1dbe4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1010595551 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all_with_rand_reset.1010595551
Directory /workspace/7.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.sram_ctrl_stress_pipeline.1980828383
Short name T476
Test name
Test status
Simulation time 6425930120 ps
CPU time 133.89 seconds
Started Jan 10 01:26:42 PM PST 24
Finished Jan 10 01:29:12 PM PST 24
Peak memory 202172 kb
Host smart-267724b4-d2e4-4582-bca8-e28c19c1505e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980828383 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.sram_ctrl_stress_pipeline.1980828383
Directory /workspace/7.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.954848476
Short name T124
Test name
Test status
Simulation time 2847895209 ps
CPU time 29.93 seconds
Started Jan 10 01:26:56 PM PST 24
Finished Jan 10 01:27:37 PM PST 24
Peak memory 224892 kb
Host smart-12d1e462-ca9f-4614-bfa4-e2e115dc62ca
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954848476 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 7.sram_ctrl_throughput_w_partial_write.954848476
Directory /workspace/7.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/8.sram_ctrl_access_during_key_req.3811453630
Short name T583
Test name
Test status
Simulation time 21920420457 ps
CPU time 1134.28 seconds
Started Jan 10 01:26:44 PM PST 24
Finished Jan 10 01:45:54 PM PST 24
Peak memory 378124 kb
Host smart-1850aa49-e836-479b-be95-cfea575276b7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811453630 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.sram_ctrl_access_during_key_req.3811453630
Directory /workspace/8.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/8.sram_ctrl_alert_test.2370849867
Short name T215
Test name
Test status
Simulation time 35667796 ps
CPU time 0.63 seconds
Started Jan 10 01:26:29 PM PST 24
Finished Jan 10 01:26:43 PM PST 24
Peak memory 201820 kb
Host smart-9bf6323f-d07f-4b64-a9a8-c03ad3084203
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370849867 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.sram_ctrl_alert_test.2370849867
Directory /workspace/8.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.sram_ctrl_executable.2425643009
Short name T110
Test name
Test status
Simulation time 66385137200 ps
CPU time 178.57 seconds
Started Jan 10 01:26:22 PM PST 24
Finished Jan 10 01:29:37 PM PST 24
Peak memory 352312 kb
Host smart-0090f6af-3fbe-4e5d-b78d-932d9ef41715
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425643009 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_executabl
e.2425643009
Directory /workspace/8.sram_ctrl_executable/latest

Test location /workspace/coverage/default/8.sram_ctrl_lc_escalation.3398968644
Short name T27
Test name
Test status
Simulation time 3643904415 ps
CPU time 99.17 seconds
Started Jan 10 01:26:44 PM PST 24
Finished Jan 10 01:28:38 PM PST 24
Peak memory 210408 kb
Host smart-956d9bf2-95b4-416a-9ca6-595405307a4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398968644 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_esc
alation.3398968644
Directory /workspace/8.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/8.sram_ctrl_max_throughput.2227843578
Short name T694
Test name
Test status
Simulation time 724391161 ps
CPU time 48.93 seconds
Started Jan 10 01:26:32 PM PST 24
Finished Jan 10 01:27:34 PM PST 24
Peak memory 283984 kb
Host smart-a5fecca4-cc49-4dbb-bf99-ed5bed5d4ddc
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227843578 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 8.sram_ctrl_max_throughput.2227843578
Directory /workspace/8.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/8.sram_ctrl_mem_partial_access.4233225401
Short name T505
Test name
Test status
Simulation time 2362555286 ps
CPU time 77.77 seconds
Started Jan 10 01:26:26 PM PST 24
Finished Jan 10 01:27:58 PM PST 24
Peak memory 210844 kb
Host smart-3e366301-6591-4c9a-905a-390637376dfc
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233225401 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.sram_ctrl_mem_partial_access.4233225401
Directory /workspace/8.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/8.sram_ctrl_mem_walk.2891767920
Short name T454
Test name
Test status
Simulation time 9988874719 ps
CPU time 157.29 seconds
Started Jan 10 01:26:37 PM PST 24
Finished Jan 10 01:29:29 PM PST 24
Peak memory 202220 kb
Host smart-e3ffe1a2-62fd-40a8-8cf9-a1624d95eec4
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891767920 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl
_mem_walk.2891767920
Directory /workspace/8.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/8.sram_ctrl_multiple_keys.1525583476
Short name T800
Test name
Test status
Simulation time 14120952766 ps
CPU time 935.34 seconds
Started Jan 10 01:26:32 PM PST 24
Finished Jan 10 01:42:20 PM PST 24
Peak memory 360960 kb
Host smart-2fa30620-4bb3-4ca0-917e-5c78faa1ee25
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525583476 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multip
le_keys.1525583476
Directory /workspace/8.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/8.sram_ctrl_partial_access.852191049
Short name T394
Test name
Test status
Simulation time 835619664 ps
CPU time 20.23 seconds
Started Jan 10 01:26:45 PM PST 24
Finished Jan 10 01:27:20 PM PST 24
Peak memory 229788 kb
Host smart-3168f55e-746e-453c-9539-fd121e8cc215
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852191049 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sr
am_ctrl_partial_access.852191049
Directory /workspace/8.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.3373236843
Short name T594
Test name
Test status
Simulation time 16843330391 ps
CPU time 425.48 seconds
Started Jan 10 01:26:33 PM PST 24
Finished Jan 10 01:33:52 PM PST 24
Peak memory 202144 kb
Host smart-3932c291-41bc-4ece-833d-f5536f6df167
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373236843 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 8.sram_ctrl_partial_access_b2b.3373236843
Directory /workspace/8.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/8.sram_ctrl_ram_cfg.2128845892
Short name T305
Test name
Test status
Simulation time 1413077614 ps
CPU time 6.66 seconds
Started Jan 10 01:26:22 PM PST 24
Finished Jan 10 01:26:46 PM PST 24
Peak memory 202276 kb
Host smart-85c899b3-2ef4-4068-b652-c25c12634196
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128845892 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.2128845892
Directory /workspace/8.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/8.sram_ctrl_regwen.3378771520
Short name T37
Test name
Test status
Simulation time 9097459615 ps
CPU time 180.59 seconds
Started Jan 10 01:26:34 PM PST 24
Finished Jan 10 01:29:48 PM PST 24
Peak memory 329040 kb
Host smart-d3309d15-6273-4961-b224-902bfc2c8297
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378771520 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.3378771520
Directory /workspace/8.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/8.sram_ctrl_smoke.1808318382
Short name T469
Test name
Test status
Simulation time 4441281479 ps
CPU time 24.99 seconds
Started Jan 10 01:26:27 PM PST 24
Finished Jan 10 01:27:06 PM PST 24
Peak memory 202132 kb
Host smart-4e3904b8-f3cd-44eb-9da7-fb5ff8210217
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808318382 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.1808318382
Directory /workspace/8.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/8.sram_ctrl_stress_all.2117381724
Short name T730
Test name
Test status
Simulation time 478100834475 ps
CPU time 5692.74 seconds
Started Jan 10 01:26:30 PM PST 24
Finished Jan 10 03:01:36 PM PST 24
Peak memory 381184 kb
Host smart-c35989cc-bf93-43ec-a325-f69126b0a4b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117381724 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 8.sram_ctrl_stress_all.2117381724
Directory /workspace/8.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.4196419675
Short name T408
Test name
Test status
Simulation time 239747764 ps
CPU time 2946.01 seconds
Started Jan 10 01:26:28 PM PST 24
Finished Jan 10 02:15:48 PM PST 24
Peak memory 665944 kb
Host smart-d152ea2b-92e2-4b49-b020-ad0424c0eb76
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4196419675 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all_with_rand_reset.4196419675
Directory /workspace/8.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.sram_ctrl_stress_pipeline.3234769497
Short name T8
Test name
Test status
Simulation time 3467644235 ps
CPU time 241.54 seconds
Started Jan 10 01:26:25 PM PST 24
Finished Jan 10 01:30:42 PM PST 24
Peak memory 202060 kb
Host smart-1ec42d71-8816-4e56-95bf-45ba7767f170
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234769497 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.sram_ctrl_stress_pipeline.3234769497
Directory /workspace/8.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.2416509491
Short name T853
Test name
Test status
Simulation time 4602700854 ps
CPU time 150.54 seconds
Started Jan 10 01:26:34 PM PST 24
Finished Jan 10 01:29:18 PM PST 24
Peak memory 366776 kb
Host smart-a6e7a3a0-e746-4b30-b3c1-2c21fc5164b0
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416509491 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.sram_ctrl_throughput_w_partial_write.2416509491
Directory /workspace/8.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/9.sram_ctrl_access_during_key_req.2926757477
Short name T810
Test name
Test status
Simulation time 7208731060 ps
CPU time 109.39 seconds
Started Jan 10 01:26:37 PM PST 24
Finished Jan 10 01:28:41 PM PST 24
Peak memory 272672 kb
Host smart-c626126f-cffa-43f9-b60b-911bb29ee139
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926757477 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.sram_ctrl_access_during_key_req.2926757477
Directory /workspace/9.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/9.sram_ctrl_alert_test.890020247
Short name T787
Test name
Test status
Simulation time 46898991 ps
CPU time 0.63 seconds
Started Jan 10 01:26:41 PM PST 24
Finished Jan 10 01:26:57 PM PST 24
Peak memory 201828 kb
Host smart-5b5832e4-2c30-480f-b7a0-be12923e9b49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890020247 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.sram_ctrl_alert_test.890020247
Directory /workspace/9.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.sram_ctrl_bijection.4173726323
Short name T555
Test name
Test status
Simulation time 22176056671 ps
CPU time 558.98 seconds
Started Jan 10 01:26:44 PM PST 24
Finished Jan 10 01:36:18 PM PST 24
Peak memory 202168 kb
Host smart-09e717cd-cf0a-47a2-825b-a720951a2a28
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173726323 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection.
4173726323
Directory /workspace/9.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/9.sram_ctrl_max_throughput.957847992
Short name T935
Test name
Test status
Simulation time 3050474481 ps
CPU time 61.44 seconds
Started Jan 10 01:26:34 PM PST 24
Finished Jan 10 01:27:49 PM PST 24
Peak memory 311936 kb
Host smart-8a7c7449-b00b-4df2-b70c-9046b6c76ba4
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957847992 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.sram_ctrl_max_throughput.957847992
Directory /workspace/9.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/9.sram_ctrl_mem_partial_access.3780676442
Short name T424
Test name
Test status
Simulation time 2422578948 ps
CPU time 73.66 seconds
Started Jan 10 01:26:28 PM PST 24
Finished Jan 10 01:27:55 PM PST 24
Peak memory 211248 kb
Host smart-2ffa3caa-0351-4c2d-8537-4b2ecc450dc0
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780676442 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.sram_ctrl_mem_partial_access.3780676442
Directory /workspace/9.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/9.sram_ctrl_mem_walk.408966145
Short name T243
Test name
Test status
Simulation time 16425763602 ps
CPU time 246.06 seconds
Started Jan 10 01:26:44 PM PST 24
Finished Jan 10 01:31:05 PM PST 24
Peak memory 202240 kb
Host smart-b049e72d-e726-4750-960d-7db2dde5baca
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408966145 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_
mem_walk.408966145
Directory /workspace/9.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/9.sram_ctrl_multiple_keys.3667701015
Short name T684
Test name
Test status
Simulation time 18118313644 ps
CPU time 1617.94 seconds
Started Jan 10 01:26:22 PM PST 24
Finished Jan 10 01:53:37 PM PST 24
Peak memory 379164 kb
Host smart-6c8af2ec-a9e6-4bb0-899b-e6bd029c5b38
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667701015 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multip
le_keys.3667701015
Directory /workspace/9.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/9.sram_ctrl_partial_access.3557694007
Short name T608
Test name
Test status
Simulation time 365447034 ps
CPU time 14.28 seconds
Started Jan 10 01:26:43 PM PST 24
Finished Jan 10 01:27:13 PM PST 24
Peak memory 202144 kb
Host smart-7f3ccb07-8ad3-4787-a0bf-ecb6e5ec4989
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557694007 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.s
ram_ctrl_partial_access.3557694007
Directory /workspace/9.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.592860324
Short name T379
Test name
Test status
Simulation time 86064875229 ps
CPU time 605.19 seconds
Started Jan 10 01:26:32 PM PST 24
Finished Jan 10 01:36:50 PM PST 24
Peak memory 202160 kb
Host smart-31dec7fb-6b17-4096-b8ce-f9e714d490b3
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592860324 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.sram_ctrl_partial_access_b2b.592860324
Directory /workspace/9.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/9.sram_ctrl_ram_cfg.3972320821
Short name T239
Test name
Test status
Simulation time 3035406993 ps
CPU time 14.11 seconds
Started Jan 10 01:26:22 PM PST 24
Finished Jan 10 01:26:53 PM PST 24
Peak memory 202456 kb
Host smart-bacbd06d-259c-4d85-9adf-0760c662e960
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972320821 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.3972320821
Directory /workspace/9.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/9.sram_ctrl_regwen.1807168636
Short name T844
Test name
Test status
Simulation time 2382805543 ps
CPU time 443.51 seconds
Started Jan 10 01:26:35 PM PST 24
Finished Jan 10 01:34:13 PM PST 24
Peak memory 376172 kb
Host smart-8ee9988e-bd44-45b9-800e-1dcf0f74a6ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807168636 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.1807168636
Directory /workspace/9.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/9.sram_ctrl_smoke.1994926934
Short name T231
Test name
Test status
Simulation time 1995705002 ps
CPU time 8.42 seconds
Started Jan 10 01:26:47 PM PST 24
Finished Jan 10 01:27:10 PM PST 24
Peak memory 202104 kb
Host smart-29554611-a378-4d7b-b9b6-be80d993b1e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994926934 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.1994926934
Directory /workspace/9.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3901821450
Short name T773
Test name
Test status
Simulation time 1220750717 ps
CPU time 2132.75 seconds
Started Jan 10 01:26:31 PM PST 24
Finished Jan 10 02:02:16 PM PST 24
Peak memory 476728 kb
Host smart-dd0ffd37-987a-436a-a560-f36e40cc22d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3901821450 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all_with_rand_reset.3901821450
Directory /workspace/9.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.sram_ctrl_stress_pipeline.3158269088
Short name T801
Test name
Test status
Simulation time 17044232164 ps
CPU time 309.2 seconds
Started Jan 10 01:26:22 PM PST 24
Finished Jan 10 01:31:48 PM PST 24
Peak memory 202036 kb
Host smart-5332bfab-89ec-43c0-810d-de745cb57981
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158269088 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.sram_ctrl_stress_pipeline.3158269088
Directory /workspace/9.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.2253947048
Short name T362
Test name
Test status
Simulation time 1543305980 ps
CPU time 61.47 seconds
Started Jan 10 01:26:42 PM PST 24
Finished Jan 10 01:27:59 PM PST 24
Peak memory 295168 kb
Host smart-92312753-29f8-4a80-9512-8f79db9ab456
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253947048 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.sram_ctrl_throughput_w_partial_write.2253947048
Directory /workspace/9.sram_ctrl_throughput_w_partial_write/latest
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