Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	288932636	1			T1	4922		T2	327696		T3	1328
instr_valid_dis	263684178	1			T1	4922		T2	327696		T3	1328
instr_en	14123283	1			T17	40684		T18	185784		T51	4

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	5889186	1			T16	24752		T18	65606		T36	13960
sram_ifetch_valid_disable	262145664	1			T1	4922		T2	327696		T3	1328
sram_ifetch_enable	20897786	1			T16	140828		T17	21284		T18	26632

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	288932636	1			T1	4922		T2	327696		T3	1328
hw_debug_en_valid_off	263474931	1			T1	4922		T2	327696		T3	1328
hw_debug_en_on	18485013	1			T16	108632		T18	67858		T36	132792

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	262145664	1			T1	4922		T2	327696		T3	1328
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	251254186	1			T1	4922		T2	327696		T3	1328
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	5114067	1			T17	39734		T18	93546		T51	4
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	2461314	1			T16	24752		T18	20000		T28	12488
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	803094	1			T126	65264		T122	67784		T124	101662
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1088234	1			T18	20000		T29	25130		T121	39314
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	2229310	1			T18	27332		T36	13960		T35	19146
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	873192	1			T122	36126		T109	85866		T127	15454
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	937412	1			T18	27332		T35	8076		T29	28424
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	5191395	1			T16	33050		T18	18068		T36	73784
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	2118616	1			T36	33046		T121	58762		T122	98126
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	2072061	1			T18	18068		T36	40738		T35	72620

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	6387306	1			T17	950		T18	26632		T36	45048
lc_exec_en	11064308	1			T16	75582		T18	22458		T36	45048
valid_exec_dis	264896055	1			T1	4922		T2	327696		T3	1328
invalid_exec_dis	26786972	1			T16	165580		T17	21284		T18	92238