Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	121540939	1			T1	2037		T2	148717		T3	199
triple_byte_access	2598133	1			T1	79		T2	2975		T3	3
halfword_access	3994337	1			T1	123		T2	4510		T3	7
byte_access	5611752	1			T1	175		T2	6093		T3	7
zero_access	1723172	1			T1	47		T2	1553		T3	2

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

67134493

1

T1

1203

T2

82401

T3

113

auto[1]

68333840

1

T1

1258

T2

81447

T3

105

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	60072162	1			T1	1002		T2	74810		T3	102
auto[0]	triple_byte_access	1224268	1			T1	42		T2	1455		T3	1
auto[0]	halfword_access	1936330	1			T1	54		T2	2240		T3	7
auto[0]	byte_access	2864246	1			T1	85		T2	3113		T3	3
auto[0]	zero_access	1037487	1			T1	20		T2	783		T4	484
auto[1]	word_access	61468777	1			T1	1035		T2	73907		T3	97
auto[1]	triple_byte_access	1373865	1			T1	37		T2	1520		T3	2
auto[1]	halfword_access	2058007	1			T1	69		T2	2270		T4	1439
auto[1]	byte_access	2747506	1			T1	90		T2	2980		T3	4
auto[1]	zero_access	685685	1			T1	27		T2	770		T3	2