Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.67 100.00 98.27 100.00 100.00 99.71 99.70 100.00


Total test records in report: 990
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
T751 /workspace/coverage/default/15.sram_ctrl_executable.2522141934 Jan 14 02:19:53 PM PST 24 Jan 14 02:39:07 PM PST 24 49884929765 ps
T752 /workspace/coverage/default/4.sram_ctrl_access_during_key_req.3900646685 Jan 14 02:14:05 PM PST 24 Jan 14 02:35:56 PM PST 24 5581701251 ps
T753 /workspace/coverage/default/45.sram_ctrl_access_during_key_req.2849211753 Jan 14 02:32:39 PM PST 24 Jan 14 02:46:38 PM PST 24 10819315864 ps
T754 /workspace/coverage/default/6.sram_ctrl_lc_escalation.1606132382 Jan 14 02:15:23 PM PST 24 Jan 14 02:16:47 PM PST 24 8800062600 ps
T755 /workspace/coverage/default/5.sram_ctrl_mem_partial_access.1950189158 Jan 14 02:15:01 PM PST 24 Jan 14 02:16:20 PM PST 24 2411360548 ps
T756 /workspace/coverage/default/12.sram_ctrl_stress_all.3752578457 Jan 14 02:18:22 PM PST 24 Jan 14 04:12:42 PM PST 24 201603584648 ps
T757 /workspace/coverage/default/48.sram_ctrl_regwen.1091047074 Jan 14 02:33:42 PM PST 24 Jan 14 02:49:55 PM PST 24 7821830756 ps
T758 /workspace/coverage/default/2.sram_ctrl_max_throughput.2980505020 Jan 14 02:12:47 PM PST 24 Jan 14 02:13:15 PM PST 24 1357555483 ps
T759 /workspace/coverage/default/23.sram_ctrl_max_throughput.62833560 Jan 14 02:23:40 PM PST 24 Jan 14 02:27:07 PM PST 24 1735159698 ps
T760 /workspace/coverage/default/16.sram_ctrl_ram_cfg.3507251387 Jan 14 02:20:23 PM PST 24 Jan 14 02:20:37 PM PST 24 361145773 ps
T761 /workspace/coverage/default/0.sram_ctrl_partial_access.3211309676 Jan 14 02:11:35 PM PST 24 Jan 14 02:14:13 PM PST 24 523884318 ps
T762 /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.1858055134 Jan 14 02:19:48 PM PST 24 Jan 14 02:20:42 PM PST 24 1508928467 ps
T763 /workspace/coverage/default/7.sram_ctrl_alert_test.3103211606 Jan 14 02:16:13 PM PST 24 Jan 14 02:16:15 PM PST 24 15925001 ps
T764 /workspace/coverage/default/40.sram_ctrl_partial_access.1462826980 Jan 14 02:30:47 PM PST 24 Jan 14 02:31:30 PM PST 24 968495750 ps
T765 /workspace/coverage/default/27.sram_ctrl_bijection.3004909512 Jan 14 02:26:04 PM PST 24 Jan 14 02:37:28 PM PST 24 9940872689 ps
T766 /workspace/coverage/default/32.sram_ctrl_mem_partial_access.1400316549 Jan 14 02:27:52 PM PST 24 Jan 14 02:29:18 PM PST 24 3481399233 ps
T767 /workspace/coverage/default/18.sram_ctrl_smoke.826045447 Jan 14 02:21:01 PM PST 24 Jan 14 02:21:20 PM PST 24 3767746103 ps
T768 /workspace/coverage/default/21.sram_ctrl_mem_walk.2901108143 Jan 14 02:22:51 PM PST 24 Jan 14 02:28:21 PM PST 24 82525361209 ps
T769 /workspace/coverage/default/14.sram_ctrl_max_throughput.384010285 Jan 14 02:19:18 PM PST 24 Jan 14 02:20:48 PM PST 24 790909446 ps
T770 /workspace/coverage/default/46.sram_ctrl_stress_all.193755914 Jan 14 02:33:13 PM PST 24 Jan 14 04:31:03 PM PST 24 372693894608 ps
T771 /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.478231901 Jan 14 02:28:35 PM PST 24 Jan 14 03:52:04 PM PST 24 1504414798 ps
T772 /workspace/coverage/default/46.sram_ctrl_regwen.3919430472 Jan 14 02:33:02 PM PST 24 Jan 14 02:46:26 PM PST 24 39075450290 ps
T773 /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.3025816837 Jan 14 02:28:46 PM PST 24 Jan 14 02:32:01 PM PST 24 816840445 ps
T774 /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.2815110372 Jan 14 02:15:07 PM PST 24 Jan 14 03:32:20 PM PST 24 1890106369 ps
T775 /workspace/coverage/default/25.sram_ctrl_stress_pipeline.247629545 Jan 14 02:24:14 PM PST 24 Jan 14 02:28:22 PM PST 24 3293916148 ps
T776 /workspace/coverage/default/9.sram_ctrl_multiple_keys.2922585234 Jan 14 02:16:40 PM PST 24 Jan 14 02:45:15 PM PST 24 92695540065 ps
T777 /workspace/coverage/default/3.sram_ctrl_regwen.875549399 Jan 14 02:13:42 PM PST 24 Jan 14 02:29:55 PM PST 24 24641972400 ps
T778 /workspace/coverage/default/36.sram_ctrl_regwen.3860539339 Jan 14 02:29:04 PM PST 24 Jan 14 02:43:07 PM PST 24 46951752061 ps
T779 /workspace/coverage/default/10.sram_ctrl_partial_access.2352341088 Jan 14 02:17:19 PM PST 24 Jan 14 02:17:34 PM PST 24 1701821561 ps
T780 /workspace/coverage/default/20.sram_ctrl_max_throughput.3176609709 Jan 14 02:22:01 PM PST 24 Jan 14 02:23:22 PM PST 24 3632210089 ps
T781 /workspace/coverage/default/10.sram_ctrl_stress_pipeline.1947832807 Jan 14 02:17:05 PM PST 24 Jan 14 02:21:33 PM PST 24 5189394730 ps
T782 /workspace/coverage/default/25.sram_ctrl_max_throughput.2718485157 Jan 14 02:24:25 PM PST 24 Jan 14 02:25:37 PM PST 24 868897736 ps
T783 /workspace/coverage/default/11.sram_ctrl_regwen.4140711199 Jan 14 02:17:57 PM PST 24 Jan 14 02:23:14 PM PST 24 2987948136 ps
T784 /workspace/coverage/default/37.sram_ctrl_access_during_key_req.3168409392 Jan 14 02:29:38 PM PST 24 Jan 14 02:31:52 PM PST 24 4003769767 ps
T785 /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.2809483824 Jan 14 02:33:13 PM PST 24 Jan 14 03:17:28 PM PST 24 3188170857 ps
T786 /workspace/coverage/default/27.sram_ctrl_stress_pipeline.2769328558 Jan 14 02:25:20 PM PST 24 Jan 14 02:32:21 PM PST 24 23469875681 ps
T787 /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.3206290302 Jan 14 02:17:56 PM PST 24 Jan 14 02:18:26 PM PST 24 706905221 ps
T788 /workspace/coverage/default/46.sram_ctrl_lc_escalation.3908513687 Jan 14 02:33:08 PM PST 24 Jan 14 02:34:00 PM PST 24 35332178939 ps
T789 /workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.389019616 Jan 14 02:20:52 PM PST 24 Jan 14 04:07:53 PM PST 24 4333725439 ps
T790 /workspace/coverage/default/3.sram_ctrl_bijection.2316392552 Jan 14 02:13:20 PM PST 24 Jan 14 02:46:00 PM PST 24 110638798366 ps
T791 /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.1933218958 Jan 14 02:13:40 PM PST 24 Jan 14 02:14:08 PM PST 24 3018793845 ps
T792 /workspace/coverage/default/0.sram_ctrl_mem_partial_access.1806981506 Jan 14 02:11:40 PM PST 24 Jan 14 02:13:06 PM PST 24 2449273512 ps
T793 /workspace/coverage/default/1.sram_ctrl_alert_test.4111011701 Jan 14 02:12:44 PM PST 24 Jan 14 02:12:46 PM PST 24 14875269 ps
T794 /workspace/coverage/default/5.sram_ctrl_alert_test.2558579483 Jan 14 02:15:10 PM PST 24 Jan 14 02:15:11 PM PST 24 14924492 ps
T795 /workspace/coverage/default/12.sram_ctrl_max_throughput.1979495488 Jan 14 02:18:15 PM PST 24 Jan 14 02:19:49 PM PST 24 773177125 ps
T796 /workspace/coverage/default/13.sram_ctrl_partial_access.1348069291 Jan 14 02:18:45 PM PST 24 Jan 14 02:18:53 PM PST 24 420288736 ps
T797 /workspace/coverage/default/45.sram_ctrl_lc_escalation.3243583384 Jan 14 02:32:40 PM PST 24 Jan 14 02:34:37 PM PST 24 13057349560 ps
T798 /workspace/coverage/default/40.sram_ctrl_smoke.3165973487 Jan 14 02:30:37 PM PST 24 Jan 14 02:30:55 PM PST 24 7933263575 ps
T799 /workspace/coverage/default/24.sram_ctrl_ram_cfg.3930527812 Jan 14 02:24:07 PM PST 24 Jan 14 02:24:21 PM PST 24 358812291 ps
T800 /workspace/coverage/default/34.sram_ctrl_smoke.224721157 Jan 14 02:28:07 PM PST 24 Jan 14 02:28:29 PM PST 24 1303342403 ps
T801 /workspace/coverage/default/46.sram_ctrl_ram_cfg.2262436337 Jan 14 02:33:13 PM PST 24 Jan 14 02:33:29 PM PST 24 800419770 ps
T802 /workspace/coverage/default/48.sram_ctrl_mem_partial_access.1100651521 Jan 14 02:33:56 PM PST 24 Jan 14 02:36:37 PM PST 24 19732703705 ps
T803 /workspace/coverage/default/26.sram_ctrl_ram_cfg.256024397 Jan 14 02:25:09 PM PST 24 Jan 14 02:25:17 PM PST 24 704651214 ps
T804 /workspace/coverage/default/12.sram_ctrl_stress_pipeline.1598591635 Jan 14 02:18:12 PM PST 24 Jan 14 02:23:01 PM PST 24 3825168190 ps
T805 /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.1854168370 Jan 14 02:18:16 PM PST 24 Jan 14 02:24:32 PM PST 24 6178531552 ps
T806 /workspace/coverage/default/42.sram_ctrl_lc_escalation.4257461343 Jan 14 02:31:39 PM PST 24 Jan 14 02:32:40 PM PST 24 19926521336 ps
T807 /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.882659660 Jan 14 02:14:37 PM PST 24 Jan 14 02:22:05 PM PST 24 77787766205 ps
T808 /workspace/coverage/default/28.sram_ctrl_mem_walk.1151231722 Jan 14 02:26:05 PM PST 24 Jan 14 02:28:45 PM PST 24 10464575572 ps
T809 /workspace/coverage/default/19.sram_ctrl_mem_partial_access.1140175534 Jan 14 02:21:47 PM PST 24 Jan 14 02:23:04 PM PST 24 4737687397 ps
T810 /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.1522681556 Jan 14 02:29:28 PM PST 24 Jan 14 02:30:35 PM PST 24 741786743 ps
T811 /workspace/coverage/default/36.sram_ctrl_max_throughput.2412184714 Jan 14 02:29:03 PM PST 24 Jan 14 02:30:48 PM PST 24 746528998 ps
T812 /workspace/coverage/default/42.sram_ctrl_alert_test.3850795021 Jan 14 02:31:50 PM PST 24 Jan 14 02:31:51 PM PST 24 17243658 ps
T813 /workspace/coverage/default/1.sram_ctrl_regwen.3608574759 Jan 14 02:12:12 PM PST 24 Jan 14 02:32:36 PM PST 24 80213538722 ps
T814 /workspace/coverage/default/44.sram_ctrl_stress_pipeline.3872184663 Jan 14 02:32:20 PM PST 24 Jan 14 02:39:06 PM PST 24 5174905024 ps
T815 /workspace/coverage/default/46.sram_ctrl_partial_access.949447637 Jan 14 02:32:51 PM PST 24 Jan 14 02:33:21 PM PST 24 1226164818 ps
T816 /workspace/coverage/default/23.sram_ctrl_stress_pipeline.4133351249 Jan 14 02:23:28 PM PST 24 Jan 14 02:31:40 PM PST 24 13015458655 ps
T817 /workspace/coverage/default/38.sram_ctrl_mem_partial_access.3926696996 Jan 14 02:30:13 PM PST 24 Jan 14 02:32:34 PM PST 24 3326501841 ps
T818 /workspace/coverage/default/37.sram_ctrl_regwen.994793462 Jan 14 02:29:43 PM PST 24 Jan 14 02:39:15 PM PST 24 10225174269 ps
T819 /workspace/coverage/default/22.sram_ctrl_mem_walk.3497388927 Jan 14 02:23:16 PM PST 24 Jan 14 02:25:52 PM PST 24 49681758714 ps
T820 /workspace/coverage/default/43.sram_ctrl_max_throughput.1516931839 Jan 14 02:31:57 PM PST 24 Jan 14 02:32:25 PM PST 24 1359573137 ps
T821 /workspace/coverage/default/43.sram_ctrl_regwen.480332640 Jan 14 02:31:59 PM PST 24 Jan 14 02:56:30 PM PST 24 78346505674 ps
T822 /workspace/coverage/default/44.sram_ctrl_lc_escalation.2093607178 Jan 14 02:32:29 PM PST 24 Jan 14 02:33:13 PM PST 24 3982043964 ps
T823 /workspace/coverage/default/0.sram_ctrl_access_during_key_req.215365192 Jan 14 02:11:34 PM PST 24 Jan 14 02:32:08 PM PST 24 20741450882 ps
T824 /workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.2130402420 Jan 14 02:31:25 PM PST 24 Jan 14 03:34:51 PM PST 24 270607490 ps
T825 /workspace/coverage/default/33.sram_ctrl_executable.3909102671 Jan 14 02:28:07 PM PST 24 Jan 14 02:42:16 PM PST 24 113351476236 ps
T826 /workspace/coverage/default/17.sram_ctrl_multiple_keys.1773615659 Jan 14 02:20:31 PM PST 24 Jan 14 02:32:02 PM PST 24 33717997534 ps
T827 /workspace/coverage/default/20.sram_ctrl_partial_access.4067502089 Jan 14 02:22:02 PM PST 24 Jan 14 02:22:30 PM PST 24 2862318026 ps
T828 /workspace/coverage/default/47.sram_ctrl_stress_all.1506576150 Jan 14 02:33:35 PM PST 24 Jan 14 03:36:20 PM PST 24 132680689918 ps
T829 /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.286265281 Jan 14 02:26:17 PM PST 24 Jan 14 02:33:04 PM PST 24 16120009185 ps
T830 /workspace/coverage/default/10.sram_ctrl_multiple_keys.3258811296 Jan 14 02:17:04 PM PST 24 Jan 14 02:18:03 PM PST 24 1166626665 ps
T831 /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.3832285626 Jan 14 02:32:29 PM PST 24 Jan 14 02:38:43 PM PST 24 15501127417 ps
T832 /workspace/coverage/default/6.sram_ctrl_bijection.2885835527 Jan 14 02:15:14 PM PST 24 Jan 14 02:30:34 PM PST 24 48534623450 ps
T833 /workspace/coverage/default/29.sram_ctrl_executable.743200422 Jan 14 02:26:17 PM PST 24 Jan 14 02:47:56 PM PST 24 17083953376 ps
T834 /workspace/coverage/default/37.sram_ctrl_lc_escalation.1472058959 Jan 14 02:29:38 PM PST 24 Jan 14 02:32:24 PM PST 24 5566180884 ps
T835 /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.1741142247 Jan 14 02:25:20 PM PST 24 Jan 14 02:30:45 PM PST 24 70201454693 ps
T836 /workspace/coverage/default/16.sram_ctrl_partial_access.3810343961 Jan 14 02:20:15 PM PST 24 Jan 14 02:20:44 PM PST 24 5674928516 ps
T837 /workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.1900518298 Jan 14 02:14:21 PM PST 24 Jan 14 03:20:23 PM PST 24 964916789 ps
T838 /workspace/coverage/default/28.sram_ctrl_smoke.2733560783 Jan 14 02:25:24 PM PST 24 Jan 14 02:25:44 PM PST 24 4318463297 ps
T839 /workspace/coverage/default/11.sram_ctrl_access_during_key_req.2558813762 Jan 14 02:17:58 PM PST 24 Jan 14 02:28:00 PM PST 24 8222398952 ps
T840 /workspace/coverage/default/31.sram_ctrl_multiple_keys.1575305449 Jan 14 02:26:56 PM PST 24 Jan 14 02:48:24 PM PST 24 131373769881 ps
T841 /workspace/coverage/default/18.sram_ctrl_alert_test.3387900728 Jan 14 02:21:25 PM PST 24 Jan 14 02:21:27 PM PST 24 20530231 ps
T842 /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.4219178917 Jan 14 02:33:26 PM PST 24 Jan 14 02:41:09 PM PST 24 37437884470 ps
T843 /workspace/coverage/default/20.sram_ctrl_regwen.2942399374 Jan 14 02:22:08 PM PST 24 Jan 14 02:43:25 PM PST 24 10950305909 ps
T844 /workspace/coverage/default/14.sram_ctrl_lc_escalation.2338014772 Jan 14 02:19:17 PM PST 24 Jan 14 02:22:16 PM PST 24 7377710232 ps
T845 /workspace/coverage/default/34.sram_ctrl_stress_pipeline.911813273 Jan 14 02:28:12 PM PST 24 Jan 14 02:32:02 PM PST 24 6809586560 ps
T846 /workspace/coverage/default/31.sram_ctrl_lc_escalation.1811616398 Jan 14 02:27:23 PM PST 24 Jan 14 02:28:10 PM PST 24 13675627325 ps
T847 /workspace/coverage/default/49.sram_ctrl_alert_test.341917970 Jan 14 02:34:14 PM PST 24 Jan 14 02:34:17 PM PST 24 30898962 ps
T848 /workspace/coverage/default/44.sram_ctrl_mem_walk.1345584792 Jan 14 02:32:28 PM PST 24 Jan 14 02:37:31 PM PST 24 14330938890 ps
T849 /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.3109034137 Jan 14 02:25:34 PM PST 24 Jan 14 02:33:57 PM PST 24 19973523462 ps
T850 /workspace/coverage/default/34.sram_ctrl_ram_cfg.3904204403 Jan 14 02:28:29 PM PST 24 Jan 14 02:28:36 PM PST 24 1365627353 ps
T851 /workspace/coverage/default/23.sram_ctrl_lc_escalation.62135808 Jan 14 02:24:23 PM PST 24 Jan 14 02:26:36 PM PST 24 53209288578 ps
T852 /workspace/coverage/default/16.sram_ctrl_max_throughput.1363460792 Jan 14 02:20:10 PM PST 24 Jan 14 02:20:38 PM PST 24 2794254293 ps
T853 /workspace/coverage/default/40.sram_ctrl_multiple_keys.1351625674 Jan 14 02:30:38 PM PST 24 Jan 14 02:50:41 PM PST 24 82441909493 ps
T854 /workspace/coverage/default/47.sram_ctrl_alert_test.1434910022 Jan 14 02:33:34 PM PST 24 Jan 14 02:33:36 PM PST 24 107781118 ps
T855 /workspace/coverage/default/14.sram_ctrl_alert_test.2795021690 Jan 14 02:19:33 PM PST 24 Jan 14 02:19:37 PM PST 24 19218227 ps
T856 /workspace/coverage/default/22.sram_ctrl_bijection.3784625788 Jan 14 02:23:01 PM PST 24 Jan 14 02:31:08 PM PST 24 14661939737 ps
T857 /workspace/coverage/default/31.sram_ctrl_access_during_key_req.1973116837 Jan 14 02:27:20 PM PST 24 Jan 14 02:44:00 PM PST 24 18430387366 ps
T858 /workspace/coverage/default/36.sram_ctrl_executable.3266468869 Jan 14 02:29:07 PM PST 24 Jan 14 02:43:05 PM PST 24 14236266051 ps
T859 /workspace/coverage/default/40.sram_ctrl_bijection.3401884626 Jan 14 02:30:37 PM PST 24 Jan 14 02:51:50 PM PST 24 395495394644 ps
T860 /workspace/coverage/default/28.sram_ctrl_bijection.505963661 Jan 14 02:25:35 PM PST 24 Jan 14 02:50:29 PM PST 24 105263688344 ps
T861 /workspace/coverage/default/37.sram_ctrl_stress_pipeline.1821693578 Jan 14 02:29:20 PM PST 24 Jan 14 02:34:57 PM PST 24 4586530499 ps
T862 /workspace/coverage/default/32.sram_ctrl_stress_pipeline.343535169 Jan 14 02:27:37 PM PST 24 Jan 14 02:33:24 PM PST 24 10400793479 ps
T863 /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.1332942341 Jan 14 02:17:21 PM PST 24 Jan 14 02:20:49 PM PST 24 3117572227 ps
T864 /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.3182468455 Jan 14 02:29:03 PM PST 24 Jan 14 02:39:36 PM PST 24 262820560919 ps
T865 /workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.305350354 Jan 14 02:21:29 PM PST 24 Jan 14 03:27:31 PM PST 24 5232028104 ps
T866 /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.3005611929 Jan 14 02:12:45 PM PST 24 Jan 14 03:36:29 PM PST 24 710582424 ps
T867 /workspace/coverage/default/35.sram_ctrl_mem_walk.757355967 Jan 14 02:28:53 PM PST 24 Jan 14 02:31:39 PM PST 24 41337489798 ps
T868 /workspace/coverage/default/45.sram_ctrl_partial_access.1011827677 Jan 14 02:32:38 PM PST 24 Jan 14 02:32:47 PM PST 24 1363449196 ps
T869 /workspace/coverage/default/37.sram_ctrl_max_throughput.1571855869 Jan 14 02:29:29 PM PST 24 Jan 14 02:31:59 PM PST 24 1513422859 ps
T870 /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.2905603411 Jan 14 02:19:33 PM PST 24 Jan 14 03:13:56 PM PST 24 819712863 ps
T871 /workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.3002535808 Jan 14 02:30:31 PM PST 24 Jan 14 04:38:40 PM PST 24 6551079415 ps
T872 /workspace/coverage/default/35.sram_ctrl_partial_access.4242894410 Jan 14 02:28:58 PM PST 24 Jan 14 02:29:27 PM PST 24 5330182902 ps
T873 /workspace/coverage/default/29.sram_ctrl_partial_access.1822032243 Jan 14 02:26:17 PM PST 24 Jan 14 02:26:49 PM PST 24 2550500542 ps
T874 /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.1265892320 Jan 14 02:31:58 PM PST 24 Jan 14 02:39:57 PM PST 24 386754520985 ps
T875 /workspace/coverage/default/25.sram_ctrl_stress_all.2170176292 Jan 14 02:24:35 PM PST 24 Jan 14 03:21:36 PM PST 24 46397629882 ps
T876 /workspace/coverage/default/9.sram_ctrl_mem_partial_access.2400337442 Jan 14 02:17:04 PM PST 24 Jan 14 02:19:49 PM PST 24 9141048213 ps
T877 /workspace/coverage/default/44.sram_ctrl_smoke.215462286 Jan 14 02:32:17 PM PST 24 Jan 14 02:32:42 PM PST 24 8875120671 ps
T878 /workspace/coverage/default/32.sram_ctrl_mem_walk.3985181226 Jan 14 02:27:50 PM PST 24 Jan 14 02:32:44 PM PST 24 57301593713 ps
T879 /workspace/coverage/default/46.sram_ctrl_max_throughput.3482668060 Jan 14 02:32:50 PM PST 24 Jan 14 02:35:15 PM PST 24 1564098583 ps
T880 /workspace/coverage/default/16.sram_ctrl_mem_partial_access.3161440831 Jan 14 02:20:27 PM PST 24 Jan 14 02:22:51 PM PST 24 31220845827 ps
T881 /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.653491603 Jan 14 02:18:45 PM PST 24 Jan 14 02:19:22 PM PST 24 1385995746 ps
T882 /workspace/coverage/default/32.sram_ctrl_partial_access.2880896561 Jan 14 02:27:37 PM PST 24 Jan 14 02:28:01 PM PST 24 20399325256 ps
T883 /workspace/coverage/default/4.sram_ctrl_regwen.438158277 Jan 14 02:14:13 PM PST 24 Jan 14 02:40:46 PM PST 24 8709423798 ps
T884 /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1805905072 Jan 14 02:33:36 PM PST 24 Jan 14 03:18:50 PM PST 24 290951225 ps
T885 /workspace/coverage/default/31.sram_ctrl_stress_pipeline.3292208617 Jan 14 02:27:01 PM PST 24 Jan 14 02:33:02 PM PST 24 4441449317 ps
T886 /workspace/coverage/default/29.sram_ctrl_access_during_key_req.2003617875 Jan 14 02:26:16 PM PST 24 Jan 14 02:29:34 PM PST 24 8733726754 ps
T887 /workspace/coverage/default/31.sram_ctrl_bijection.1904847167 Jan 14 02:26:56 PM PST 24 Jan 14 02:55:13 PM PST 24 76819166138 ps
T888 /workspace/coverage/default/34.sram_ctrl_access_during_key_req.822630480 Jan 14 02:28:19 PM PST 24 Jan 14 02:41:17 PM PST 24 5598195763 ps
T889 /workspace/coverage/default/12.sram_ctrl_access_during_key_req.3813124497 Jan 14 02:18:23 PM PST 24 Jan 14 02:30:22 PM PST 24 4315825465 ps
T890 /workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.2506510867 Jan 14 02:13:40 PM PST 24 Jan 14 05:06:55 PM PST 24 6096507516 ps
T891 /workspace/coverage/default/35.sram_ctrl_multiple_keys.2451835190 Jan 14 02:28:35 PM PST 24 Jan 14 02:29:34 PM PST 24 3286075589 ps
T892 /workspace/coverage/default/20.sram_ctrl_ram_cfg.1277332160 Jan 14 02:22:08 PM PST 24 Jan 14 02:22:16 PM PST 24 342846291 ps
T893 /workspace/coverage/default/29.sram_ctrl_stress_all.773474519 Jan 14 02:26:32 PM PST 24 Jan 14 04:26:16 PM PST 24 290205361333 ps
T894 /workspace/coverage/default/18.sram_ctrl_stress_all.1953320923 Jan 14 02:21:36 PM PST 24 Jan 14 03:37:49 PM PST 24 264483543124 ps
T895 /workspace/coverage/default/48.sram_ctrl_multiple_keys.2121929640 Jan 14 02:33:36 PM PST 24 Jan 14 02:52:59 PM PST 24 17341770061 ps
T896 /workspace/coverage/default/20.sram_ctrl_multiple_keys.521377336 Jan 14 02:21:54 PM PST 24 Jan 14 02:26:32 PM PST 24 3005627126 ps
T897 /workspace/coverage/default/32.sram_ctrl_alert_test.4157892251 Jan 14 02:27:51 PM PST 24 Jan 14 02:27:53 PM PST 24 15413429 ps
T898 /workspace/coverage/default/25.sram_ctrl_mem_walk.4200148173 Jan 14 02:24:38 PM PST 24 Jan 14 02:27:18 PM PST 24 27550169068 ps
T899 /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.918959458 Jan 14 02:31:15 PM PST 24 Jan 14 02:33:59 PM PST 24 4605346318 ps
T900 /workspace/coverage/default/44.sram_ctrl_partial_access.2827403398 Jan 14 02:32:17 PM PST 24 Jan 14 02:32:52 PM PST 24 6520274734 ps
T901 /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.734790372 Jan 14 02:33:26 PM PST 24 Jan 14 02:34:59 PM PST 24 2214426386 ps
T902 /workspace/coverage/default/26.sram_ctrl_lc_escalation.3013274912 Jan 14 02:24:56 PM PST 24 Jan 14 02:29:05 PM PST 24 37196215769 ps
T903 /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.2897024622 Jan 14 02:20:09 PM PST 24 Jan 14 03:31:27 PM PST 24 9961358419 ps
T904 /workspace/coverage/default/32.sram_ctrl_smoke.3350705973 Jan 14 02:27:29 PM PST 24 Jan 14 02:27:57 PM PST 24 1620799484 ps
T905 /workspace/coverage/default/36.sram_ctrl_lc_escalation.61588309 Jan 14 02:29:04 PM PST 24 Jan 14 02:31:39 PM PST 24 13798969769 ps
T906 /workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.597114226 Jan 14 02:13:04 PM PST 24 Jan 14 03:23:23 PM PST 24 2621624580 ps
T907 /workspace/coverage/default/2.sram_ctrl_multiple_keys.3787130543 Jan 14 02:12:46 PM PST 24 Jan 14 02:36:02 PM PST 24 15091855772 ps
T908 /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.1727456277 Jan 14 02:16:39 PM PST 24 Jan 14 02:17:17 PM PST 24 979506494 ps
T909 /workspace/coverage/default/48.sram_ctrl_mem_walk.2548851329 Jan 14 02:33:47 PM PST 24 Jan 14 02:39:26 PM PST 24 86019441094 ps
T910 /workspace/coverage/default/13.sram_ctrl_mem_walk.725031038 Jan 14 02:18:48 PM PST 24 Jan 14 02:21:30 PM PST 24 10683869021 ps
T911 /workspace/coverage/default/35.sram_ctrl_alert_test.487416593 Jan 14 02:28:52 PM PST 24 Jan 14 02:28:53 PM PST 24 21604173 ps
T912 /workspace/coverage/default/30.sram_ctrl_alert_test.498998482 Jan 14 02:26:52 PM PST 24 Jan 14 02:26:59 PM PST 24 154007625 ps
T913 /workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.1733369039 Jan 14 02:29:52 PM PST 24 Jan 14 03:21:59 PM PST 24 1065742865 ps
T914 /workspace/coverage/default/15.sram_ctrl_regwen.2413954067 Jan 14 02:19:54 PM PST 24 Jan 14 02:39:14 PM PST 24 4094779051 ps
T915 /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.3414750267 Jan 14 02:32:51 PM PST 24 Jan 14 02:39:32 PM PST 24 21867800495 ps
T916 /workspace/coverage/default/29.sram_ctrl_mem_walk.521961101 Jan 14 02:26:31 PM PST 24 Jan 14 02:29:14 PM PST 24 10337071198 ps
T917 /workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.2900752156 Jan 14 02:24:03 PM PST 24 Jan 14 02:26:03 PM PST 24 1591715785 ps
T918 /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.2006952426 Jan 14 02:24:58 PM PST 24 Jan 14 02:25:32 PM PST 24 703575879 ps
T919 /workspace/coverage/default/31.sram_ctrl_mem_walk.1504363105 Jan 14 02:27:22 PM PST 24 Jan 14 02:29:32 PM PST 24 2251776687 ps
T920 /workspace/coverage/default/38.sram_ctrl_partial_access.3718506527 Jan 14 02:30:03 PM PST 24 Jan 14 02:30:42 PM PST 24 3287653983 ps
T921 /workspace/coverage/default/10.sram_ctrl_smoke.2308588634 Jan 14 02:17:05 PM PST 24 Jan 14 02:17:36 PM PST 24 2144534127 ps
T922 /workspace/coverage/default/7.sram_ctrl_smoke.3034024976 Jan 14 02:15:52 PM PST 24 Jan 14 02:16:58 PM PST 24 445921864 ps
T923 /workspace/coverage/default/39.sram_ctrl_lc_escalation.3353489282 Jan 14 02:30:29 PM PST 24 Jan 14 02:32:16 PM PST 24 37557352819 ps
T924 /workspace/coverage/default/30.sram_ctrl_smoke.3912494292 Jan 14 02:26:37 PM PST 24 Jan 14 02:26:49 PM PST 24 2085489339 ps
T925 /workspace/coverage/default/11.sram_ctrl_stress_pipeline.433052927 Jan 14 02:17:40 PM PST 24 Jan 14 02:22:51 PM PST 24 4188040835 ps
T926 /workspace/coverage/default/22.sram_ctrl_smoke.3204948312 Jan 14 02:22:55 PM PST 24 Jan 14 02:23:33 PM PST 24 1400533489 ps
T927 /workspace/coverage/default/33.sram_ctrl_access_during_key_req.953993333 Jan 14 02:28:01 PM PST 24 Jan 14 02:48:50 PM PST 24 55445849502 ps
T928 /workspace/coverage/default/6.sram_ctrl_max_throughput.165505246 Jan 14 02:15:20 PM PST 24 Jan 14 02:15:55 PM PST 24 2739755268 ps
T929 /workspace/coverage/default/28.sram_ctrl_ram_cfg.18977927 Jan 14 02:26:03 PM PST 24 Jan 14 02:26:09 PM PST 24 362641827 ps
T930 /workspace/coverage/default/27.sram_ctrl_regwen.1809583004 Jan 14 02:25:25 PM PST 24 Jan 14 02:48:10 PM PST 24 37633843904 ps
T931 /workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.3312907481 Jan 14 02:25:25 PM PST 24 Jan 14 03:46:16 PM PST 24 1220734820 ps
T932 /workspace/coverage/default/37.sram_ctrl_partial_access.3361897191 Jan 14 02:29:27 PM PST 24 Jan 14 02:29:47 PM PST 24 434899131 ps
T933 /workspace/coverage/default/40.sram_ctrl_max_throughput.124278281 Jan 14 02:30:45 PM PST 24 Jan 14 02:31:31 PM PST 24 2927815509 ps
T934 /workspace/coverage/default/37.sram_ctrl_mem_partial_access.406999823 Jan 14 02:29:47 PM PST 24 Jan 14 02:32:20 PM PST 24 4967659150 ps
T935 /workspace/coverage/default/5.sram_ctrl_multiple_keys.3968506516 Jan 14 02:14:29 PM PST 24 Jan 14 02:31:46 PM PST 24 36461914519 ps
T936 /workspace/coverage/default/39.sram_ctrl_smoke.667714018 Jan 14 02:30:18 PM PST 24 Jan 14 02:31:02 PM PST 24 1312414868 ps
T937 /workspace/coverage/default/45.sram_ctrl_smoke.14346937 Jan 14 02:32:37 PM PST 24 Jan 14 02:33:07 PM PST 24 1068471677 ps
T938 /workspace/coverage/default/29.sram_ctrl_multiple_keys.3953050410 Jan 14 02:26:09 PM PST 24 Jan 14 02:41:53 PM PST 24 132141392611 ps
T939 /workspace/coverage/default/41.sram_ctrl_stress_all.2740249739 Jan 14 02:31:24 PM PST 24 Jan 14 02:45:16 PM PST 24 51282901687 ps
T940 /workspace/coverage/default/20.sram_ctrl_mem_walk.1366207092 Jan 14 02:22:23 PM PST 24 Jan 14 02:25:01 PM PST 24 7271580988 ps
T941 /workspace/coverage/default/35.sram_ctrl_lc_escalation.793677204 Jan 14 02:28:52 PM PST 24 Jan 14 02:29:29 PM PST 24 3517761627 ps
T942 /workspace/coverage/default/29.sram_ctrl_bijection.689172067 Jan 14 02:26:09 PM PST 24 Jan 14 03:01:08 PM PST 24 175062570360 ps
T943 /workspace/coverage/default/38.sram_ctrl_lc_escalation.1942141734 Jan 14 02:30:03 PM PST 24 Jan 14 02:31:53 PM PST 24 30361629268 ps
T944 /workspace/coverage/default/42.sram_ctrl_bijection.2860864931 Jan 14 02:31:25 PM PST 24 Jan 14 02:53:35 PM PST 24 251713216615 ps
T945 /workspace/coverage/default/2.sram_ctrl_stress_pipeline.1119662788 Jan 14 02:12:48 PM PST 24 Jan 14 02:16:49 PM PST 24 14371370842 ps
T946 /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.387487224 Jan 14 02:17:43 PM PST 24 Jan 14 02:24:57 PM PST 24 9942603580 ps
T947 /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.1244321409 Jan 14 02:21:41 PM PST 24 Jan 14 02:24:33 PM PST 24 3250486255 ps
T948 /workspace/coverage/default/27.sram_ctrl_alert_test.14092194 Jan 14 02:25:25 PM PST 24 Jan 14 02:25:28 PM PST 24 43791628 ps
T949 /workspace/coverage/default/9.sram_ctrl_regwen.2070665340 Jan 14 02:17:06 PM PST 24 Jan 14 02:37:18 PM PST 24 22399257028 ps
T950 /workspace/coverage/default/13.sram_ctrl_ram_cfg.3786741947 Jan 14 02:18:53 PM PST 24 Jan 14 02:19:08 PM PST 24 1342443840 ps
T951 /workspace/coverage/default/19.sram_ctrl_lc_escalation.1031767953 Jan 14 02:21:46 PM PST 24 Jan 14 02:23:17 PM PST 24 38903691270 ps
T952 /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.1682757158 Jan 14 02:30:21 PM PST 24 Jan 14 02:36:46 PM PST 24 14709516495 ps
T953 /workspace/coverage/default/48.sram_ctrl_smoke.1064280331 Jan 14 02:33:33 PM PST 24 Jan 14 02:33:59 PM PST 24 1989751140 ps
T954 /workspace/coverage/default/9.sram_ctrl_alert_test.4014828123 Jan 14 02:17:04 PM PST 24 Jan 14 02:17:06 PM PST 24 49771960 ps
T955 /workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.2080627898 Jan 14 02:24:14 PM PST 24 Jan 14 03:33:34 PM PST 24 8492222372 ps
T956 /workspace/coverage/default/31.sram_ctrl_max_throughput.2969913181 Jan 14 02:27:10 PM PST 24 Jan 14 02:28:31 PM PST 24 2830699867 ps
T957 /workspace/coverage/default/42.sram_ctrl_partial_access.644133126 Jan 14 02:31:34 PM PST 24 Jan 14 02:33:25 PM PST 24 3716815831 ps
T958 /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.838369707 Jan 14 02:23:51 PM PST 24 Jan 14 02:24:22 PM PST 24 2741012734 ps
T959 /workspace/coverage/default/5.sram_ctrl_stress_pipeline.90645354 Jan 14 02:14:37 PM PST 24 Jan 14 02:17:42 PM PST 24 2119109027 ps
T960 /workspace/coverage/default/47.sram_ctrl_lc_escalation.2299945552 Jan 14 02:33:29 PM PST 24 Jan 14 02:34:01 PM PST 24 4461196694 ps
T961 /workspace/coverage/default/8.sram_ctrl_mem_walk.2389925069 Jan 14 02:16:38 PM PST 24 Jan 14 02:19:47 PM PST 24 127770268747 ps
T962 /workspace/coverage/default/5.sram_ctrl_regwen.3084280093 Jan 14 02:14:56 PM PST 24 Jan 14 02:32:53 PM PST 24 3192879959 ps
T963 /workspace/coverage/default/9.sram_ctrl_mem_walk.1863568939 Jan 14 02:17:06 PM PST 24 Jan 14 02:19:19 PM PST 24 1979168464 ps
T964 /workspace/coverage/default/25.sram_ctrl_mem_partial_access.2282061482 Jan 14 02:24:34 PM PST 24 Jan 14 02:25:53 PM PST 24 1962463255 ps
T965 /workspace/coverage/default/33.sram_ctrl_mem_walk.2757491101 Jan 14 02:28:08 PM PST 24 Jan 14 02:33:27 PM PST 24 21753748365 ps
T966 /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.450866629 Jan 14 02:24:23 PM PST 24 Jan 14 02:26:33 PM PST 24 803343400 ps
T967 /workspace/coverage/default/22.sram_ctrl_mem_partial_access.3330282468 Jan 14 02:23:18 PM PST 24 Jan 14 02:24:37 PM PST 24 2345200383 ps
T968 /workspace/coverage/default/31.sram_ctrl_partial_access.4164810081 Jan 14 02:27:01 PM PST 24 Jan 14 02:27:24 PM PST 24 3881803765 ps
T969 /workspace/coverage/default/32.sram_ctrl_regwen.245274852 Jan 14 02:27:42 PM PST 24 Jan 14 02:37:56 PM PST 24 7539373490 ps
T970 /workspace/coverage/default/42.sram_ctrl_ram_cfg.442374752 Jan 14 02:31:40 PM PST 24 Jan 14 02:31:53 PM PST 24 368304899 ps
T971 /workspace/coverage/default/49.sram_ctrl_multiple_keys.733896062 Jan 14 02:33:56 PM PST 24 Jan 14 02:49:14 PM PST 24 10050826742 ps
T972 /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.2300561544 Jan 14 02:32:45 PM PST 24 Jan 14 03:40:28 PM PST 24 5621549189 ps
T973 /workspace/coverage/default/7.sram_ctrl_lc_escalation.1710339370 Jan 14 02:16:01 PM PST 24 Jan 14 02:17:53 PM PST 24 31880799784 ps
T974 /workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.3027986378 Jan 14 02:20:26 PM PST 24 Jan 14 02:56:52 PM PST 24 952421841 ps
T975 /workspace/coverage/default/7.sram_ctrl_partial_access.2062625568 Jan 14 02:15:57 PM PST 24 Jan 14 02:16:30 PM PST 24 2495244333 ps
T976 /workspace/coverage/default/16.sram_ctrl_mem_walk.3736200332 Jan 14 02:20:23 PM PST 24 Jan 14 02:25:41 PM PST 24 57411449149 ps
T977 /workspace/coverage/default/40.sram_ctrl_stress_pipeline.2247188924 Jan 14 02:30:45 PM PST 24 Jan 14 02:36:08 PM PST 24 15722585930 ps
T978 /workspace/coverage/default/41.sram_ctrl_stress_pipeline.3209740413 Jan 14 02:31:06 PM PST 24 Jan 14 02:36:53 PM PST 24 20754593562 ps
T979 /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.1031207684 Jan 14 02:24:45 PM PST 24 Jan 14 02:31:12 PM PST 24 57224299627 ps
T980 /workspace/coverage/default/40.sram_ctrl_stress_all.2674071741 Jan 14 02:31:05 PM PST 24 Jan 14 03:36:09 PM PST 24 627678749151 ps
T981 /workspace/coverage/default/25.sram_ctrl_lc_escalation.768535828 Jan 14 02:24:28 PM PST 24 Jan 14 02:25:25 PM PST 24 5949805311 ps
T982 /workspace/coverage/default/35.sram_ctrl_access_during_key_req.2750807602 Jan 14 02:28:52 PM PST 24 Jan 14 02:43:49 PM PST 24 17083802100 ps
T983 /workspace/coverage/default/0.sram_ctrl_stress_pipeline.2029177254 Jan 14 02:11:26 PM PST 24 Jan 14 02:19:25 PM PST 24 5187661313 ps
T984 /workspace/coverage/default/26.sram_ctrl_stress_pipeline.3808172506 Jan 14 02:24:48 PM PST 24 Jan 14 02:27:22 PM PST 24 1804535699 ps
T985 /workspace/coverage/default/23.sram_ctrl_bijection.3656878604 Jan 14 02:23:29 PM PST 24 Jan 14 03:03:26 PM PST 24 878980635005 ps
T986 /workspace/coverage/default/2.sram_ctrl_smoke.4079595048 Jan 14 02:12:44 PM PST 24 Jan 14 02:13:38 PM PST 24 2953827323 ps
T987 /workspace/coverage/default/33.sram_ctrl_stress_all.115575906 Jan 14 02:28:07 PM PST 24 Jan 14 03:43:56 PM PST 24 278317334559 ps
T988 /workspace/coverage/default/22.sram_ctrl_partial_access.183280151 Jan 14 02:23:00 PM PST 24 Jan 14 02:23:59 PM PST 24 4212852962 ps
T989 /workspace/coverage/default/30.sram_ctrl_regwen.2040256071 Jan 14 02:26:48 PM PST 24 Jan 14 02:39:28 PM PST 24 8292283335 ps
T990 /workspace/coverage/default/15.sram_ctrl_multiple_keys.80227780 Jan 14 02:19:33 PM PST 24 Jan 14 02:30:51 PM PST 24 4136518437 ps

Test location /workspace/coverage/default/5.sram_ctrl_lc_escalation.3053582893
Short name T3
Test name
Test status
Simulation time 2648856082 ps
CPU time 69.65 seconds
Started Jan 14 02:15:02 PM PST 24
Finished Jan 14 02:16:12 PM PST 24
Peak memory 213532 kb
Host smart-55474653-f385-4b2f-bbe2-5f7bcee71d46
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053582893 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_lc_esc
alation.3053582893
Directory /workspace/5.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/19.sram_ctrl_regwen.2643670549
Short name T18
Test name
Test status
Simulation time 83021219453 ps
CPU time 1191.54 seconds
Started Jan 14 02:21:48 PM PST 24
Finished Jan 14 02:41:47 PM PST 24
Peak memory 377108 kb
Host smart-603c931d-af5f-4124-b537-8ed5090c710e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643670549 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.2643670549
Directory /workspace/19.sram_ctrl_regwen/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2057935949
Short name T31
Test name
Test status
Simulation time 170752961 ps
CPU time 2.1 seconds
Started Jan 14 01:15:00 PM PST 24
Finished Jan 14 01:15:08 PM PST 24
Peak memory 202304 kb
Host smart-ea7aade7-e817-4e98-b99c-8b186dd8a383
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057935949 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 3.sram_ctrl_tl_intg_err.2057935949
Directory /workspace/3.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/17.sram_ctrl_lc_escalation.2139390545
Short name T6
Test name
Test status
Simulation time 10062814656 ps
CPU time 131.37 seconds
Started Jan 14 02:20:36 PM PST 24
Finished Jan 14 02:22:48 PM PST 24
Peak memory 214176 kb
Host smart-9bb30cb7-2309-43ac-9043-ba93c7ae2e15
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139390545 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_es
calation.2139390545
Directory /workspace/17.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.588479094
Short name T56
Test name
Test status
Simulation time 314056728 ps
CPU time 3.05 seconds
Started Jan 14 01:14:59 PM PST 24
Finished Jan 14 01:15:09 PM PST 24
Peak memory 202384 kb
Host smart-d899e675-0461-49ed-8ff6-18d67297cc17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588479094 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.sram_ctrl_tl_errors.588479094
Directory /workspace/2.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/default/1.sram_ctrl_sec_cm.3415723275
Short name T23
Test name
Test status
Simulation time 219853044 ps
CPU time 2.17 seconds
Started Jan 14 02:12:33 PM PST 24
Finished Jan 14 02:12:37 PM PST 24
Peak memory 221000 kb
Host smart-be8b935c-6a2e-4798-b64c-ac5717069578
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415723275 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.sram_ctrl_sec_cm.3415723275
Directory /workspace/1.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/35.sram_ctrl_partial_access_b2b.3390333458
Short name T102
Test name
Test status
Simulation time 7788686649 ps
CPU time 184.46 seconds
Started Jan 14 02:28:51 PM PST 24
Finished Jan 14 02:31:56 PM PST 24
Peak memory 202156 kb
Host smart-0336b299-666f-4fc9-8a59-ca45380b1356
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390333458 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 35.sram_ctrl_partial_access_b2b.3390333458
Directory /workspace/35.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/15.sram_ctrl_stress_all.1409710780
Short name T124
Test name
Test status
Simulation time 567994318609 ps
CPU time 6958.67 seconds
Started Jan 14 02:20:11 PM PST 24
Finished Jan 14 04:16:12 PM PST 24
Peak memory 382156 kb
Host smart-5167b893-2ea4-45b7-8b6f-d0b771e94af0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409710780 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 15.sram_ctrl_stress_all.1409710780
Directory /workspace/15.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.sram_ctrl_access_during_key_req.2011862354
Short name T19
Test name
Test status
Simulation time 5498997844 ps
CPU time 662.98 seconds
Started Jan 14 02:30:47 PM PST 24
Finished Jan 14 02:41:51 PM PST 24
Peak memory 378788 kb
Host smart-d44c0a6a-371e-4024-afd6-d96836fffd4e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011862354 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 40.sram_ctrl_access_during_key_req.2011862354
Directory /workspace/40.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.2329108567
Short name T106
Test name
Test status
Simulation time 4830144792 ps
CPU time 6665.48 seconds
Started Jan 14 02:26:32 PM PST 24
Finished Jan 14 04:17:39 PM PST 24
Peak memory 712956 kb
Host smart-5dda4885-c0bf-40ff-b236-6d732bf10a12
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2329108567 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all_with_rand_reset.2329108567
Directory /workspace/29.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3974055032
Short name T51
Test name
Test status
Simulation time 15088892754 ps
CPU time 271.68 seconds
Started Jan 14 01:14:54 PM PST 24
Finished Jan 14 01:19:27 PM PST 24
Peak memory 202552 kb
Host smart-e23fbf78-ada7-4b22-ba67-39b1d37e508a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974055032 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 13.sram_ctrl_passthru_mem_tl_intg_err.3974055032
Directory /workspace/13.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/35.sram_ctrl_ram_cfg.1561155154
Short name T30
Test name
Test status
Simulation time 363937350 ps
CPU time 6.64 seconds
Started Jan 14 02:28:53 PM PST 24
Finished Jan 14 02:29:01 PM PST 24
Peak memory 202444 kb
Host smart-15389634-9c14-4dfd-aaac-34f991552afe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561155154 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.1561155154
Directory /workspace/35.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2081940833
Short name T112
Test name
Test status
Simulation time 335611080 ps
CPU time 2.44 seconds
Started Jan 14 01:15:01 PM PST 24
Finished Jan 14 01:15:09 PM PST 24
Peak memory 202396 kb
Host smart-f359e1bf-11c8-4a28-8484-6cbbc45c14cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081940833 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 19.sram_ctrl_tl_intg_err.2081940833
Directory /workspace/19.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3171220905
Short name T115
Test name
Test status
Simulation time 525278828 ps
CPU time 2.42 seconds
Started Jan 14 01:15:05 PM PST 24
Finished Jan 14 01:15:13 PM PST 24
Peak memory 202396 kb
Host smart-1efcaf8d-cc34-4f5f-8ca5-7215f05a48bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171220905 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 15.sram_ctrl_tl_intg_err.3171220905
Directory /workspace/15.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/23.sram_ctrl_regwen.3529540633
Short name T16
Test name
Test status
Simulation time 20570274289 ps
CPU time 647.22 seconds
Started Jan 14 02:23:42 PM PST 24
Finished Jan 14 02:34:29 PM PST 24
Peak memory 372960 kb
Host smart-a029724d-e464-4add-88fb-de9dbf853148
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529540633 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.3529540633
Directory /workspace/23.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/17.sram_ctrl_alert_test.3761591346
Short name T22
Test name
Test status
Simulation time 111642240 ps
CPU time 0.63 seconds
Started Jan 14 02:20:52 PM PST 24
Finished Jan 14 02:20:53 PM PST 24
Peak memory 201460 kb
Host smart-63e11d73-39b6-483d-a1c3-3faad432253d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761591346 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.sram_ctrl_alert_test.3761591346
Directory /workspace/17.sram_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3916130363
Short name T158
Test name
Test status
Simulation time 667316874 ps
CPU time 5.77 seconds
Started Jan 14 01:14:48 PM PST 24
Finished Jan 14 01:14:57 PM PST 24
Peak memory 202416 kb
Host smart-0c3c9fa2-7f45-4b1d-9038-3cabee7bf554
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916130363 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_mem_rw_with_rand_reset.3916130363
Directory /workspace/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2861966967
Short name T117
Test name
Test status
Simulation time 192435440 ps
CPU time 2.33 seconds
Started Jan 14 01:14:36 PM PST 24
Finished Jan 14 01:14:39 PM PST 24
Peak memory 202424 kb
Host smart-a7b2ab5c-6658-4a73-af12-67e121bd4de6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861966967 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 0.sram_ctrl_tl_intg_err.2861966967
Directory /workspace/0.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.4122819987
Short name T187
Test name
Test status
Simulation time 181324691 ps
CPU time 0.79 seconds
Started Jan 14 01:14:34 PM PST 24
Finished Jan 14 01:14:36 PM PST 24
Peak memory 202144 kb
Host smart-f1575a3a-918a-463e-89d5-3d4c1f5578ca
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122819987 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.sram_ctrl_csr_aliasing.4122819987
Directory /workspace/0.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.994295200
Short name T177
Test name
Test status
Simulation time 59269025 ps
CPU time 1.29 seconds
Started Jan 14 01:14:34 PM PST 24
Finished Jan 14 01:14:36 PM PST 24
Peak memory 202088 kb
Host smart-e068658d-2e4d-499f-ab91-cc8a40f18db7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994295200 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.sram_ctrl_csr_bit_bash.994295200
Directory /workspace/0.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1857893234
Short name T188
Test name
Test status
Simulation time 54516926 ps
CPU time 0.66 seconds
Started Jan 14 01:14:35 PM PST 24
Finished Jan 14 01:14:36 PM PST 24
Peak memory 201244 kb
Host smart-c6f0d34f-01ee-4863-b03c-04b5c5365f69
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857893234 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.sram_ctrl_csr_hw_reset.1857893234
Directory /workspace/0.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1155378366
Short name T160
Test name
Test status
Simulation time 109960213 ps
CPU time 0.68 seconds
Started Jan 14 01:14:32 PM PST 24
Finished Jan 14 01:14:34 PM PST 24
Peak memory 201464 kb
Host smart-0baf64f2-c3b8-4165-be3d-47815a249f13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155378366 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 0.sram_ctrl_csr_rw.1155378366
Directory /workspace/0.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1734546612
Short name T144
Test name
Test status
Simulation time 14407405327 ps
CPU time 123.34 seconds
Started Jan 14 01:14:35 PM PST 24
Finished Jan 14 01:16:40 PM PST 24
Peak memory 210668 kb
Host smart-ebf0a33d-687c-4bd0-84ad-b0f243b9569f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734546612 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.sram_ctrl_passthru_mem_tl_intg_err.1734546612
Directory /workspace/0.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3184524854
Short name T149
Test name
Test status
Simulation time 156048215 ps
CPU time 0.84 seconds
Started Jan 14 01:14:33 PM PST 24
Finished Jan 14 01:14:35 PM PST 24
Peak memory 202084 kb
Host smart-ef1b5139-ea3a-45b3-90d1-5667b4432a32
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184524854 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.sram_ctrl_same_csr_outstanding.3184524854
Directory /workspace/0.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2747289996
Short name T194
Test name
Test status
Simulation time 45808135 ps
CPU time 3.31 seconds
Started Jan 14 01:14:34 PM PST 24
Finished Jan 14 01:14:38 PM PST 24
Peak memory 202368 kb
Host smart-03855f75-56a5-4d34-a4af-5e280c86b730
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747289996 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 0.sram_ctrl_tl_errors.2747289996
Directory /workspace/0.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1925457725
Short name T200
Test name
Test status
Simulation time 22530032 ps
CPU time 0.72 seconds
Started Jan 14 01:14:47 PM PST 24
Finished Jan 14 01:14:52 PM PST 24
Peak memory 201196 kb
Host smart-b82b485c-a0de-4e54-8797-bfc197be9e23
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925457725 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.sram_ctrl_csr_aliasing.1925457725
Directory /workspace/1.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2581645066
Short name T142
Test name
Test status
Simulation time 91187850 ps
CPU time 1.1 seconds
Started Jan 14 01:15:00 PM PST 24
Finished Jan 14 01:15:07 PM PST 24
Peak memory 202268 kb
Host smart-4baef8ff-4716-4bfa-a804-14ef96440e64
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581645066 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.sram_ctrl_csr_bit_bash.2581645066
Directory /workspace/1.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1018595075
Short name T209
Test name
Test status
Simulation time 39769102 ps
CPU time 0.67 seconds
Started Jan 14 01:14:47 PM PST 24
Finished Jan 14 01:14:52 PM PST 24
Peak memory 202112 kb
Host smart-5953dd65-cbcf-4160-b19b-8fee3475989a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018595075 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.sram_ctrl_csr_hw_reset.1018595075
Directory /workspace/1.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3457605592
Short name T55
Test name
Test status
Simulation time 4201803921 ps
CPU time 7.27 seconds
Started Jan 14 01:14:49 PM PST 24
Finished Jan 14 01:14:59 PM PST 24
Peak memory 202456 kb
Host smart-8bb850c2-37e7-4764-9a48-5af9a030dd1c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457605592 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_mem_rw_with_rand_reset.3457605592
Directory /workspace/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.4102039355
Short name T203
Test name
Test status
Simulation time 43032588 ps
CPU time 0.68 seconds
Started Jan 14 01:14:51 PM PST 24
Finished Jan 14 01:14:53 PM PST 24
Peak memory 201324 kb
Host smart-32680f98-b1a9-4e3a-95b9-ae8fa30497a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102039355 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 1.sram_ctrl_csr_rw.4102039355
Directory /workspace/1.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.719229222
Short name T94
Test name
Test status
Simulation time 3762274477 ps
CPU time 64.03 seconds
Started Jan 14 01:14:49 PM PST 24
Finished Jan 14 01:15:55 PM PST 24
Peak memory 210644 kb
Host smart-6344655a-9608-45a6-a897-2bcebc88d258
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719229222 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.sram_ctrl_passthru_mem_tl_intg_err.719229222
Directory /workspace/1.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1203685997
Short name T195
Test name
Test status
Simulation time 22136259 ps
CPU time 0.72 seconds
Started Jan 14 01:14:56 PM PST 24
Finished Jan 14 01:14:58 PM PST 24
Peak memory 202164 kb
Host smart-b36938f9-477d-43e1-a5fe-d400a739e9af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203685997 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.sram_ctrl_same_csr_outstanding.1203685997
Directory /workspace/1.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3118801652
Short name T151
Test name
Test status
Simulation time 110810780 ps
CPU time 4.02 seconds
Started Jan 14 01:14:51 PM PST 24
Finished Jan 14 01:14:57 PM PST 24
Peak memory 202336 kb
Host smart-8e67afe1-0c9c-455c-8d77-8dc119677513
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118801652 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 1.sram_ctrl_tl_errors.3118801652
Directory /workspace/1.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1818396001
Short name T69
Test name
Test status
Simulation time 1365747884 ps
CPU time 2.29 seconds
Started Jan 14 01:14:55 PM PST 24
Finished Jan 14 01:14:59 PM PST 24
Peak memory 202364 kb
Host smart-d7cd9051-a3c3-47c6-9c22-69c11e4a7607
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818396001 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 1.sram_ctrl_tl_intg_err.1818396001
Directory /workspace/1.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.318494903
Short name T33
Test name
Test status
Simulation time 369623085 ps
CPU time 14.24 seconds
Started Jan 14 01:14:58 PM PST 24
Finished Jan 14 01:15:19 PM PST 24
Peak memory 210676 kb
Host smart-16ffcc19-928d-45c6-948b-1e83cd530bb7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318494903 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_mem_rw_with_rand_reset.318494903
Directory /workspace/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2501918032
Short name T186
Test name
Test status
Simulation time 15497806 ps
CPU time 0.74 seconds
Started Jan 14 01:14:54 PM PST 24
Finished Jan 14 01:14:56 PM PST 24
Peak memory 202112 kb
Host smart-8f027bbb-0d38-4336-906c-a4b974559fba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501918032 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 10.sram_ctrl_csr_rw.2501918032
Directory /workspace/10.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2150852703
Short name T215
Test name
Test status
Simulation time 15388083424 ps
CPU time 54.62 seconds
Started Jan 14 01:14:54 PM PST 24
Finished Jan 14 01:15:50 PM PST 24
Peak memory 210672 kb
Host smart-78dd278d-8289-4009-a12e-2e8ffe4af111
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150852703 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 10.sram_ctrl_passthru_mem_tl_intg_err.2150852703
Directory /workspace/10.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1947140476
Short name T86
Test name
Test status
Simulation time 38615960 ps
CPU time 0.69 seconds
Started Jan 14 01:14:57 PM PST 24
Finished Jan 14 01:14:58 PM PST 24
Peak memory 201796 kb
Host smart-1cd84c20-7330-4571-8b17-a2260a4f7e47
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947140476 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.sram_ctrl_same_csr_outstanding.1947140476
Directory /workspace/10.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.629811248
Short name T72
Test name
Test status
Simulation time 367606489 ps
CPU time 3.39 seconds
Started Jan 14 01:15:00 PM PST 24
Finished Jan 14 01:15:10 PM PST 24
Peak memory 202304 kb
Host smart-b1c45df0-8eae-46d8-ba74-70929418e466
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629811248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
10.sram_ctrl_tl_errors.629811248
Directory /workspace/10.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2431239227
Short name T114
Test name
Test status
Simulation time 449363710 ps
CPU time 1.96 seconds
Started Jan 14 01:14:58 PM PST 24
Finished Jan 14 01:15:00 PM PST 24
Peak memory 210556 kb
Host smart-e847e385-2c71-4fa2-8a65-1adffef7a8bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431239227 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 10.sram_ctrl_tl_intg_err.2431239227
Directory /workspace/10.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2897029238
Short name T60
Test name
Test status
Simulation time 1389622970 ps
CPU time 6.35 seconds
Started Jan 14 01:15:01 PM PST 24
Finished Jan 14 01:15:13 PM PST 24
Peak memory 210560 kb
Host smart-01aa804b-0e8f-4f55-b5e5-703e5749ff28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897029238 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_mem_rw_with_rand_reset.2897029238
Directory /workspace/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.328844668
Short name T201
Test name
Test status
Simulation time 13880478 ps
CPU time 0.67 seconds
Started Jan 14 01:15:01 PM PST 24
Finished Jan 14 01:15:07 PM PST 24
Peak memory 201460 kb
Host smart-af16d1a4-dac5-489b-aa60-28cfcb0376dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328844668 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 11.sram_ctrl_csr_rw.328844668
Directory /workspace/11.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1556975922
Short name T63
Test name
Test status
Simulation time 14406720278 ps
CPU time 124.4 seconds
Started Jan 14 01:15:03 PM PST 24
Finished Jan 14 01:17:11 PM PST 24
Peak memory 210756 kb
Host smart-8e1a837f-de08-42c6-aa76-e5fd642ce668
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556975922 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 11.sram_ctrl_passthru_mem_tl_intg_err.1556975922
Directory /workspace/11.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3962950815
Short name T208
Test name
Test status
Simulation time 24818677 ps
CPU time 0.77 seconds
Started Jan 14 01:14:55 PM PST 24
Finished Jan 14 01:14:56 PM PST 24
Peak memory 202120 kb
Host smart-e3c0d8e5-4d56-4627-bc41-404d77ab5bec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962950815 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.sram_ctrl_same_csr_outstanding.3962950815
Directory /workspace/11.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.189189093
Short name T150
Test name
Test status
Simulation time 45129125 ps
CPU time 2.41 seconds
Started Jan 14 01:14:51 PM PST 24
Finished Jan 14 01:14:55 PM PST 24
Peak memory 202452 kb
Host smart-7d38155a-8dd3-469f-b7b6-d84cb634c32b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189189093 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
11.sram_ctrl_tl_errors.189189093
Directory /workspace/11.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3613008007
Short name T111
Test name
Test status
Simulation time 375857513 ps
CPU time 2.3 seconds
Started Jan 14 01:15:00 PM PST 24
Finished Jan 14 01:15:08 PM PST 24
Peak memory 202348 kb
Host smart-98003b6a-24ba-4848-bb0b-f200de8e3656
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613008007 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 11.sram_ctrl_tl_intg_err.3613008007
Directory /workspace/11.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3983166870
Short name T180
Test name
Test status
Simulation time 738194148 ps
CPU time 14.35 seconds
Started Jan 14 01:14:57 PM PST 24
Finished Jan 14 01:15:12 PM PST 24
Peak memory 210616 kb
Host smart-cf2f0f9d-b4b1-4c5f-b308-4642f801512f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983166870 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_mem_rw_with_rand_reset.3983166870
Directory /workspace/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1855276527
Short name T171
Test name
Test status
Simulation time 24849793 ps
CPU time 0.64 seconds
Started Jan 14 01:14:58 PM PST 24
Finished Jan 14 01:14:59 PM PST 24
Peak memory 202184 kb
Host smart-6763b34d-c2f6-48ab-991c-2148cbfbb33e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855276527 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 12.sram_ctrl_csr_rw.1855276527
Directory /workspace/12.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3108451880
Short name T88
Test name
Test status
Simulation time 29340426419 ps
CPU time 275.74 seconds
Started Jan 14 01:14:59 PM PST 24
Finished Jan 14 01:19:42 PM PST 24
Peak memory 202528 kb
Host smart-60433e90-2036-4954-8694-18aba5e873a9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108451880 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 12.sram_ctrl_passthru_mem_tl_intg_err.3108451880
Directory /workspace/12.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1834861290
Short name T145
Test name
Test status
Simulation time 44867854 ps
CPU time 0.73 seconds
Started Jan 14 01:15:12 PM PST 24
Finished Jan 14 01:15:17 PM PST 24
Peak memory 201840 kb
Host smart-793dcc68-b333-4060-8e61-b381efc04d3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834861290 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.sram_ctrl_same_csr_outstanding.1834861290
Directory /workspace/12.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1019489964
Short name T192
Test name
Test status
Simulation time 125143544 ps
CPU time 2.55 seconds
Started Jan 14 01:15:01 PM PST 24
Finished Jan 14 01:15:09 PM PST 24
Peak memory 202396 kb
Host smart-e322c589-c1f7-46b9-823a-11bc4eb98347
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019489964 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 12.sram_ctrl_tl_errors.1019489964
Directory /workspace/12.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.4192195098
Short name T113
Test name
Test status
Simulation time 171265291 ps
CPU time 2.18 seconds
Started Jan 14 01:14:54 PM PST 24
Finished Jan 14 01:14:58 PM PST 24
Peak memory 202392 kb
Host smart-a4ff83b3-fa56-4ed8-8ab0-c6f5e43b864c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192195098 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 12.sram_ctrl_tl_intg_err.4192195098
Directory /workspace/12.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2450442186
Short name T146
Test name
Test status
Simulation time 1435207180 ps
CPU time 4.98 seconds
Started Jan 14 01:15:02 PM PST 24
Finished Jan 14 01:15:11 PM PST 24
Peak memory 202396 kb
Host smart-78d6b71b-2d12-4734-8a3b-dfaebd04abb9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450442186 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_mem_rw_with_rand_reset.2450442186
Directory /workspace/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2138857683
Short name T183
Test name
Test status
Simulation time 18110720 ps
CPU time 0.67 seconds
Started Jan 14 01:15:00 PM PST 24
Finished Jan 14 01:15:07 PM PST 24
Peak memory 201508 kb
Host smart-a5303cdf-4de9-41e6-9c9f-31e8709f62f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138857683 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 13.sram_ctrl_csr_rw.2138857683
Directory /workspace/13.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.425353205
Short name T82
Test name
Test status
Simulation time 60193886 ps
CPU time 0.69 seconds
Started Jan 14 01:15:00 PM PST 24
Finished Jan 14 01:15:07 PM PST 24
Peak memory 202100 kb
Host smart-43dc1d8a-4aea-4ce2-89d2-a2fe524ca430
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425353205 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.sram_ctrl_same_csr_outstanding.425353205
Directory /workspace/13.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.182364020
Short name T166
Test name
Test status
Simulation time 28988347 ps
CPU time 2.62 seconds
Started Jan 14 01:15:02 PM PST 24
Finished Jan 14 01:15:09 PM PST 24
Peak memory 202428 kb
Host smart-fef4b9b3-d79f-4a6a-993f-337d70a9b708
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182364020 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
13.sram_ctrl_tl_errors.182364020
Directory /workspace/13.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.139831002
Short name T58
Test name
Test status
Simulation time 137480342 ps
CPU time 1.53 seconds
Started Jan 14 01:15:01 PM PST 24
Finished Jan 14 01:15:08 PM PST 24
Peak memory 202416 kb
Host smart-533e12ab-d4ac-45b9-abc3-c2c2d8a8cb20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139831002 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 13.sram_ctrl_tl_intg_err.139831002
Directory /workspace/13.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1937012021
Short name T181
Test name
Test status
Simulation time 371914065 ps
CPU time 5.84 seconds
Started Jan 14 01:15:02 PM PST 24
Finished Jan 14 01:15:12 PM PST 24
Peak memory 202364 kb
Host smart-9ccf4930-0afc-4deb-b381-e915c0a4d925
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937012021 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_mem_rw_with_rand_reset.1937012021
Directory /workspace/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.923806636
Short name T66
Test name
Test status
Simulation time 94230636 ps
CPU time 0.68 seconds
Started Jan 14 01:15:01 PM PST 24
Finished Jan 14 01:15:07 PM PST 24
Peak memory 202104 kb
Host smart-cc592554-3385-4ade-b304-ea25b3514a43
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923806636 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 14.sram_ctrl_csr_rw.923806636
Directory /workspace/14.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1479021504
Short name T196
Test name
Test status
Simulation time 29358073874 ps
CPU time 124.96 seconds
Started Jan 14 01:15:01 PM PST 24
Finished Jan 14 01:17:11 PM PST 24
Peak memory 202444 kb
Host smart-cbd9adee-11cf-46e9-89a0-cbf7cd1adf18
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479021504 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 14.sram_ctrl_passthru_mem_tl_intg_err.1479021504
Directory /workspace/14.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3588456588
Short name T141
Test name
Test status
Simulation time 17146686 ps
CPU time 0.72 seconds
Started Jan 14 01:15:02 PM PST 24
Finished Jan 14 01:15:07 PM PST 24
Peak memory 202212 kb
Host smart-03e6a0e1-4649-46b3-a482-16f1bc840263
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588456588 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.sram_ctrl_same_csr_outstanding.3588456588
Directory /workspace/14.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1327328175
Short name T214
Test name
Test status
Simulation time 26695392 ps
CPU time 1.73 seconds
Started Jan 14 01:15:12 PM PST 24
Finished Jan 14 01:15:17 PM PST 24
Peak memory 202404 kb
Host smart-57ed0483-1121-43ee-a82e-1cd12063bab9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327328175 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 14.sram_ctrl_tl_errors.1327328175
Directory /workspace/14.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.157711436
Short name T204
Test name
Test status
Simulation time 272336055 ps
CPU time 2.3 seconds
Started Jan 14 01:15:00 PM PST 24
Finished Jan 14 01:15:08 PM PST 24
Peak memory 202320 kb
Host smart-39818173-ff33-4ebe-bd65-cade7b275b93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157711436 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 14.sram_ctrl_tl_intg_err.157711436
Directory /workspace/14.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.669088932
Short name T174
Test name
Test status
Simulation time 378119218 ps
CPU time 14.53 seconds
Started Jan 14 01:15:10 PM PST 24
Finished Jan 14 01:15:28 PM PST 24
Peak memory 210504 kb
Host smart-b172858f-b9c4-427a-a53a-644ff28a50bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669088932 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_mem_rw_with_rand_reset.669088932
Directory /workspace/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2891565429
Short name T185
Test name
Test status
Simulation time 20920194 ps
CPU time 0.62 seconds
Started Jan 14 01:15:05 PM PST 24
Finished Jan 14 01:15:12 PM PST 24
Peak memory 201376 kb
Host smart-37248311-9424-4881-9517-ed39d708e3ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891565429 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 15.sram_ctrl_csr_rw.2891565429
Directory /workspace/15.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2309203867
Short name T75
Test name
Test status
Simulation time 25195320686 ps
CPU time 137.54 seconds
Started Jan 14 01:15:02 PM PST 24
Finished Jan 14 01:17:24 PM PST 24
Peak memory 210712 kb
Host smart-85c75b86-1694-42dc-888b-c65f4a6813c8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309203867 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 15.sram_ctrl_passthru_mem_tl_intg_err.2309203867
Directory /workspace/15.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.93280528
Short name T65
Test name
Test status
Simulation time 170968124 ps
CPU time 0.74 seconds
Started Jan 14 01:15:11 PM PST 24
Finished Jan 14 01:15:15 PM PST 24
Peak memory 202224 kb
Host smart-ac1865c8-5f62-450b-af00-8d0fd902f951
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93280528 -assert nopostproc +UVM_TESTNAME=sram_ctr
l_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 15.sram_ctrl_same_csr_outstanding.93280528
Directory /workspace/15.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1737412538
Short name T59
Test name
Test status
Simulation time 134864900 ps
CPU time 3.82 seconds
Started Jan 14 01:15:09 PM PST 24
Finished Jan 14 01:15:17 PM PST 24
Peak memory 202404 kb
Host smart-a3b614d1-8b7b-4997-9fb5-2deac76d4af1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737412538 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 15.sram_ctrl_tl_errors.1737412538
Directory /workspace/15.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2107210976
Short name T68
Test name
Test status
Simulation time 355524319 ps
CPU time 5.13 seconds
Started Jan 14 01:15:05 PM PST 24
Finished Jan 14 01:15:16 PM PST 24
Peak memory 210564 kb
Host smart-1694163e-f21f-4d49-bbd9-6abb9c485e65
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107210976 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_mem_rw_with_rand_reset.2107210976
Directory /workspace/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.4103610004
Short name T193
Test name
Test status
Simulation time 12186802 ps
CPU time 0.67 seconds
Started Jan 14 01:15:11 PM PST 24
Finished Jan 14 01:15:15 PM PST 24
Peak memory 201260 kb
Host smart-b64d6a5f-b923-4d1b-b331-5cec2f89aca4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103610004 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 16.sram_ctrl_csr_rw.4103610004
Directory /workspace/16.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3791289752
Short name T91
Test name
Test status
Simulation time 28168469430 ps
CPU time 296.93 seconds
Started Jan 14 01:15:11 PM PST 24
Finished Jan 14 01:20:11 PM PST 24
Peak memory 202560 kb
Host smart-4cd963b6-fffc-4e9a-a38d-c69a6c9fdbec
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791289752 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 16.sram_ctrl_passthru_mem_tl_intg_err.3791289752
Directory /workspace/16.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1276488482
Short name T168
Test name
Test status
Simulation time 24787246 ps
CPU time 0.76 seconds
Started Jan 14 01:15:08 PM PST 24
Finished Jan 14 01:15:13 PM PST 24
Peak memory 201988 kb
Host smart-79276b06-d5e9-4897-9c64-55b02e59215c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276488482 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.sram_ctrl_same_csr_outstanding.1276488482
Directory /workspace/16.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2086174866
Short name T153
Test name
Test status
Simulation time 72590820 ps
CPU time 2.52 seconds
Started Jan 14 01:15:04 PM PST 24
Finished Jan 14 01:15:10 PM PST 24
Peak memory 210592 kb
Host smart-ff23510f-a30e-4432-9b2b-8055ee0403c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086174866 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 16.sram_ctrl_tl_errors.2086174866
Directory /workspace/16.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.892806737
Short name T50
Test name
Test status
Simulation time 309542154 ps
CPU time 1.39 seconds
Started Jan 14 01:15:04 PM PST 24
Finished Jan 14 01:15:10 PM PST 24
Peak memory 202444 kb
Host smart-b019fdbe-f2ab-4c90-bb02-89e1365cfbd8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892806737 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 16.sram_ctrl_tl_intg_err.892806737
Directory /workspace/16.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1820637142
Short name T184
Test name
Test status
Simulation time 1739962631 ps
CPU time 6.05 seconds
Started Jan 14 01:15:10 PM PST 24
Finished Jan 14 01:15:20 PM PST 24
Peak memory 202432 kb
Host smart-e6cff0fe-80cd-4919-81fc-b450a4a89cb0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820637142 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_mem_rw_with_rand_reset.1820637142
Directory /workspace/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.4013825076
Short name T190
Test name
Test status
Simulation time 13820275 ps
CPU time 0.67 seconds
Started Jan 14 01:15:11 PM PST 24
Finished Jan 14 01:15:16 PM PST 24
Peak memory 202136 kb
Host smart-825e8ab8-9e9d-4bdd-a800-655551732dfb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013825076 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 17.sram_ctrl_csr_rw.4013825076
Directory /workspace/17.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.562746012
Short name T84
Test name
Test status
Simulation time 7550641218 ps
CPU time 55.19 seconds
Started Jan 14 01:15:09 PM PST 24
Finished Jan 14 01:16:08 PM PST 24
Peak memory 202488 kb
Host smart-a0fee8e4-bdad-4706-b843-1dc2b5ab3999
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562746012 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 17.sram_ctrl_passthru_mem_tl_intg_err.562746012
Directory /workspace/17.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.161476137
Short name T83
Test name
Test status
Simulation time 44074223 ps
CPU time 0.65 seconds
Started Jan 14 01:15:07 PM PST 24
Finished Jan 14 01:15:13 PM PST 24
Peak memory 202232 kb
Host smart-7822420c-6c72-4e9a-aefb-fb64da1096fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161476137 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.sram_ctrl_same_csr_outstanding.161476137
Directory /workspace/17.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.4060443011
Short name T205
Test name
Test status
Simulation time 31032792 ps
CPU time 2.87 seconds
Started Jan 14 01:15:11 PM PST 24
Finished Jan 14 01:15:17 PM PST 24
Peak memory 202336 kb
Host smart-68211bb7-cbc9-41cc-b5a5-8cda25b1ef01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060443011 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 17.sram_ctrl_tl_errors.4060443011
Directory /workspace/17.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.179954048
Short name T162
Test name
Test status
Simulation time 388672151 ps
CPU time 1.46 seconds
Started Jan 14 01:15:07 PM PST 24
Finished Jan 14 01:15:14 PM PST 24
Peak memory 202436 kb
Host smart-574e6dbb-17d9-4c23-9295-539c486e451d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179954048 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 17.sram_ctrl_tl_intg_err.179954048
Directory /workspace/17.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3280295296
Short name T172
Test name
Test status
Simulation time 698657145 ps
CPU time 5.4 seconds
Started Jan 14 01:15:11 PM PST 24
Finished Jan 14 01:15:20 PM PST 24
Peak memory 210544 kb
Host smart-6c264cd2-bbc5-42f7-a768-6b134845189e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280295296 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_mem_rw_with_rand_reset.3280295296
Directory /workspace/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.4281147685
Short name T207
Test name
Test status
Simulation time 12711932 ps
CPU time 0.72 seconds
Started Jan 14 01:15:09 PM PST 24
Finished Jan 14 01:15:14 PM PST 24
Peak memory 201180 kb
Host smart-77328745-4321-43d7-b90d-e820bc4fbfc1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281147685 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 18.sram_ctrl_csr_rw.4281147685
Directory /workspace/18.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1221927439
Short name T74
Test name
Test status
Simulation time 3911551891 ps
CPU time 137.1 seconds
Started Jan 14 01:15:10 PM PST 24
Finished Jan 14 01:17:31 PM PST 24
Peak memory 202464 kb
Host smart-b5a1fc62-1af8-403b-8227-d08c696cd0d4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221927439 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 18.sram_ctrl_passthru_mem_tl_intg_err.1221927439
Directory /workspace/18.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1689704772
Short name T159
Test name
Test status
Simulation time 17356166 ps
CPU time 0.7 seconds
Started Jan 14 01:15:09 PM PST 24
Finished Jan 14 01:15:14 PM PST 24
Peak memory 201884 kb
Host smart-3b7cdcdc-8304-41c0-9d5c-557f3fd1f055
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689704772 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.sram_ctrl_same_csr_outstanding.1689704772
Directory /workspace/18.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2650261556
Short name T157
Test name
Test status
Simulation time 73469539 ps
CPU time 2.56 seconds
Started Jan 14 01:15:12 PM PST 24
Finished Jan 14 01:15:18 PM PST 24
Peak memory 201632 kb
Host smart-47fb2432-2d63-4a36-9fb5-5d60743059d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650261556 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 18.sram_ctrl_tl_errors.2650261556
Directory /workspace/18.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2076359248
Short name T211
Test name
Test status
Simulation time 238202710 ps
CPU time 1.47 seconds
Started Jan 14 01:15:11 PM PST 24
Finished Jan 14 01:15:16 PM PST 24
Peak memory 202332 kb
Host smart-ec8733e5-5a0e-450e-9bb8-a6d26e3b1f7f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076359248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 18.sram_ctrl_tl_intg_err.2076359248
Directory /workspace/18.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.458969255
Short name T133
Test name
Test status
Simulation time 380703030 ps
CPU time 5.93 seconds
Started Jan 14 01:15:05 PM PST 24
Finished Jan 14 01:15:17 PM PST 24
Peak memory 210724 kb
Host smart-61b71a6c-8891-4497-a437-4a84e904a512
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458969255 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_mem_rw_with_rand_reset.458969255
Directory /workspace/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1211592987
Short name T163
Test name
Test status
Simulation time 15086603 ps
CPU time 0.62 seconds
Started Jan 14 01:15:10 PM PST 24
Finished Jan 14 01:15:14 PM PST 24
Peak memory 201228 kb
Host smart-cb8b71f0-f9d7-4c80-97ac-5fef420b5915
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211592987 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 19.sram_ctrl_csr_rw.1211592987
Directory /workspace/19.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2192412384
Short name T198
Test name
Test status
Simulation time 141169844736 ps
CPU time 139.43 seconds
Started Jan 14 01:15:04 PM PST 24
Finished Jan 14 01:17:27 PM PST 24
Peak memory 210676 kb
Host smart-bb46de2c-5536-48de-9878-80e55864db27
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192412384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 19.sram_ctrl_passthru_mem_tl_intg_err.2192412384
Directory /workspace/19.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3938080664
Short name T178
Test name
Test status
Simulation time 137451697 ps
CPU time 0.68 seconds
Started Jan 14 01:15:11 PM PST 24
Finished Jan 14 01:15:16 PM PST 24
Peak memory 202168 kb
Host smart-0b56b3bc-2f62-4bfb-a7f8-881fbb063c5b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938080664 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.sram_ctrl_same_csr_outstanding.3938080664
Directory /workspace/19.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.13997815
Short name T182
Test name
Test status
Simulation time 35100843 ps
CPU time 3.46 seconds
Started Jan 14 01:15:09 PM PST 24
Finished Jan 14 01:15:16 PM PST 24
Peak memory 202236 kb
Host smart-c8d12e92-35b8-4b80-95d3-a72e6b7e5f19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13997815 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST
_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
19.sram_ctrl_tl_errors.13997815
Directory /workspace/19.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1051840167
Short name T143
Test name
Test status
Simulation time 15726446 ps
CPU time 0.72 seconds
Started Jan 14 01:14:55 PM PST 24
Finished Jan 14 01:14:57 PM PST 24
Peak memory 201972 kb
Host smart-a0cc23d4-3c3f-4ba9-ba91-20035e4c218e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051840167 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.sram_ctrl_csr_aliasing.1051840167
Directory /workspace/2.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2760331148
Short name T175
Test name
Test status
Simulation time 74337057 ps
CPU time 1.75 seconds
Started Jan 14 01:15:12 PM PST 24
Finished Jan 14 01:15:18 PM PST 24
Peak memory 201244 kb
Host smart-b5a4a252-dfb9-4ed0-a658-0dfc86fcf0d0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760331148 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.sram_ctrl_csr_bit_bash.2760331148
Directory /workspace/2.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1412229786
Short name T148
Test name
Test status
Simulation time 33432571 ps
CPU time 0.62 seconds
Started Jan 14 01:15:01 PM PST 24
Finished Jan 14 01:15:07 PM PST 24
Peak memory 201408 kb
Host smart-44f4736c-535b-41de-a997-4dc9c772b9a1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412229786 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.sram_ctrl_csr_hw_reset.1412229786
Directory /workspace/2.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.508533358
Short name T155
Test name
Test status
Simulation time 366154126 ps
CPU time 5.78 seconds
Started Jan 14 01:15:02 PM PST 24
Finished Jan 14 01:15:12 PM PST 24
Peak memory 202428 kb
Host smart-9035dfc9-d187-4a13-8774-86be9e28c76f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508533358 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_mem_rw_with_rand_reset.508533358
Directory /workspace/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1232727116
Short name T161
Test name
Test status
Simulation time 39610747 ps
CPU time 0.66 seconds
Started Jan 14 01:14:54 PM PST 24
Finished Jan 14 01:14:56 PM PST 24
Peak memory 202020 kb
Host smart-75e085d8-cf7d-457a-8c27-c83c78e688e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232727116 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 2.sram_ctrl_csr_rw.1232727116
Directory /workspace/2.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2324636124
Short name T73
Test name
Test status
Simulation time 15646859267 ps
CPU time 109.09 seconds
Started Jan 14 01:14:53 PM PST 24
Finished Jan 14 01:16:44 PM PST 24
Peak memory 211620 kb
Host smart-d6bb2e69-b65a-44f3-88b2-2bd1378daa34
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324636124 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.sram_ctrl_passthru_mem_tl_intg_err.2324636124
Directory /workspace/2.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.69711565
Short name T70
Test name
Test status
Simulation time 44306702 ps
CPU time 0.67 seconds
Started Jan 14 01:15:01 PM PST 24
Finished Jan 14 01:15:07 PM PST 24
Peak memory 201476 kb
Host smart-95feec70-88f1-4d7e-9ee4-b501d589bc3f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69711565 -assert nopostproc +UVM_TESTNAME=sram_ctr
l_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 2.sram_ctrl_same_csr_outstanding.69711565
Directory /workspace/2.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2275765486
Short name T216
Test name
Test status
Simulation time 901103448 ps
CPU time 2.57 seconds
Started Jan 14 01:15:03 PM PST 24
Finished Jan 14 01:15:10 PM PST 24
Peak memory 202392 kb
Host smart-13b33c86-549b-4c65-b9cc-f78c652ae929
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275765486 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 2.sram_ctrl_tl_intg_err.2275765486
Directory /workspace/2.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2094512328
Short name T67
Test name
Test status
Simulation time 21453024 ps
CPU time 0.68 seconds
Started Jan 14 01:15:01 PM PST 24
Finished Jan 14 01:15:07 PM PST 24
Peak memory 201296 kb
Host smart-b0db4cd2-5416-4517-b39e-b6b356920ea6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094512328 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.sram_ctrl_csr_aliasing.2094512328
Directory /workspace/3.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2181085714
Short name T64
Test name
Test status
Simulation time 56386628 ps
CPU time 1.25 seconds
Started Jan 14 01:14:59 PM PST 24
Finished Jan 14 01:15:07 PM PST 24
Peak memory 202336 kb
Host smart-4c524c28-09a4-4ed2-b7c2-d14a96acf5a2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181085714 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.sram_ctrl_csr_bit_bash.2181085714
Directory /workspace/3.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.4012526223
Short name T170
Test name
Test status
Simulation time 46757604 ps
CPU time 0.73 seconds
Started Jan 14 01:15:04 PM PST 24
Finished Jan 14 01:15:09 PM PST 24
Peak memory 201268 kb
Host smart-cf74e2b1-12cb-4300-b6d6-02f745501a42
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012526223 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.sram_ctrl_csr_hw_reset.4012526223
Directory /workspace/3.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2363366462
Short name T213
Test name
Test status
Simulation time 1328065796 ps
CPU time 5.26 seconds
Started Jan 14 01:15:03 PM PST 24
Finished Jan 14 01:15:12 PM PST 24
Peak memory 202436 kb
Host smart-ef2714ea-c07d-45da-92bf-437e706c1c19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363366462 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_mem_rw_with_rand_reset.2363366462
Directory /workspace/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2876311181
Short name T199
Test name
Test status
Simulation time 37000598 ps
CPU time 0.66 seconds
Started Jan 14 01:15:04 PM PST 24
Finished Jan 14 01:15:09 PM PST 24
Peak memory 201240 kb
Host smart-1bfeca48-80b8-48f4-ba38-b094cb4c565a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876311181 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 3.sram_ctrl_csr_rw.2876311181
Directory /workspace/3.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1074675232
Short name T101
Test name
Test status
Simulation time 24322445716 ps
CPU time 122.45 seconds
Started Jan 14 01:15:02 PM PST 24
Finished Jan 14 01:17:09 PM PST 24
Peak memory 202516 kb
Host smart-f70417b8-4f11-48b6-a53f-32659679f0df
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074675232 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.sram_ctrl_passthru_mem_tl_intg_err.1074675232
Directory /workspace/3.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1924549670
Short name T140
Test name
Test status
Simulation time 93861657 ps
CPU time 0.75 seconds
Started Jan 14 01:15:02 PM PST 24
Finished Jan 14 01:15:07 PM PST 24
Peak memory 202156 kb
Host smart-e52303ca-7a88-4be6-9e16-5e346af29f49
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924549670 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.sram_ctrl_same_csr_outstanding.1924549670
Directory /workspace/3.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2645663640
Short name T202
Test name
Test status
Simulation time 311160742 ps
CPU time 2.25 seconds
Started Jan 14 01:14:55 PM PST 24
Finished Jan 14 01:14:58 PM PST 24
Peak memory 202436 kb
Host smart-c97c6b9d-6782-4a51-a277-8d07f8929ca9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645663640 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 3.sram_ctrl_tl_errors.2645663640
Directory /workspace/3.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.858460354
Short name T85
Test name
Test status
Simulation time 17635555 ps
CPU time 0.67 seconds
Started Jan 14 01:15:04 PM PST 24
Finished Jan 14 01:15:09 PM PST 24
Peak memory 201248 kb
Host smart-2045158c-1ef0-401b-977d-129436bd295f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858460354 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.sram_ctrl_csr_aliasing.858460354
Directory /workspace/4.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2295404931
Short name T62
Test name
Test status
Simulation time 139255834 ps
CPU time 1.72 seconds
Started Jan 14 01:15:05 PM PST 24
Finished Jan 14 01:15:13 PM PST 24
Peak memory 202296 kb
Host smart-5e14409f-6c70-4f05-aa60-616ce6ebbb18
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295404931 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.sram_ctrl_csr_bit_bash.2295404931
Directory /workspace/4.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.260589318
Short name T93
Test name
Test status
Simulation time 22015763 ps
CPU time 0.72 seconds
Started Jan 14 01:15:05 PM PST 24
Finished Jan 14 01:15:12 PM PST 24
Peak memory 201644 kb
Host smart-8944c73a-190c-46a9-a508-49381e45be67
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260589318 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.sram_ctrl_csr_hw_reset.260589318
Directory /workspace/4.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2903600265
Short name T54
Test name
Test status
Simulation time 1381870888 ps
CPU time 6.64 seconds
Started Jan 14 01:15:10 PM PST 24
Finished Jan 14 01:15:20 PM PST 24
Peak memory 210676 kb
Host smart-ff4bfd17-d850-41ec-a60b-33254af953c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903600265 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_mem_rw_with_rand_reset.2903600265
Directory /workspace/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2867663254
Short name T217
Test name
Test status
Simulation time 14227211 ps
CPU time 0.67 seconds
Started Jan 14 01:15:02 PM PST 24
Finished Jan 14 01:15:07 PM PST 24
Peak memory 201460 kb
Host smart-9be2db19-22d8-4a88-b9de-00d7b3bcbd1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867663254 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 4.sram_ctrl_csr_rw.2867663254
Directory /workspace/4.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3365410121
Short name T90
Test name
Test status
Simulation time 9466348906 ps
CPU time 54.92 seconds
Started Jan 14 01:15:09 PM PST 24
Finished Jan 14 01:16:08 PM PST 24
Peak memory 210760 kb
Host smart-2801b775-7ecb-4768-901f-1df754b958ba
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365410121 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.sram_ctrl_passthru_mem_tl_intg_err.3365410121
Directory /workspace/4.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1617514181
Short name T176
Test name
Test status
Simulation time 16864282 ps
CPU time 0.71 seconds
Started Jan 14 01:15:03 PM PST 24
Finished Jan 14 01:15:07 PM PST 24
Peak memory 202240 kb
Host smart-8c1fc67c-664b-4abc-bf78-ceebf882a23d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617514181 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.sram_ctrl_same_csr_outstanding.1617514181
Directory /workspace/4.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2892569330
Short name T53
Test name
Test status
Simulation time 82038570 ps
CPU time 2.69 seconds
Started Jan 14 01:15:03 PM PST 24
Finished Jan 14 01:15:09 PM PST 24
Peak memory 202448 kb
Host smart-b2193207-2646-4227-949c-983f2cbce69b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892569330 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 4.sram_ctrl_tl_errors.2892569330
Directory /workspace/4.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.659485004
Short name T179
Test name
Test status
Simulation time 130580601 ps
CPU time 1.48 seconds
Started Jan 14 01:15:10 PM PST 24
Finished Jan 14 01:15:15 PM PST 24
Peak memory 202508 kb
Host smart-84989872-00e7-4b97-b1e3-d752b0a64cfe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659485004 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 4.sram_ctrl_tl_intg_err.659485004
Directory /workspace/4.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1342915141
Short name T57
Test name
Test status
Simulation time 363918339 ps
CPU time 12.41 seconds
Started Jan 14 01:15:09 PM PST 24
Finished Jan 14 01:15:26 PM PST 24
Peak memory 210612 kb
Host smart-c4985afc-0a9c-4407-bf85-e0022e335b62
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342915141 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_mem_rw_with_rand_reset.1342915141
Directory /workspace/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1383543284
Short name T189
Test name
Test status
Simulation time 12472334 ps
CPU time 0.63 seconds
Started Jan 14 01:15:06 PM PST 24
Finished Jan 14 01:15:12 PM PST 24
Peak memory 202056 kb
Host smart-0e47bb81-f18f-4244-82da-7d566e791439
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383543284 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 5.sram_ctrl_csr_rw.1383543284
Directory /workspace/5.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2166225137
Short name T76
Test name
Test status
Simulation time 100787388534 ps
CPU time 109.64 seconds
Started Jan 14 01:15:10 PM PST 24
Finished Jan 14 01:17:04 PM PST 24
Peak memory 210752 kb
Host smart-960a7b48-a9eb-4666-ae38-4ce0488e82df
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166225137 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.sram_ctrl_passthru_mem_tl_intg_err.2166225137
Directory /workspace/5.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1305711727
Short name T156
Test name
Test status
Simulation time 62299101 ps
CPU time 0.67 seconds
Started Jan 14 01:15:11 PM PST 24
Finished Jan 14 01:15:15 PM PST 24
Peak memory 201184 kb
Host smart-38b1c36f-fd8e-4442-af83-7f05e3d4a6d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305711727 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.sram_ctrl_same_csr_outstanding.1305711727
Directory /workspace/5.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.450084244
Short name T165
Test name
Test status
Simulation time 429297198 ps
CPU time 3.91 seconds
Started Jan 14 01:15:04 PM PST 24
Finished Jan 14 01:15:13 PM PST 24
Peak memory 210668 kb
Host smart-1bff7595-7732-4b84-8ea6-14f34822f284
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450084244 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
5.sram_ctrl_tl_errors.450084244
Directory /workspace/5.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2793682186
Short name T116
Test name
Test status
Simulation time 2802347463 ps
CPU time 2.68 seconds
Started Jan 14 01:15:11 PM PST 24
Finished Jan 14 01:15:17 PM PST 24
Peak memory 210620 kb
Host smart-3250bb13-e367-4c15-b9b7-3ca9ac0a436c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793682186 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 5.sram_ctrl_tl_intg_err.2793682186
Directory /workspace/5.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.337730146
Short name T164
Test name
Test status
Simulation time 713027111 ps
CPU time 12.49 seconds
Started Jan 14 01:14:52 PM PST 24
Finished Jan 14 01:15:07 PM PST 24
Peak memory 210580 kb
Host smart-1b0967cd-3336-463f-82a4-c65f49131bc8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337730146 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_mem_rw_with_rand_reset.337730146
Directory /workspace/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3333705257
Short name T52
Test name
Test status
Simulation time 43213371 ps
CPU time 0.62 seconds
Started Jan 14 01:14:49 PM PST 24
Finished Jan 14 01:14:52 PM PST 24
Peak memory 202120 kb
Host smart-33e11c2f-6c5e-4a99-90fe-a9de69b0f2f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333705257 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 6.sram_ctrl_csr_rw.3333705257
Directory /workspace/6.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.245809449
Short name T89
Test name
Test status
Simulation time 14730267753 ps
CPU time 160.66 seconds
Started Jan 14 01:15:11 PM PST 24
Finished Jan 14 01:17:55 PM PST 24
Peak memory 202536 kb
Host smart-1325a731-d13c-4698-acd2-a7375190f8d8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245809449 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.sram_ctrl_passthru_mem_tl_intg_err.245809449
Directory /workspace/6.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1320707631
Short name T169
Test name
Test status
Simulation time 68819603 ps
CPU time 0.73 seconds
Started Jan 14 01:15:02 PM PST 24
Finished Jan 14 01:15:07 PM PST 24
Peak memory 202200 kb
Host smart-1b48adfc-7e6e-4b97-9e0e-af6a7642898f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320707631 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.sram_ctrl_same_csr_outstanding.1320707631
Directory /workspace/6.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2866103983
Short name T173
Test name
Test status
Simulation time 94143128 ps
CPU time 2.09 seconds
Started Jan 14 01:14:48 PM PST 24
Finished Jan 14 01:14:53 PM PST 24
Peak memory 202436 kb
Host smart-f4912f47-5db9-470d-9614-8c3b2978c5d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866103983 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 6.sram_ctrl_tl_errors.2866103983
Directory /workspace/6.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.120085797
Short name T110
Test name
Test status
Simulation time 105463124 ps
CPU time 1.46 seconds
Started Jan 14 01:14:48 PM PST 24
Finished Jan 14 01:14:53 PM PST 24
Peak memory 202288 kb
Host smart-7593e1c9-e45d-4e00-b35c-ddc1eb3e049a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120085797 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 6.sram_ctrl_tl_intg_err.120085797
Directory /workspace/6.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2178028759
Short name T32
Test name
Test status
Simulation time 1305969316 ps
CPU time 4.69 seconds
Started Jan 14 01:14:50 PM PST 24
Finished Jan 14 01:14:56 PM PST 24
Peak memory 202436 kb
Host smart-de48d693-477f-42f3-98e0-0530fe04641c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178028759 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_mem_rw_with_rand_reset.2178028759
Directory /workspace/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1100499026
Short name T152
Test name
Test status
Simulation time 26733251 ps
CPU time 0.63 seconds
Started Jan 14 01:14:47 PM PST 24
Finished Jan 14 01:14:52 PM PST 24
Peak memory 201748 kb
Host smart-5196cf16-6718-42a9-89a8-c25fa95a61e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100499026 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 7.sram_ctrl_csr_rw.1100499026
Directory /workspace/7.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3070600487
Short name T81
Test name
Test status
Simulation time 7499553017 ps
CPU time 94.59 seconds
Started Jan 14 01:14:51 PM PST 24
Finished Jan 14 01:16:27 PM PST 24
Peak memory 210716 kb
Host smart-8c13c03a-5f97-4bae-b904-85ae83e77f59
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070600487 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 7.sram_ctrl_passthru_mem_tl_intg_err.3070600487
Directory /workspace/7.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1959634653
Short name T167
Test name
Test status
Simulation time 65843219 ps
CPU time 0.78 seconds
Started Jan 14 01:14:59 PM PST 24
Finished Jan 14 01:15:07 PM PST 24
Peak memory 202232 kb
Host smart-a41d87a7-3839-4315-845b-2b673228b6db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959634653 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.sram_ctrl_same_csr_outstanding.1959634653
Directory /workspace/7.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.646152138
Short name T34
Test name
Test status
Simulation time 220565797 ps
CPU time 2.08 seconds
Started Jan 14 01:14:59 PM PST 24
Finished Jan 14 01:15:08 PM PST 24
Peak memory 202296 kb
Host smart-9d6e69ef-8608-4978-8930-e190448907c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646152138 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
7.sram_ctrl_tl_errors.646152138
Directory /workspace/7.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3652791592
Short name T119
Test name
Test status
Simulation time 189708186 ps
CPU time 1.97 seconds
Started Jan 14 01:14:49 PM PST 24
Finished Jan 14 01:14:53 PM PST 24
Peak memory 202424 kb
Host smart-9920eba2-9fd2-4b4c-9b24-768f6e9b7c9b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652791592 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 7.sram_ctrl_tl_intg_err.3652791592
Directory /workspace/7.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2816066791
Short name T212
Test name
Test status
Simulation time 1150940482 ps
CPU time 6.15 seconds
Started Jan 14 01:14:55 PM PST 24
Finished Jan 14 01:15:02 PM PST 24
Peak memory 210632 kb
Host smart-8b89e775-06f8-4bf9-a6f0-fb85ad7bef92
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816066791 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_mem_rw_with_rand_reset.2816066791
Directory /workspace/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2000058887
Short name T95
Test name
Test status
Simulation time 41627687 ps
CPU time 0.66 seconds
Started Jan 14 01:14:49 PM PST 24
Finished Jan 14 01:14:52 PM PST 24
Peak memory 201424 kb
Host smart-f2dc7a4d-fd2d-4fb5-8a32-df684e912fae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000058887 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 8.sram_ctrl_csr_rw.2000058887
Directory /workspace/8.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.228972070
Short name T92
Test name
Test status
Simulation time 21702534726 ps
CPU time 64.16 seconds
Started Jan 14 01:14:54 PM PST 24
Finished Jan 14 01:16:00 PM PST 24
Peak memory 210616 kb
Host smart-682c398a-0ea6-47c8-85c9-8859ff16424b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228972070 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.sram_ctrl_passthru_mem_tl_intg_err.228972070
Directory /workspace/8.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.196924184
Short name T197
Test name
Test status
Simulation time 45647648 ps
CPU time 0.7 seconds
Started Jan 14 01:15:02 PM PST 24
Finished Jan 14 01:15:07 PM PST 24
Peak memory 201912 kb
Host smart-1dc82da8-b8c7-4d83-84e0-0161777349ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196924184 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.sram_ctrl_same_csr_outstanding.196924184
Directory /workspace/8.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1052448478
Short name T71
Test name
Test status
Simulation time 961791031 ps
CPU time 4.23 seconds
Started Jan 14 01:14:49 PM PST 24
Finished Jan 14 01:14:56 PM PST 24
Peak memory 202256 kb
Host smart-6961ef4c-c7a8-4102-9c3c-e31683e4e495
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052448478 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 8.sram_ctrl_tl_errors.1052448478
Directory /workspace/8.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.4035345598
Short name T61
Test name
Test status
Simulation time 240978121 ps
CPU time 2.37 seconds
Started Jan 14 01:14:51 PM PST 24
Finished Jan 14 01:14:55 PM PST 24
Peak memory 202428 kb
Host smart-138877c2-d27a-4525-8456-428745eacc64
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035345598 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 8.sram_ctrl_tl_intg_err.4035345598
Directory /workspace/8.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.736206296
Short name T206
Test name
Test status
Simulation time 366566635 ps
CPU time 13.29 seconds
Started Jan 14 01:14:49 PM PST 24
Finished Jan 14 01:15:05 PM PST 24
Peak memory 210532 kb
Host smart-9a8e0216-3412-49a7-9ee4-1ad7a570b06c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736206296 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_mem_rw_with_rand_reset.736206296
Directory /workspace/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.882349820
Short name T147
Test name
Test status
Simulation time 13759022 ps
CPU time 0.65 seconds
Started Jan 14 01:14:50 PM PST 24
Finished Jan 14 01:14:52 PM PST 24
Peak memory 201276 kb
Host smart-556a2e8a-f355-4d16-a298-7d8c1f4161d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882349820 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 9.sram_ctrl_csr_rw.882349820
Directory /workspace/9.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.257426937
Short name T154
Test name
Test status
Simulation time 4287096294 ps
CPU time 63.66 seconds
Started Jan 14 01:14:54 PM PST 24
Finished Jan 14 01:15:59 PM PST 24
Peak memory 210812 kb
Host smart-94ab34e9-c524-41e4-94c0-a50972555ef4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257426937 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.sram_ctrl_passthru_mem_tl_intg_err.257426937
Directory /workspace/9.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.924409689
Short name T210
Test name
Test status
Simulation time 17897923 ps
CPU time 0.69 seconds
Started Jan 14 01:14:52 PM PST 24
Finished Jan 14 01:14:56 PM PST 24
Peak memory 201828 kb
Host smart-13f4960d-ae89-4741-8bf0-71dddd6f0cd1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924409689 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.sram_ctrl_same_csr_outstanding.924409689
Directory /workspace/9.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2389537220
Short name T191
Test name
Test status
Simulation time 329690653 ps
CPU time 2.15 seconds
Started Jan 14 01:14:55 PM PST 24
Finished Jan 14 01:14:58 PM PST 24
Peak memory 202392 kb
Host smart-dde2d050-d30a-4210-bc2e-ef6ea7ba17dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389537220 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 9.sram_ctrl_tl_errors.2389537220
Directory /workspace/9.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.115086142
Short name T118
Test name
Test status
Simulation time 607338608 ps
CPU time 1.47 seconds
Started Jan 14 01:14:47 PM PST 24
Finished Jan 14 01:14:53 PM PST 24
Peak memory 202440 kb
Host smart-837fd6db-1ced-456a-be7e-4b70dd9c2644
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115086142 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 9.sram_ctrl_tl_intg_err.115086142
Directory /workspace/9.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.sram_ctrl_access_during_key_req.215365192
Short name T823
Test name
Test status
Simulation time 20741450882 ps
CPU time 1228.63 seconds
Started Jan 14 02:11:34 PM PST 24
Finished Jan 14 02:32:08 PM PST 24
Peak memory 380220 kb
Host smart-2e65828e-7090-4e59-bcbb-46db61a16056
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215365192 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 0.sram_ctrl_access_during_key_req.215365192
Directory /workspace/0.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/0.sram_ctrl_alert_test.3755769540
Short name T644
Test name
Test status
Simulation time 13724324 ps
CPU time 0.65 seconds
Started Jan 14 02:11:48 PM PST 24
Finished Jan 14 02:11:50 PM PST 24
Peak memory 201508 kb
Host smart-ab26bf62-efe0-441a-8087-9b3c672e9d76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755769540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.sram_ctrl_alert_test.3755769540
Directory /workspace/0.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.sram_ctrl_bijection.1825434626
Short name T691
Test name
Test status
Simulation time 71315134776 ps
CPU time 1188.99 seconds
Started Jan 14 02:11:26 PM PST 24
Finished Jan 14 02:31:16 PM PST 24
Peak memory 202120 kb
Host smart-38018fd6-4abb-4cd1-9a47-9f539417b463
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825434626 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection.
1825434626
Directory /workspace/0.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/0.sram_ctrl_lc_escalation.2635486638
Short name T374
Test name
Test status
Simulation time 25222924626 ps
CPU time 70.38 seconds
Started Jan 14 02:11:36 PM PST 24
Finished Jan 14 02:12:50 PM PST 24
Peak memory 202208 kb
Host smart-f82f45c9-997d-459f-9f77-9301d0910b79
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635486638 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_lc_esc
alation.2635486638
Directory /workspace/0.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/0.sram_ctrl_max_throughput.3448272411
Short name T271
Test name
Test status
Simulation time 2834148608 ps
CPU time 54.2 seconds
Started Jan 14 02:11:32 PM PST 24
Finished Jan 14 02:12:27 PM PST 24
Peak memory 274552 kb
Host smart-af509c30-7a73-4641-8bb7-eac6b07a5e55
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448272411 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 0.sram_ctrl_max_throughput.3448272411
Directory /workspace/0.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/0.sram_ctrl_mem_partial_access.1806981506
Short name T792
Test name
Test status
Simulation time 2449273512 ps
CPU time 82.01 seconds
Started Jan 14 02:11:40 PM PST 24
Finished Jan 14 02:13:06 PM PST 24
Peak memory 211112 kb
Host smart-09bcd92f-bc91-41ae-a329-dbf75c4db3b7
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806981506 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.sram_ctrl_mem_partial_access.1806981506
Directory /workspace/0.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/0.sram_ctrl_mem_walk.1624630901
Short name T223
Test name
Test status
Simulation time 15159129472 ps
CPU time 252.02 seconds
Started Jan 14 02:11:41 PM PST 24
Finished Jan 14 02:15:57 PM PST 24
Peak memory 202248 kb
Host smart-187f922a-b0f1-4d29-a5a2-8339c99c2697
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624630901 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl
_mem_walk.1624630901
Directory /workspace/0.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/0.sram_ctrl_multiple_keys.1972030547
Short name T541
Test name
Test status
Simulation time 17030454103 ps
CPU time 1487.16 seconds
Started Jan 14 02:11:24 PM PST 24
Finished Jan 14 02:36:13 PM PST 24
Peak memory 380116 kb
Host smart-7b866ef6-caec-4bb6-af46-8f540babbd2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972030547 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multip
le_keys.1972030547
Directory /workspace/0.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/0.sram_ctrl_partial_access.3211309676
Short name T761
Test name
Test status
Simulation time 523884318 ps
CPU time 153 seconds
Started Jan 14 02:11:35 PM PST 24
Finished Jan 14 02:14:13 PM PST 24
Peak memory 365568 kb
Host smart-1b583101-fa9b-4a21-96a4-1aab0cd4322d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211309676 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.s
ram_ctrl_partial_access.3211309676
Directory /workspace/0.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.1801278615
Short name T512
Test name
Test status
Simulation time 121292458252 ps
CPU time 475.63 seconds
Started Jan 14 02:11:35 PM PST 24
Finished Jan 14 02:19:36 PM PST 24
Peak memory 202172 kb
Host smart-c5e4a38e-f22d-4858-b39d-f56962151092
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801278615 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 0.sram_ctrl_partial_access_b2b.1801278615
Directory /workspace/0.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/0.sram_ctrl_ram_cfg.3585101261
Short name T234
Test name
Test status
Simulation time 681734144 ps
CPU time 5.99 seconds
Started Jan 14 02:11:42 PM PST 24
Finished Jan 14 02:11:51 PM PST 24
Peak memory 202432 kb
Host smart-b4413448-6848-453c-b0cb-b1f9e5d56986
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585101261 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.3585101261
Directory /workspace/0.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/0.sram_ctrl_regwen.1535826770
Short name T535
Test name
Test status
Simulation time 10467360991 ps
CPU time 843.37 seconds
Started Jan 14 02:11:43 PM PST 24
Finished Jan 14 02:25:49 PM PST 24
Peak memory 363592 kb
Host smart-ab0480a2-6bcc-47ba-8765-02a0e503f063
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535826770 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.1535826770
Directory /workspace/0.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/0.sram_ctrl_sec_cm.4174901337
Short name T24
Test name
Test status
Simulation time 340747980 ps
CPU time 1.9 seconds
Started Jan 14 02:11:53 PM PST 24
Finished Jan 14 02:11:56 PM PST 24
Peak memory 220992 kb
Host smart-51855f18-22e1-459f-93af-5f7ad5345fb6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174901337 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.sram_ctrl_sec_cm.4174901337
Directory /workspace/0.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.sram_ctrl_smoke.2778431597
Short name T588
Test name
Test status
Simulation time 995163642 ps
CPU time 164.97 seconds
Started Jan 14 02:11:24 PM PST 24
Finished Jan 14 02:14:10 PM PST 24
Peak memory 371792 kb
Host smart-a66445cf-32f6-4ffc-9125-4b6545226856
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778431597 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.2778431597
Directory /workspace/0.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/0.sram_ctrl_stress_all.247721098
Short name T109
Test name
Test status
Simulation time 273906227417 ps
CPU time 6252.49 seconds
Started Jan 14 02:11:48 PM PST 24
Finished Jan 14 03:56:02 PM PST 24
Peak memory 380200 kb
Host smart-13c27864-b896-481e-b98f-840bfa92225a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247721098 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 0.sram_ctrl_stress_all.247721098
Directory /workspace/0.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.4145303275
Short name T240
Test name
Test status
Simulation time 3970883055 ps
CPU time 3151.73 seconds
Started Jan 14 02:11:48 PM PST 24
Finished Jan 14 03:04:21 PM PST 24
Peak memory 461660 kb
Host smart-3d80a087-9455-4950-a297-1204b9973527
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4145303275 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all_with_rand_reset.4145303275
Directory /workspace/0.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.sram_ctrl_stress_pipeline.2029177254
Short name T983
Test name
Test status
Simulation time 5187661313 ps
CPU time 477.78 seconds
Started Jan 14 02:11:26 PM PST 24
Finished Jan 14 02:19:25 PM PST 24
Peak memory 202128 kb
Host smart-b6ff056d-d242-4568-bc29-6916762c739c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029177254 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.sram_ctrl_stress_pipeline.2029177254
Directory /workspace/0.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.2726829497
Short name T421
Test name
Test status
Simulation time 765848655 ps
CPU time 111.62 seconds
Started Jan 14 02:11:34 PM PST 24
Finished Jan 14 02:13:31 PM PST 24
Peak memory 323800 kb
Host smart-c6dab0a5-023a-447e-bace-aff883ad44b3
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726829497 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.sram_ctrl_throughput_w_partial_write.2726829497
Directory /workspace/0.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/1.sram_ctrl_access_during_key_req.2450691705
Short name T669
Test name
Test status
Simulation time 15225806241 ps
CPU time 935.42 seconds
Started Jan 14 02:12:13 PM PST 24
Finished Jan 14 02:27:50 PM PST 24
Peak memory 380176 kb
Host smart-f864ccd5-6986-4c45-9470-3e869c9455b7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450691705 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.sram_ctrl_access_during_key_req.2450691705
Directory /workspace/1.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/1.sram_ctrl_alert_test.4111011701
Short name T793
Test name
Test status
Simulation time 14875269 ps
CPU time 0.64 seconds
Started Jan 14 02:12:44 PM PST 24
Finished Jan 14 02:12:46 PM PST 24
Peak memory 201440 kb
Host smart-8af0adc3-52e2-4025-b274-5e67789743cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111011701 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.sram_ctrl_alert_test.4111011701
Directory /workspace/1.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.sram_ctrl_bijection.2693176562
Short name T363
Test name
Test status
Simulation time 504125916145 ps
CPU time 2601.07 seconds
Started Jan 14 02:11:59 PM PST 24
Finished Jan 14 02:55:21 PM PST 24
Peak memory 202176 kb
Host smart-d89d4b1c-844e-4b4d-b2d8-8908c87a4d4d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693176562 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection.
2693176562
Directory /workspace/1.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/1.sram_ctrl_max_throughput.1936629350
Short name T633
Test name
Test status
Simulation time 6335885204 ps
CPU time 42.18 seconds
Started Jan 14 02:12:12 PM PST 24
Finished Jan 14 02:12:55 PM PST 24
Peak memory 252320 kb
Host smart-43220a91-bad9-4ed0-a74b-c26473a62887
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936629350 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.sram_ctrl_max_throughput.1936629350
Directory /workspace/1.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/1.sram_ctrl_mem_partial_access.3340131883
Short name T376
Test name
Test status
Simulation time 7253649231 ps
CPU time 81.77 seconds
Started Jan 14 02:12:34 PM PST 24
Finished Jan 14 02:13:57 PM PST 24
Peak memory 211452 kb
Host smart-4eed9ef6-2360-48aa-bd73-8cbe4b103c42
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340131883 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.sram_ctrl_mem_partial_access.3340131883
Directory /workspace/1.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/1.sram_ctrl_mem_walk.1713644840
Short name T712
Test name
Test status
Simulation time 20877959991 ps
CPU time 320.41 seconds
Started Jan 14 02:12:20 PM PST 24
Finished Jan 14 02:17:42 PM PST 24
Peak memory 202212 kb
Host smart-c5cdff17-fac4-4951-b06f-9b3cd02d292a
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713644840 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl
_mem_walk.1713644840
Directory /workspace/1.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/1.sram_ctrl_multiple_keys.3296537836
Short name T565
Test name
Test status
Simulation time 4409931370 ps
CPU time 500.6 seconds
Started Jan 14 02:11:47 PM PST 24
Finished Jan 14 02:20:09 PM PST 24
Peak memory 375992 kb
Host smart-8123bb98-038d-4dd6-a532-52796977d4b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296537836 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multip
le_keys.3296537836
Directory /workspace/1.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/1.sram_ctrl_partial_access.2029714184
Short name T364
Test name
Test status
Simulation time 2323859674 ps
CPU time 20.4 seconds
Started Jan 14 02:12:05 PM PST 24
Finished Jan 14 02:12:27 PM PST 24
Peak memory 202172 kb
Host smart-c6109b60-223f-41aa-b38c-c0bfdef89591
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029714184 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.s
ram_ctrl_partial_access.2029714184
Directory /workspace/1.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.3692510081
Short name T703
Test name
Test status
Simulation time 12259425396 ps
CPU time 203.04 seconds
Started Jan 14 02:12:13 PM PST 24
Finished Jan 14 02:15:37 PM PST 24
Peak memory 202176 kb
Host smart-791e91e0-fe74-4a0e-89e0-06f2261b8f48
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692510081 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 1.sram_ctrl_partial_access_b2b.3692510081
Directory /workspace/1.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/1.sram_ctrl_ram_cfg.2255410620
Short name T139
Test name
Test status
Simulation time 661195685 ps
CPU time 13.2 seconds
Started Jan 14 02:12:20 PM PST 24
Finished Jan 14 02:12:34 PM PST 24
Peak memory 202336 kb
Host smart-cd9a18ac-07ea-4d0b-b5c9-3902855fac1d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255410620 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.2255410620
Directory /workspace/1.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/1.sram_ctrl_regwen.3608574759
Short name T813
Test name
Test status
Simulation time 80213538722 ps
CPU time 1222.44 seconds
Started Jan 14 02:12:12 PM PST 24
Finished Jan 14 02:32:36 PM PST 24
Peak memory 360668 kb
Host smart-88fe65dc-a4b0-4096-bc2b-c946ae2e6efe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608574759 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.3608574759
Directory /workspace/1.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/1.sram_ctrl_smoke.2883293972
Short name T719
Test name
Test status
Simulation time 4370085023 ps
CPU time 86.18 seconds
Started Jan 14 02:11:58 PM PST 24
Finished Jan 14 02:13:25 PM PST 24
Peak memory 319652 kb
Host smart-330e1c8f-6100-455f-a0f6-ecd017fcab32
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883293972 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.2883293972
Directory /workspace/1.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.3005611929
Short name T866
Test name
Test status
Simulation time 710582424 ps
CPU time 5021.9 seconds
Started Jan 14 02:12:45 PM PST 24
Finished Jan 14 03:36:29 PM PST 24
Peak memory 772732 kb
Host smart-dd181b43-00c0-414c-b4f0-63415d58cef9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3005611929 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all_with_rand_reset.3005611929
Directory /workspace/1.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.sram_ctrl_stress_pipeline.3343236980
Short name T330
Test name
Test status
Simulation time 10401537581 ps
CPU time 181.56 seconds
Started Jan 14 02:11:58 PM PST 24
Finished Jan 14 02:15:00 PM PST 24
Peak memory 202180 kb
Host smart-8475dfba-1803-4394-998e-279d9f033c29
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343236980 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.sram_ctrl_stress_pipeline.3343236980
Directory /workspace/1.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.1623815607
Short name T739
Test name
Test status
Simulation time 6007701840 ps
CPU time 51.88 seconds
Started Jan 14 02:12:12 PM PST 24
Finished Jan 14 02:13:05 PM PST 24
Peak memory 274572 kb
Host smart-d8b2fe1d-2393-43ff-948d-09d21522d959
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623815607 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.sram_ctrl_throughput_w_partial_write.1623815607
Directory /workspace/1.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/10.sram_ctrl_access_during_key_req.2646871106
Short name T262
Test name
Test status
Simulation time 15003196112 ps
CPU time 1349.6 seconds
Started Jan 14 02:17:18 PM PST 24
Finished Jan 14 02:39:48 PM PST 24
Peak memory 374716 kb
Host smart-debf1d01-613f-484a-8dbe-68aef23d1828
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646871106 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 10.sram_ctrl_access_during_key_req.2646871106
Directory /workspace/10.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/10.sram_ctrl_alert_test.1358941664
Short name T596
Test name
Test status
Simulation time 21203390 ps
CPU time 0.66 seconds
Started Jan 14 02:17:32 PM PST 24
Finished Jan 14 02:17:34 PM PST 24
Peak memory 201460 kb
Host smart-1ae1935e-61fa-498e-8c2f-0eafcbb8b016
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358941664 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.sram_ctrl_alert_test.1358941664
Directory /workspace/10.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.sram_ctrl_bijection.1988723647
Short name T616
Test name
Test status
Simulation time 406623084358 ps
CPU time 1986.05 seconds
Started Jan 14 02:17:09 PM PST 24
Finished Jan 14 02:50:19 PM PST 24
Peak memory 202156 kb
Host smart-e9f32bdc-117c-4271-b1a9-219e09510e51
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988723647 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection
.1988723647
Directory /workspace/10.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/10.sram_ctrl_executable.567160701
Short name T281
Test name
Test status
Simulation time 60389648775 ps
CPU time 642.16 seconds
Started Jan 14 02:17:18 PM PST 24
Finished Jan 14 02:28:01 PM PST 24
Peak memory 379096 kb
Host smart-520a5652-8b88-49d0-a98d-a23ebfd9c5c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567160701 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executabl
e.567160701
Directory /workspace/10.sram_ctrl_executable/latest

Test location /workspace/coverage/default/10.sram_ctrl_lc_escalation.53622164
Short name T664
Test name
Test status
Simulation time 3931683711 ps
CPU time 49.02 seconds
Started Jan 14 02:17:19 PM PST 24
Finished Jan 14 02:18:08 PM PST 24
Peak memory 210332 kb
Host smart-145a2b74-9004-4d10-8f79-12a4e7f73f18
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53622164 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_esc
alation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_esca
lation.53622164
Directory /workspace/10.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/10.sram_ctrl_max_throughput.2394215989
Short name T509
Test name
Test status
Simulation time 5453783271 ps
CPU time 171.69 seconds
Started Jan 14 02:17:19 PM PST 24
Finished Jan 14 02:20:11 PM PST 24
Peak memory 365700 kb
Host smart-7fa54808-bf6a-401a-a54c-f93edef6a4e5
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394215989 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 10.sram_ctrl_max_throughput.2394215989
Directory /workspace/10.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/10.sram_ctrl_mem_partial_access.898760158
Short name T314
Test name
Test status
Simulation time 1557925867 ps
CPU time 143.91 seconds
Started Jan 14 02:17:26 PM PST 24
Finished Jan 14 02:19:51 PM PST 24
Peak memory 211060 kb
Host smart-b3d59561-9dd4-4c70-a42b-197c15a18bbe
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898760158 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.sram_ctrl_mem_partial_access.898760158
Directory /workspace/10.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/10.sram_ctrl_mem_walk.4254474052
Short name T559
Test name
Test status
Simulation time 7903382135 ps
CPU time 135.93 seconds
Started Jan 14 02:17:25 PM PST 24
Finished Jan 14 02:19:42 PM PST 24
Peak memory 202280 kb
Host smart-fa6f4eb8-c09f-4321-bd0b-4c045f364bca
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254474052 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctr
l_mem_walk.4254474052
Directory /workspace/10.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/10.sram_ctrl_multiple_keys.3258811296
Short name T830
Test name
Test status
Simulation time 1166626665 ps
CPU time 56.46 seconds
Started Jan 14 02:17:04 PM PST 24
Finished Jan 14 02:18:03 PM PST 24
Peak memory 202140 kb
Host smart-725c6469-b8eb-458f-85d4-69bc31ba1753
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258811296 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multi
ple_keys.3258811296
Directory /workspace/10.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/10.sram_ctrl_partial_access.2352341088
Short name T779
Test name
Test status
Simulation time 1701821561 ps
CPU time 14.45 seconds
Started Jan 14 02:17:19 PM PST 24
Finished Jan 14 02:17:34 PM PST 24
Peak memory 210268 kb
Host smart-d8dda255-fcc0-40d1-8555-e5e816fbfa6a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352341088 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
sram_ctrl_partial_access.2352341088
Directory /workspace/10.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.1688917454
Short name T263
Test name
Test status
Simulation time 6899749698 ps
CPU time 463.54 seconds
Started Jan 14 02:17:15 PM PST 24
Finished Jan 14 02:25:00 PM PST 24
Peak memory 202184 kb
Host smart-50905644-6442-4b86-9cd9-e93d2e7b17b4
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688917454 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 10.sram_ctrl_partial_access_b2b.1688917454
Directory /workspace/10.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/10.sram_ctrl_ram_cfg.3478371582
Short name T724
Test name
Test status
Simulation time 349737970 ps
CPU time 6.83 seconds
Started Jan 14 02:17:27 PM PST 24
Finished Jan 14 02:17:35 PM PST 24
Peak memory 202460 kb
Host smart-32386424-df53-4258-a45e-fa8353300dac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478371582 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.3478371582
Directory /workspace/10.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/10.sram_ctrl_regwen.1735343258
Short name T388
Test name
Test status
Simulation time 3253579802 ps
CPU time 904.19 seconds
Started Jan 14 02:17:27 PM PST 24
Finished Jan 14 02:32:32 PM PST 24
Peak memory 369928 kb
Host smart-18dc7148-8884-4934-9bba-77df00fd4bf8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735343258 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.1735343258
Directory /workspace/10.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/10.sram_ctrl_smoke.2308588634
Short name T921
Test name
Test status
Simulation time 2144534127 ps
CPU time 25.47 seconds
Started Jan 14 02:17:05 PM PST 24
Finished Jan 14 02:17:36 PM PST 24
Peak memory 202088 kb
Host smart-5754cb3e-6000-44eb-81c9-d90eff9ee68d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308588634 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.2308588634
Directory /workspace/10.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.1945912860
Short name T506
Test name
Test status
Simulation time 2950389513 ps
CPU time 6280.11 seconds
Started Jan 14 02:17:34 PM PST 24
Finished Jan 14 04:02:15 PM PST 24
Peak memory 671632 kb
Host smart-3a317b27-fe71-4239-a3ee-425feef4fd11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1945912860 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all_with_rand_reset.1945912860
Directory /workspace/10.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.sram_ctrl_stress_pipeline.1947832807
Short name T781
Test name
Test status
Simulation time 5189394730 ps
CPU time 261.76 seconds
Started Jan 14 02:17:05 PM PST 24
Finished Jan 14 02:21:33 PM PST 24
Peak memory 202180 kb
Host smart-446c98b1-9844-4744-badf-6e8e1f35a0d0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947832807 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.sram_ctrl_stress_pipeline.1947832807
Directory /workspace/10.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.1332942341
Short name T863
Test name
Test status
Simulation time 3117572227 ps
CPU time 207.39 seconds
Started Jan 14 02:17:21 PM PST 24
Finished Jan 14 02:20:49 PM PST 24
Peak memory 366584 kb
Host smart-e6d5df17-dd9b-4427-ba91-16962c2771f4
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332942341 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.sram_ctrl_throughput_w_partial_write.1332942341
Directory /workspace/10.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/11.sram_ctrl_access_during_key_req.2558813762
Short name T839
Test name
Test status
Simulation time 8222398952 ps
CPU time 601.83 seconds
Started Jan 14 02:17:58 PM PST 24
Finished Jan 14 02:28:00 PM PST 24
Peak memory 372972 kb
Host smart-a9ac16c4-4b61-4e85-9524-7b11ae966d21
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558813762 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.sram_ctrl_access_during_key_req.2558813762
Directory /workspace/11.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/11.sram_ctrl_alert_test.115223590
Short name T693
Test name
Test status
Simulation time 14761542 ps
CPU time 0.64 seconds
Started Jan 14 02:18:06 PM PST 24
Finished Jan 14 02:18:07 PM PST 24
Peak memory 201892 kb
Host smart-8db5b27c-dda2-4511-b815-ad55ca89b4ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115223590 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.sram_ctrl_alert_test.115223590
Directory /workspace/11.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.sram_ctrl_bijection.1649230610
Short name T397
Test name
Test status
Simulation time 69471755736 ps
CPU time 572.03 seconds
Started Jan 14 02:17:42 PM PST 24
Finished Jan 14 02:27:14 PM PST 24
Peak memory 202180 kb
Host smart-93eb2f44-a021-4c7b-9f2d-ce14c068ea62
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649230610 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection
.1649230610
Directory /workspace/11.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/11.sram_ctrl_executable.4110479469
Short name T35
Test name
Test status
Simulation time 27224337284 ps
CPU time 906.33 seconds
Started Jan 14 02:17:59 PM PST 24
Finished Jan 14 02:33:06 PM PST 24
Peak memory 376988 kb
Host smart-3491faf1-0722-4835-97b4-51f99cd69954
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110479469 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_executab
le.4110479469
Directory /workspace/11.sram_ctrl_executable/latest

Test location /workspace/coverage/default/11.sram_ctrl_max_throughput.1210097582
Short name T253
Test name
Test status
Simulation time 3040508087 ps
CPU time 145.08 seconds
Started Jan 14 02:17:42 PM PST 24
Finished Jan 14 02:20:07 PM PST 24
Peak memory 358632 kb
Host smart-72db78e1-7ccf-4e20-898a-680bce4642c3
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210097582 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 11.sram_ctrl_max_throughput.1210097582
Directory /workspace/11.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/11.sram_ctrl_mem_partial_access.2368626307
Short name T607
Test name
Test status
Simulation time 3230568595 ps
CPU time 146.14 seconds
Started Jan 14 02:18:05 PM PST 24
Finished Jan 14 02:20:32 PM PST 24
Peak memory 211236 kb
Host smart-522e78c2-1c12-492c-bb80-2654357b85dc
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368626307 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.sram_ctrl_mem_partial_access.2368626307
Directory /workspace/11.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/11.sram_ctrl_mem_walk.3581037346
Short name T14
Test name
Test status
Simulation time 21522295566 ps
CPU time 155.37 seconds
Started Jan 14 02:17:59 PM PST 24
Finished Jan 14 02:20:35 PM PST 24
Peak memory 202176 kb
Host smart-88093ca6-68b9-4d96-8310-84f46b079a58
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581037346 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctr
l_mem_walk.3581037346
Directory /workspace/11.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/11.sram_ctrl_multiple_keys.3134591545
Short name T592
Test name
Test status
Simulation time 45254898568 ps
CPU time 978.86 seconds
Started Jan 14 02:17:35 PM PST 24
Finished Jan 14 02:33:55 PM PST 24
Peak memory 369916 kb
Host smart-5598d341-9156-4be2-8c03-68bfbb1e1b15
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134591545 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multi
ple_keys.3134591545
Directory /workspace/11.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/11.sram_ctrl_partial_access.1535412198
Short name T283
Test name
Test status
Simulation time 10678522235 ps
CPU time 56.42 seconds
Started Jan 14 02:17:43 PM PST 24
Finished Jan 14 02:18:40 PM PST 24
Peak memory 274348 kb
Host smart-77a225af-3e15-41e0-9266-4358f460506f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535412198 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
sram_ctrl_partial_access.1535412198
Directory /workspace/11.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.387487224
Short name T946
Test name
Test status
Simulation time 9942603580 ps
CPU time 432.54 seconds
Started Jan 14 02:17:43 PM PST 24
Finished Jan 14 02:24:57 PM PST 24
Peak memory 202192 kb
Host smart-c6438e09-6896-4860-9134-d235ae045e5d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387487224 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.sram_ctrl_partial_access_b2b.387487224
Directory /workspace/11.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/11.sram_ctrl_ram_cfg.3495446632
Short name T446
Test name
Test status
Simulation time 1400667190 ps
CPU time 6.94 seconds
Started Jan 14 02:17:56 PM PST 24
Finished Jan 14 02:18:04 PM PST 24
Peak memory 202428 kb
Host smart-e9ad049f-b476-4fbf-9aa2-8cd5db27905d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495446632 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.3495446632
Directory /workspace/11.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/11.sram_ctrl_regwen.4140711199
Short name T783
Test name
Test status
Simulation time 2987948136 ps
CPU time 315.92 seconds
Started Jan 14 02:17:57 PM PST 24
Finished Jan 14 02:23:14 PM PST 24
Peak memory 365760 kb
Host smart-5b51a7ca-16f6-4b14-9107-ddd6caa6bd18
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140711199 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.4140711199
Directory /workspace/11.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/11.sram_ctrl_smoke.4094902438
Short name T488
Test name
Test status
Simulation time 13886934879 ps
CPU time 32.32 seconds
Started Jan 14 02:17:35 PM PST 24
Finished Jan 14 02:18:08 PM PST 24
Peak memory 202136 kb
Host smart-05075d6f-79e7-4d97-bed4-250cdbe0dd02
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094902438 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.4094902438
Directory /workspace/11.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.3377658373
Short name T238
Test name
Test status
Simulation time 522830934 ps
CPU time 2231.29 seconds
Started Jan 14 02:17:59 PM PST 24
Finished Jan 14 02:55:12 PM PST 24
Peak memory 539212 kb
Host smart-e8e8b71c-abe4-4f53-8819-57fca83e5c46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3377658373 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all_with_rand_reset.3377658373
Directory /workspace/11.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.sram_ctrl_stress_pipeline.433052927
Short name T925
Test name
Test status
Simulation time 4188040835 ps
CPU time 309.68 seconds
Started Jan 14 02:17:40 PM PST 24
Finished Jan 14 02:22:51 PM PST 24
Peak memory 202168 kb
Host smart-0c85beb1-ee46-43f2-9a15-88be0acc3556
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433052927 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.sram_ctrl_stress_pipeline.433052927
Directory /workspace/11.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.3206290302
Short name T787
Test name
Test status
Simulation time 706905221 ps
CPU time 28.97 seconds
Started Jan 14 02:17:56 PM PST 24
Finished Jan 14 02:18:26 PM PST 24
Peak memory 215868 kb
Host smart-edbdef0c-c03f-46a3-8cc6-e3ba63a3fa73
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206290302 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.sram_ctrl_throughput_w_partial_write.3206290302
Directory /workspace/11.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/12.sram_ctrl_access_during_key_req.3813124497
Short name T889
Test name
Test status
Simulation time 4315825465 ps
CPU time 718.94 seconds
Started Jan 14 02:18:23 PM PST 24
Finished Jan 14 02:30:22 PM PST 24
Peak memory 377124 kb
Host smart-a8956f67-61b9-4010-bd6e-2b30f36fb030
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813124497 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 12.sram_ctrl_access_during_key_req.3813124497
Directory /workspace/12.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/12.sram_ctrl_alert_test.1342045485
Short name T385
Test name
Test status
Simulation time 15501859 ps
CPU time 0.67 seconds
Started Jan 14 02:18:26 PM PST 24
Finished Jan 14 02:18:27 PM PST 24
Peak memory 201868 kb
Host smart-f11438ed-67dd-4e90-9264-821cf5c83cd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342045485 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.sram_ctrl_alert_test.1342045485
Directory /workspace/12.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.sram_ctrl_bijection.2564331440
Short name T603
Test name
Test status
Simulation time 119811145243 ps
CPU time 2515.4 seconds
Started Jan 14 02:18:13 PM PST 24
Finished Jan 14 03:00:10 PM PST 24
Peak memory 202172 kb
Host smart-87ed90fc-e6d2-463f-a6a7-394348e9bf26
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564331440 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection
.2564331440
Directory /workspace/12.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/12.sram_ctrl_lc_escalation.3582562881
Short name T600
Test name
Test status
Simulation time 44067026536 ps
CPU time 227.29 seconds
Started Jan 14 02:18:25 PM PST 24
Finished Jan 14 02:22:13 PM PST 24
Peak memory 210464 kb
Host smart-3441d481-bb43-494f-8316-2c847fa23500
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582562881 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_es
calation.3582562881
Directory /workspace/12.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/12.sram_ctrl_max_throughput.1979495488
Short name T795
Test name
Test status
Simulation time 773177125 ps
CPU time 93.75 seconds
Started Jan 14 02:18:15 PM PST 24
Finished Jan 14 02:19:49 PM PST 24
Peak memory 329920 kb
Host smart-68fa39f8-7d2c-4883-8dc3-949fb3b4edbe
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979495488 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 12.sram_ctrl_max_throughput.1979495488
Directory /workspace/12.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/12.sram_ctrl_mem_partial_access.947461713
Short name T87
Test name
Test status
Simulation time 1665826125 ps
CPU time 132.19 seconds
Started Jan 14 02:18:22 PM PST 24
Finished Jan 14 02:20:35 PM PST 24
Peak memory 211116 kb
Host smart-0d974b4a-90a1-4f78-86bb-274c8beb8de1
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947461713 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.sram_ctrl_mem_partial_access.947461713
Directory /workspace/12.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/12.sram_ctrl_mem_walk.4215012917
Short name T408
Test name
Test status
Simulation time 10414705740 ps
CPU time 155.64 seconds
Started Jan 14 02:18:26 PM PST 24
Finished Jan 14 02:21:02 PM PST 24
Peak memory 202336 kb
Host smart-02dfa8cb-c192-40ee-96b5-601a8614fbcd
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215012917 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctr
l_mem_walk.4215012917
Directory /workspace/12.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/12.sram_ctrl_multiple_keys.3146345719
Short name T230
Test name
Test status
Simulation time 99809394083 ps
CPU time 1534.88 seconds
Started Jan 14 02:18:11 PM PST 24
Finished Jan 14 02:43:46 PM PST 24
Peak memory 379176 kb
Host smart-2e3978ba-470e-4651-95a8-252583241bd9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146345719 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multi
ple_keys.3146345719
Directory /workspace/12.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/12.sram_ctrl_partial_access.4114051958
Short name T727
Test name
Test status
Simulation time 4988276503 ps
CPU time 26.22 seconds
Started Jan 14 02:18:14 PM PST 24
Finished Jan 14 02:18:41 PM PST 24
Peak memory 202092 kb
Host smart-1583d658-f969-411c-86c4-f7921d16ecd8
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114051958 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
sram_ctrl_partial_access.4114051958
Directory /workspace/12.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.1854168370
Short name T805
Test name
Test status
Simulation time 6178531552 ps
CPU time 374.86 seconds
Started Jan 14 02:18:16 PM PST 24
Finished Jan 14 02:24:32 PM PST 24
Peak memory 202180 kb
Host smart-296aaada-5441-45b4-b04b-646d47fe0d43
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854168370 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 12.sram_ctrl_partial_access_b2b.1854168370
Directory /workspace/12.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/12.sram_ctrl_ram_cfg.235380099
Short name T463
Test name
Test status
Simulation time 654113401 ps
CPU time 6.53 seconds
Started Jan 14 02:18:23 PM PST 24
Finished Jan 14 02:18:30 PM PST 24
Peak memory 202332 kb
Host smart-e590038f-93a8-492b-9587-1dbb50036294
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235380099 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.235380099
Directory /workspace/12.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/12.sram_ctrl_regwen.921077891
Short name T387
Test name
Test status
Simulation time 70447683933 ps
CPU time 966.35 seconds
Started Jan 14 02:18:25 PM PST 24
Finished Jan 14 02:34:32 PM PST 24
Peak memory 377024 kb
Host smart-d90e8806-634d-458d-a6e4-767fb9c4bd5d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921077891 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.921077891
Directory /workspace/12.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/12.sram_ctrl_smoke.2334445882
Short name T716
Test name
Test status
Simulation time 1040835914 ps
CPU time 26.82 seconds
Started Jan 14 02:18:12 PM PST 24
Finished Jan 14 02:18:40 PM PST 24
Peak memory 210292 kb
Host smart-be2c88e8-6442-4a13-8292-e4acd0f7a505
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334445882 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.2334445882
Directory /workspace/12.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/12.sram_ctrl_stress_all.3752578457
Short name T756
Test name
Test status
Simulation time 201603584648 ps
CPU time 6858.32 seconds
Started Jan 14 02:18:22 PM PST 24
Finished Jan 14 04:12:42 PM PST 24
Peak memory 387352 kb
Host smart-b6e4a73b-0f0c-4dc8-bbe5-44c68e2fef5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752578457 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 12.sram_ctrl_stress_all.3752578457
Directory /workspace/12.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.314901353
Short name T486
Test name
Test status
Simulation time 8431881194 ps
CPU time 5099.55 seconds
Started Jan 14 02:18:22 PM PST 24
Finished Jan 14 03:43:23 PM PST 24
Peak memory 654312 kb
Host smart-e9038146-d70b-4c80-8217-164397c9467c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=314901353 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all_with_rand_reset.314901353
Directory /workspace/12.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.sram_ctrl_stress_pipeline.1598591635
Short name T804
Test name
Test status
Simulation time 3825168190 ps
CPU time 288.05 seconds
Started Jan 14 02:18:12 PM PST 24
Finished Jan 14 02:23:01 PM PST 24
Peak memory 202168 kb
Host smart-5fb464e3-e0b1-43de-8cb6-601849724542
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598591635 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.sram_ctrl_stress_pipeline.1598591635
Directory /workspace/12.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.2594361797
Short name T381
Test name
Test status
Simulation time 753532621 ps
CPU time 77.35 seconds
Started Jan 14 02:18:24 PM PST 24
Finished Jan 14 02:19:41 PM PST 24
Peak memory 300356 kb
Host smart-65381d12-ea45-4a37-ab82-d86484c8fb34
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594361797 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.sram_ctrl_throughput_w_partial_write.2594361797
Directory /workspace/12.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/13.sram_ctrl_access_during_key_req.1175048045
Short name T591
Test name
Test status
Simulation time 92948504828 ps
CPU time 1629.08 seconds
Started Jan 14 02:18:51 PM PST 24
Finished Jan 14 02:46:01 PM PST 24
Peak memory 380112 kb
Host smart-6127b3bc-a05c-4f74-8d89-a36eca5ee334
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175048045 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 13.sram_ctrl_access_during_key_req.1175048045
Directory /workspace/13.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/13.sram_ctrl_alert_test.58758971
Short name T461
Test name
Test status
Simulation time 82739863 ps
CPU time 0.66 seconds
Started Jan 14 02:18:54 PM PST 24
Finished Jan 14 02:18:55 PM PST 24
Peak memory 201892 kb
Host smart-34438f25-ece7-4a63-929d-1e440e96a7ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58758971 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.sram_ctrl_alert_test.58758971
Directory /workspace/13.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.sram_ctrl_bijection.4186823579
Short name T455
Test name
Test status
Simulation time 150375138929 ps
CPU time 1164.2 seconds
Started Jan 14 02:18:34 PM PST 24
Finished Jan 14 02:37:59 PM PST 24
Peak memory 202180 kb
Host smart-84309c79-f4ae-402e-96ba-097ee153b7d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186823579 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection
.4186823579
Directory /workspace/13.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/13.sram_ctrl_executable.2871211942
Short name T120
Test name
Test status
Simulation time 25275826041 ps
CPU time 1150.85 seconds
Started Jan 14 02:18:52 PM PST 24
Finished Jan 14 02:38:03 PM PST 24
Peak memory 367856 kb
Host smart-02120b04-c7fa-4822-bd1c-b0c16df43a21
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871211942 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_executab
le.2871211942
Directory /workspace/13.sram_ctrl_executable/latest

Test location /workspace/coverage/default/13.sram_ctrl_lc_escalation.2503882104
Short name T642
Test name
Test status
Simulation time 19190345232 ps
CPU time 78.31 seconds
Started Jan 14 02:18:53 PM PST 24
Finished Jan 14 02:20:12 PM PST 24
Peak memory 210400 kb
Host smart-52a9da1d-67ff-4f5d-865d-b3805d1eaca0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503882104 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_es
calation.2503882104
Directory /workspace/13.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/13.sram_ctrl_max_throughput.2980859403
Short name T747
Test name
Test status
Simulation time 721433865 ps
CPU time 27.56 seconds
Started Jan 14 02:18:46 PM PST 24
Finished Jan 14 02:19:14 PM PST 24
Peak memory 210376 kb
Host smart-aedb3d17-86bd-44ea-a890-3fcc7b3c8c83
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980859403 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 13.sram_ctrl_max_throughput.2980859403
Directory /workspace/13.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/13.sram_ctrl_mem_partial_access.3805965845
Short name T254
Test name
Test status
Simulation time 12903499936 ps
CPU time 145.57 seconds
Started Jan 14 02:18:53 PM PST 24
Finished Jan 14 02:21:19 PM PST 24
Peak memory 211496 kb
Host smart-f6a30714-18ab-4d8a-9d4f-df4f7f3bcf1d
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805965845 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.sram_ctrl_mem_partial_access.3805965845
Directory /workspace/13.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/13.sram_ctrl_mem_walk.725031038
Short name T910
Test name
Test status
Simulation time 10683869021 ps
CPU time 161.39 seconds
Started Jan 14 02:18:48 PM PST 24
Finished Jan 14 02:21:30 PM PST 24
Peak memory 202252 kb
Host smart-a3ddd338-b555-49a1-9efd-aeb8b8433e6a
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725031038 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl
_mem_walk.725031038
Directory /workspace/13.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/13.sram_ctrl_multiple_keys.627249281
Short name T474
Test name
Test status
Simulation time 4904729108 ps
CPU time 693.55 seconds
Started Jan 14 02:18:32 PM PST 24
Finished Jan 14 02:30:06 PM PST 24
Peak memory 377368 kb
Host smart-c6f0d1af-6f0b-4254-8393-2434254e0b66
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627249281 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multip
le_keys.627249281
Directory /workspace/13.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/13.sram_ctrl_partial_access.1348069291
Short name T796
Test name
Test status
Simulation time 420288736 ps
CPU time 7.17 seconds
Started Jan 14 02:18:45 PM PST 24
Finished Jan 14 02:18:53 PM PST 24
Peak memory 202096 kb
Host smart-afc8e446-d3ec-4647-9aec-4cbc45a36fab
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348069291 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
sram_ctrl_partial_access.1348069291
Directory /workspace/13.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.79864639
Short name T473
Test name
Test status
Simulation time 46002227358 ps
CPU time 306.94 seconds
Started Jan 14 02:18:46 PM PST 24
Finished Jan 14 02:23:54 PM PST 24
Peak memory 202048 kb
Host smart-ade76d8a-bce3-4001-aa11-2dfd814a2185
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79864639 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 13.sram_ctrl_partial_access_b2b.79864639
Directory /workspace/13.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/13.sram_ctrl_ram_cfg.3786741947
Short name T950
Test name
Test status
Simulation time 1342443840 ps
CPU time 14.4 seconds
Started Jan 14 02:18:53 PM PST 24
Finished Jan 14 02:19:08 PM PST 24
Peak memory 202468 kb
Host smart-59d7bf54-17f1-4905-8cab-c95a2bba8ffa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786741947 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.3786741947
Directory /workspace/13.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/13.sram_ctrl_regwen.2170112339
Short name T511
Test name
Test status
Simulation time 9027367149 ps
CPU time 502.75 seconds
Started Jan 14 02:18:48 PM PST 24
Finished Jan 14 02:27:11 PM PST 24
Peak memory 371480 kb
Host smart-29399210-eaab-4348-8790-df39fc604391
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170112339 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.2170112339
Directory /workspace/13.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/13.sram_ctrl_smoke.2326591440
Short name T683
Test name
Test status
Simulation time 919039072 ps
CPU time 118.43 seconds
Started Jan 14 02:18:38 PM PST 24
Finished Jan 14 02:20:37 PM PST 24
Peak memory 331896 kb
Host smart-1eb405f0-3e2a-42f0-beeb-fae1f6611907
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326591440 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.2326591440
Directory /workspace/13.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/13.sram_ctrl_stress_all.2541764340
Short name T542
Test name
Test status
Simulation time 1261577779117 ps
CPU time 5995.74 seconds
Started Jan 14 02:18:52 PM PST 24
Finished Jan 14 03:58:49 PM PST 24
Peak memory 374052 kb
Host smart-5a26d719-1f24-4d93-830b-2d8e1b38ebd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541764340 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 13.sram_ctrl_stress_all.2541764340
Directory /workspace/13.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.3367724443
Short name T525
Test name
Test status
Simulation time 972289388 ps
CPU time 2206.64 seconds
Started Jan 14 02:18:53 PM PST 24
Finished Jan 14 02:55:41 PM PST 24
Peak memory 389200 kb
Host smart-0885e57c-ef9d-4088-858c-a21b3ff0149a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3367724443 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all_with_rand_reset.3367724443
Directory /workspace/13.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.sram_ctrl_stress_pipeline.2587300687
Short name T647
Test name
Test status
Simulation time 8441406334 ps
CPU time 144.33 seconds
Started Jan 14 02:18:39 PM PST 24
Finished Jan 14 02:21:04 PM PST 24
Peak memory 202084 kb
Host smart-76bf1399-6dcd-4ad8-b66e-76bc23a3cea0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587300687 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.sram_ctrl_stress_pipeline.2587300687
Directory /workspace/13.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.653491603
Short name T881
Test name
Test status
Simulation time 1385995746 ps
CPU time 36.44 seconds
Started Jan 14 02:18:45 PM PST 24
Finished Jan 14 02:19:22 PM PST 24
Peak memory 236880 kb
Host smart-90900436-1fbd-4142-94cd-94a23fe55739
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653491603 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 13.sram_ctrl_throughput_w_partial_write.653491603
Directory /workspace/13.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/14.sram_ctrl_access_during_key_req.1939917524
Short name T620
Test name
Test status
Simulation time 28623886254 ps
CPU time 1076.71 seconds
Started Jan 14 02:19:19 PM PST 24
Finished Jan 14 02:37:17 PM PST 24
Peak memory 379016 kb
Host smart-20ba41dc-22a9-46b4-b7da-82333d066ef3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939917524 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.sram_ctrl_access_during_key_req.1939917524
Directory /workspace/14.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/14.sram_ctrl_alert_test.2795021690
Short name T855
Test name
Test status
Simulation time 19218227 ps
CPU time 0.63 seconds
Started Jan 14 02:19:33 PM PST 24
Finished Jan 14 02:19:37 PM PST 24
Peak memory 201472 kb
Host smart-edee16a6-f9cc-4099-8198-cd5c8347a0a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795021690 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.sram_ctrl_alert_test.2795021690
Directory /workspace/14.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.sram_ctrl_bijection.1446678158
Short name T10
Test name
Test status
Simulation time 30090723470 ps
CPU time 2054.15 seconds
Started Jan 14 02:19:02 PM PST 24
Finished Jan 14 02:53:17 PM PST 24
Peak memory 202136 kb
Host smart-a77991c1-61ae-432f-b21b-fa24e36e530c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446678158 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection
.1446678158
Directory /workspace/14.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/14.sram_ctrl_lc_escalation.2338014772
Short name T844
Test name
Test status
Simulation time 7377710232 ps
CPU time 175.58 seconds
Started Jan 14 02:19:17 PM PST 24
Finished Jan 14 02:22:16 PM PST 24
Peak memory 202276 kb
Host smart-204f0f73-7fba-43ae-83bf-f222bf9d3706
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338014772 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_es
calation.2338014772
Directory /workspace/14.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/14.sram_ctrl_max_throughput.384010285
Short name T769
Test name
Test status
Simulation time 790909446 ps
CPU time 88.35 seconds
Started Jan 14 02:19:18 PM PST 24
Finished Jan 14 02:20:48 PM PST 24
Peak memory 316616 kb
Host smart-65193077-6eb2-43f5-8b4e-a530dfcb6808
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384010285 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.sram_ctrl_max_throughput.384010285
Directory /workspace/14.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/14.sram_ctrl_mem_partial_access.1294214926
Short name T710
Test name
Test status
Simulation time 954296482 ps
CPU time 74.68 seconds
Started Jan 14 02:19:32 PM PST 24
Finished Jan 14 02:20:50 PM PST 24
Peak memory 211040 kb
Host smart-661a6163-0147-4dde-bdcb-8f71bd73a2fc
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294214926 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.sram_ctrl_mem_partial_access.1294214926
Directory /workspace/14.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/14.sram_ctrl_mem_walk.188532861
Short name T432
Test name
Test status
Simulation time 3468828390 ps
CPU time 126.25 seconds
Started Jan 14 02:19:28 PM PST 24
Finished Jan 14 02:21:38 PM PST 24
Peak memory 202148 kb
Host smart-f49b1ad6-68ce-4461-a362-39fafae23bf0
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188532861 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl
_mem_walk.188532861
Directory /workspace/14.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/14.sram_ctrl_multiple_keys.1269394859
Short name T612
Test name
Test status
Simulation time 28635477637 ps
CPU time 981.09 seconds
Started Jan 14 02:18:53 PM PST 24
Finished Jan 14 02:35:15 PM PST 24
Peak memory 380068 kb
Host smart-a3e7d187-2b32-45fa-bc03-80c57145cc47
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269394859 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multi
ple_keys.1269394859
Directory /workspace/14.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/14.sram_ctrl_partial_access.2692318437
Short name T287
Test name
Test status
Simulation time 1532350148 ps
CPU time 22.47 seconds
Started Jan 14 02:19:01 PM PST 24
Finished Jan 14 02:19:24 PM PST 24
Peak memory 236404 kb
Host smart-3eb07a2c-a254-4cf1-8bb0-f10bc341cc33
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692318437 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
sram_ctrl_partial_access.2692318437
Directory /workspace/14.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.3081486941
Short name T138
Test name
Test status
Simulation time 20251313104 ps
CPU time 254.65 seconds
Started Jan 14 02:19:01 PM PST 24
Finished Jan 14 02:23:16 PM PST 24
Peak memory 202152 kb
Host smart-d9f4cff4-2841-4bd8-b3b5-a3b5ad581ff5
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081486941 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 14.sram_ctrl_partial_access_b2b.3081486941
Directory /workspace/14.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/14.sram_ctrl_ram_cfg.3578862867
Short name T304
Test name
Test status
Simulation time 1347411947 ps
CPU time 14 seconds
Started Jan 14 02:19:33 PM PST 24
Finished Jan 14 02:19:50 PM PST 24
Peak memory 202424 kb
Host smart-3de6c1bb-c468-4738-9b2d-ce9ed2fdae12
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578862867 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.3578862867
Directory /workspace/14.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/14.sram_ctrl_regwen.1185264532
Short name T634
Test name
Test status
Simulation time 7597659624 ps
CPU time 241.75 seconds
Started Jan 14 02:19:18 PM PST 24
Finished Jan 14 02:23:22 PM PST 24
Peak memory 376800 kb
Host smart-54eb4f2b-fc65-4494-a5b6-2e075ba34b3f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185264532 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.1185264532
Directory /workspace/14.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/14.sram_ctrl_smoke.3507692615
Short name T666
Test name
Test status
Simulation time 947759121 ps
CPU time 16.39 seconds
Started Jan 14 02:18:55 PM PST 24
Finished Jan 14 02:19:12 PM PST 24
Peak memory 210296 kb
Host smart-ed895f1e-17fa-4459-b838-a008f57011c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507692615 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.3507692615
Directory /workspace/14.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/14.sram_ctrl_stress_all.775243222
Short name T728
Test name
Test status
Simulation time 39936006771 ps
CPU time 2233.97 seconds
Started Jan 14 02:19:33 PM PST 24
Finished Jan 14 02:56:50 PM PST 24
Peak memory 383184 kb
Host smart-0558d3b8-2524-48c4-9097-bfdc543df063
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775243222 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 14.sram_ctrl_stress_all.775243222
Directory /workspace/14.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.2905603411
Short name T870
Test name
Test status
Simulation time 819712863 ps
CPU time 3259.78 seconds
Started Jan 14 02:19:33 PM PST 24
Finished Jan 14 03:13:56 PM PST 24
Peak memory 418524 kb
Host smart-b9d8e475-61a6-47f9-9f41-0fd432379644
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2905603411 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all_with_rand_reset.2905603411
Directory /workspace/14.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.sram_ctrl_stress_pipeline.459341585
Short name T413
Test name
Test status
Simulation time 4831226961 ps
CPU time 346.73 seconds
Started Jan 14 02:19:01 PM PST 24
Finished Jan 14 02:24:48 PM PST 24
Peak memory 202168 kb
Host smart-74671b8d-c80d-4993-a28c-922e62a1b2bd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459341585 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.sram_ctrl_stress_pipeline.459341585
Directory /workspace/14.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.3545896751
Short name T701
Test name
Test status
Simulation time 2943141250 ps
CPU time 41.29 seconds
Started Jan 14 02:19:17 PM PST 24
Finished Jan 14 02:20:01 PM PST 24
Peak memory 256592 kb
Host smart-72196c5a-16a1-4388-b7f1-3d654f2786d1
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545896751 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 14.sram_ctrl_throughput_w_partial_write.3545896751
Directory /workspace/14.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/15.sram_ctrl_access_during_key_req.3312675032
Short name T309
Test name
Test status
Simulation time 16801986307 ps
CPU time 358.75 seconds
Started Jan 14 02:19:46 PM PST 24
Finished Jan 14 02:25:46 PM PST 24
Peak memory 321792 kb
Host smart-3dd7861a-db18-48bc-8e56-af24f74ba3d9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312675032 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 15.sram_ctrl_access_during_key_req.3312675032
Directory /workspace/15.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/15.sram_ctrl_alert_test.947643701
Short name T459
Test name
Test status
Simulation time 44615838 ps
CPU time 0.62 seconds
Started Jan 14 02:20:15 PM PST 24
Finished Jan 14 02:20:16 PM PST 24
Peak memory 201460 kb
Host smart-854ad584-2ac3-4629-82c9-294159a81229
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947643701 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.sram_ctrl_alert_test.947643701
Directory /workspace/15.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.sram_ctrl_bijection.682412277
Short name T256
Test name
Test status
Simulation time 94250104740 ps
CPU time 1600.22 seconds
Started Jan 14 02:19:32 PM PST 24
Finished Jan 14 02:46:16 PM PST 24
Peak memory 202160 kb
Host smart-88aa9d87-b964-4057-8e8d-acd891f8b704
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682412277 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection.
682412277
Directory /workspace/15.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/15.sram_ctrl_executable.2522141934
Short name T751
Test name
Test status
Simulation time 49884929765 ps
CPU time 1153.57 seconds
Started Jan 14 02:19:53 PM PST 24
Finished Jan 14 02:39:07 PM PST 24
Peak memory 368868 kb
Host smart-57bada54-cee1-4b96-bb37-8c14c3b6cef8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522141934 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_executab
le.2522141934
Directory /workspace/15.sram_ctrl_executable/latest

Test location /workspace/coverage/default/15.sram_ctrl_lc_escalation.928550431
Short name T601
Test name
Test status
Simulation time 17294856666 ps
CPU time 277.57 seconds
Started Jan 14 02:19:47 PM PST 24
Finished Jan 14 02:24:26 PM PST 24
Peak memory 210400 kb
Host smart-59cc31d6-9723-4408-9c7b-43df7520fd14
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928550431 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_esc
alation.928550431
Directory /workspace/15.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/15.sram_ctrl_max_throughput.632236259
Short name T8
Test name
Test status
Simulation time 3455815680 ps
CPU time 161.37 seconds
Started Jan 14 02:19:40 PM PST 24
Finished Jan 14 02:22:23 PM PST 24
Peak memory 371880 kb
Host smart-7dc87e52-38e8-4bcb-91ed-49f85018bfa9
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632236259 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.sram_ctrl_max_throughput.632236259
Directory /workspace/15.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/15.sram_ctrl_mem_partial_access.3913281978
Short name T485
Test name
Test status
Simulation time 8929669655 ps
CPU time 159.08 seconds
Started Jan 14 02:20:08 PM PST 24
Finished Jan 14 02:22:48 PM PST 24
Peak memory 210860 kb
Host smart-84f9366c-1c4d-4f20-a935-bcf2cd2872c7
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913281978 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.sram_ctrl_mem_partial_access.3913281978
Directory /workspace/15.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/15.sram_ctrl_mem_walk.3299956356
Short name T676
Test name
Test status
Simulation time 1978631663 ps
CPU time 125.74 seconds
Started Jan 14 02:20:10 PM PST 24
Finished Jan 14 02:22:17 PM PST 24
Peak memory 202132 kb
Host smart-02896c2c-0cbe-4d79-b659-83fc1616caa8
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299956356 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctr
l_mem_walk.3299956356
Directory /workspace/15.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/15.sram_ctrl_multiple_keys.80227780
Short name T990
Test name
Test status
Simulation time 4136518437 ps
CPU time 675.07 seconds
Started Jan 14 02:19:33 PM PST 24
Finished Jan 14 02:30:51 PM PST 24
Peak memory 379076 kb
Host smart-ffe92262-8624-4813-9a3e-84e256d1100b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80227780 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multip
le_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multipl
e_keys.80227780
Directory /workspace/15.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/15.sram_ctrl_partial_access.2323648938
Short name T670
Test name
Test status
Simulation time 998959812 ps
CPU time 16.99 seconds
Started Jan 14 02:19:39 PM PST 24
Finished Jan 14 02:19:57 PM PST 24
Peak memory 202064 kb
Host smart-c4dc72b3-f7ad-4568-92ce-f0a08c499684
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323648938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
sram_ctrl_partial_access.2323648938
Directory /workspace/15.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.1176223251
Short name T48
Test name
Test status
Simulation time 11185390530 ps
CPU time 296.16 seconds
Started Jan 14 02:19:39 PM PST 24
Finished Jan 14 02:24:36 PM PST 24
Peak memory 202172 kb
Host smart-090393c7-2c28-4fa2-b7da-eff6a6d0480c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176223251 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 15.sram_ctrl_partial_access_b2b.1176223251
Directory /workspace/15.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/15.sram_ctrl_ram_cfg.219175094
Short name T280
Test name
Test status
Simulation time 364907649 ps
CPU time 13.24 seconds
Started Jan 14 02:19:55 PM PST 24
Finished Jan 14 02:20:09 PM PST 24
Peak memory 202432 kb
Host smart-7d51f064-059c-4147-96f2-b40303e12606
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219175094 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.219175094
Directory /workspace/15.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/15.sram_ctrl_regwen.2413954067
Short name T914
Test name
Test status
Simulation time 4094779051 ps
CPU time 1158.75 seconds
Started Jan 14 02:19:54 PM PST 24
Finished Jan 14 02:39:14 PM PST 24
Peak memory 373980 kb
Host smart-43d37bae-b330-43ea-b055-bcb2dcfe577c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413954067 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.2413954067
Directory /workspace/15.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/15.sram_ctrl_smoke.506320689
Short name T336
Test name
Test status
Simulation time 1516082331 ps
CPU time 136.69 seconds
Started Jan 14 02:19:33 PM PST 24
Finished Jan 14 02:21:52 PM PST 24
Peak memory 340876 kb
Host smart-86a408fb-fb57-4be0-90e1-c47cf17361e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506320689 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.506320689
Directory /workspace/15.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.2897024622
Short name T903
Test name
Test status
Simulation time 9961358419 ps
CPU time 4275.21 seconds
Started Jan 14 02:20:09 PM PST 24
Finished Jan 14 03:31:27 PM PST 24
Peak memory 697952 kb
Host smart-ddae3f8c-5af7-4d3c-8319-c35257f6344a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2897024622 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all_with_rand_reset.2897024622
Directory /workspace/15.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.sram_ctrl_stress_pipeline.3016242342
Short name T536
Test name
Test status
Simulation time 6255991089 ps
CPU time 236.67 seconds
Started Jan 14 02:19:39 PM PST 24
Finished Jan 14 02:23:37 PM PST 24
Peak memory 202200 kb
Host smart-ef141939-01e0-4820-bf98-6ec112bec7d8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016242342 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.sram_ctrl_stress_pipeline.3016242342
Directory /workspace/15.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.1858055134
Short name T762
Test name
Test status
Simulation time 1508928467 ps
CPU time 53.11 seconds
Started Jan 14 02:19:48 PM PST 24
Finished Jan 14 02:20:42 PM PST 24
Peak memory 278780 kb
Host smart-58057583-18f2-40cc-bb57-eaf2dc0b57bf
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858055134 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.sram_ctrl_throughput_w_partial_write.1858055134
Directory /workspace/15.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/16.sram_ctrl_access_during_key_req.3849929756
Short name T375
Test name
Test status
Simulation time 14149241875 ps
CPU time 756.15 seconds
Started Jan 14 02:20:20 PM PST 24
Finished Jan 14 02:32:57 PM PST 24
Peak memory 379884 kb
Host smart-efb26719-9b5d-4414-87b3-b0c9b1f96c72
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849929756 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 16.sram_ctrl_access_during_key_req.3849929756
Directory /workspace/16.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/16.sram_ctrl_alert_test.660164999
Short name T518
Test name
Test status
Simulation time 18289917 ps
CPU time 0.62 seconds
Started Jan 14 02:20:30 PM PST 24
Finished Jan 14 02:20:31 PM PST 24
Peak memory 201380 kb
Host smart-73a07eac-5b29-4dbb-9657-48d82d9096c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660164999 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.sram_ctrl_alert_test.660164999
Directory /workspace/16.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.sram_ctrl_bijection.2242724200
Short name T452
Test name
Test status
Simulation time 21312448024 ps
CPU time 1576.49 seconds
Started Jan 14 02:20:16 PM PST 24
Finished Jan 14 02:46:33 PM PST 24
Peak memory 202176 kb
Host smart-05bf01ad-304a-4381-bc79-5fdd5f083b1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242724200 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection
.2242724200
Directory /workspace/16.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/16.sram_ctrl_lc_escalation.3063141709
Short name T673
Test name
Test status
Simulation time 7835944238 ps
CPU time 72.75 seconds
Started Jan 14 02:20:21 PM PST 24
Finished Jan 14 02:21:34 PM PST 24
Peak memory 213684 kb
Host smart-11c5e8ae-2b9c-4023-a444-c41b1fd4b3eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063141709 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_lc_es
calation.3063141709
Directory /workspace/16.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/16.sram_ctrl_max_throughput.1363460792
Short name T852
Test name
Test status
Simulation time 2794254293 ps
CPU time 26.55 seconds
Started Jan 14 02:20:10 PM PST 24
Finished Jan 14 02:20:38 PM PST 24
Peak memory 217596 kb
Host smart-a8db72f2-c583-4609-9109-f4b66cc48a1b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363460792 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 16.sram_ctrl_max_throughput.1363460792
Directory /workspace/16.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/16.sram_ctrl_mem_partial_access.3161440831
Short name T880
Test name
Test status
Simulation time 31220845827 ps
CPU time 143.24 seconds
Started Jan 14 02:20:27 PM PST 24
Finished Jan 14 02:22:51 PM PST 24
Peak memory 211460 kb
Host smart-87801577-f132-4109-bbd8-dd002f73a544
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161440831 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.sram_ctrl_mem_partial_access.3161440831
Directory /workspace/16.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/16.sram_ctrl_mem_walk.3736200332
Short name T976
Test name
Test status
Simulation time 57411449149 ps
CPU time 317.06 seconds
Started Jan 14 02:20:23 PM PST 24
Finished Jan 14 02:25:41 PM PST 24
Peak memory 202308 kb
Host smart-a58f2251-0e62-414e-b43c-fc418228c472
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736200332 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctr
l_mem_walk.3736200332
Directory /workspace/16.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/16.sram_ctrl_multiple_keys.111306688
Short name T746
Test name
Test status
Simulation time 21797360735 ps
CPU time 831.42 seconds
Started Jan 14 02:20:13 PM PST 24
Finished Jan 14 02:34:05 PM PST 24
Peak memory 358688 kb
Host smart-246738ff-f358-414a-b91e-fce39ca4f56c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111306688 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multip
le_keys.111306688
Directory /workspace/16.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/16.sram_ctrl_partial_access.3810343961
Short name T836
Test name
Test status
Simulation time 5674928516 ps
CPU time 28.47 seconds
Started Jan 14 02:20:15 PM PST 24
Finished Jan 14 02:20:44 PM PST 24
Peak memory 202184 kb
Host smart-5466a42d-b5f5-4c68-8a44-d6b0e796845e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810343961 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
sram_ctrl_partial_access.3810343961
Directory /workspace/16.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.3014495595
Short name T609
Test name
Test status
Simulation time 21680891293 ps
CPU time 378.02 seconds
Started Jan 14 02:20:14 PM PST 24
Finished Jan 14 02:26:33 PM PST 24
Peak memory 202244 kb
Host smart-eb25e1c8-e6a0-44e5-a4eb-6aceef4edf0b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014495595 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 16.sram_ctrl_partial_access_b2b.3014495595
Directory /workspace/16.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/16.sram_ctrl_ram_cfg.3507251387
Short name T760
Test name
Test status
Simulation time 361145773 ps
CPU time 13.08 seconds
Started Jan 14 02:20:23 PM PST 24
Finished Jan 14 02:20:37 PM PST 24
Peak memory 202440 kb
Host smart-74774c43-24a3-4b2c-a994-0403dffe58e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507251387 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.3507251387
Directory /workspace/16.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/16.sram_ctrl_regwen.1996046870
Short name T362
Test name
Test status
Simulation time 10108406171 ps
CPU time 540.73 seconds
Started Jan 14 02:20:20 PM PST 24
Finished Jan 14 02:29:22 PM PST 24
Peak memory 378976 kb
Host smart-418f43a5-e95d-4e5b-bf5a-1d8fca962b26
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996046870 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.1996046870
Directory /workspace/16.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/16.sram_ctrl_smoke.1313919619
Short name T358
Test name
Test status
Simulation time 1680938475 ps
CPU time 74.5 seconds
Started Jan 14 02:20:14 PM PST 24
Finished Jan 14 02:21:29 PM PST 24
Peak memory 318672 kb
Host smart-c6776ce8-f1a0-45fd-bb6d-25e4907eb423
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313919619 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.1313919619
Directory /workspace/16.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.3027986378
Short name T974
Test name
Test status
Simulation time 952421841 ps
CPU time 2185.43 seconds
Started Jan 14 02:20:26 PM PST 24
Finished Jan 14 02:56:52 PM PST 24
Peak memory 413840 kb
Host smart-80c8d38a-96a8-4b6d-b7db-ddfc58197717
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3027986378 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all_with_rand_reset.3027986378
Directory /workspace/16.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.sram_ctrl_stress_pipeline.609003227
Short name T503
Test name
Test status
Simulation time 20624377996 ps
CPU time 393.48 seconds
Started Jan 14 02:20:10 PM PST 24
Finished Jan 14 02:26:45 PM PST 24
Peak memory 202140 kb
Host smart-05c4673e-0a56-47d8-b282-cdcafdb61960
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609003227 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.sram_ctrl_stress_pipeline.609003227
Directory /workspace/16.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.211524202
Short name T323
Test name
Test status
Simulation time 3075989758 ps
CPU time 71.15 seconds
Started Jan 14 02:20:13 PM PST 24
Finished Jan 14 02:21:25 PM PST 24
Peak memory 303368 kb
Host smart-0138a22c-1dbb-4661-8df5-91791ae0bcd5
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211524202 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 16.sram_ctrl_throughput_w_partial_write.211524202
Directory /workspace/16.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/17.sram_ctrl_access_during_key_req.4035399330
Short name T663
Test name
Test status
Simulation time 16250631216 ps
CPU time 1318.37 seconds
Started Jan 14 02:20:37 PM PST 24
Finished Jan 14 02:42:36 PM PST 24
Peak memory 381140 kb
Host smart-61351009-0912-41bc-b585-8a7eeaaef42a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035399330 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.sram_ctrl_access_during_key_req.4035399330
Directory /workspace/17.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/17.sram_ctrl_bijection.1456164433
Short name T528
Test name
Test status
Simulation time 33118217717 ps
CPU time 2270.44 seconds
Started Jan 14 02:20:30 PM PST 24
Finished Jan 14 02:58:22 PM PST 24
Peak memory 202192 kb
Host smart-56010d03-0859-43b8-b612-0827cf91892f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456164433 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection
.1456164433
Directory /workspace/17.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/17.sram_ctrl_executable.2203511114
Short name T317
Test name
Test status
Simulation time 13268251623 ps
CPU time 381.24 seconds
Started Jan 14 02:20:44 PM PST 24
Finished Jan 14 02:27:06 PM PST 24
Peak memory 350472 kb
Host smart-838bc17a-8da8-4475-9227-67717c5d2d0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203511114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_executab
le.2203511114
Directory /workspace/17.sram_ctrl_executable/latest

Test location /workspace/coverage/default/17.sram_ctrl_max_throughput.615540073
Short name T584
Test name
Test status
Simulation time 2579405271 ps
CPU time 131.92 seconds
Started Jan 14 02:20:36 PM PST 24
Finished Jan 14 02:22:49 PM PST 24
Peak memory 342704 kb
Host smart-9a1e64c1-e67f-49c8-88a7-aa4d538218da
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615540073 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.sram_ctrl_max_throughput.615540073
Directory /workspace/17.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/17.sram_ctrl_mem_partial_access.2008582017
Short name T566
Test name
Test status
Simulation time 1571116139 ps
CPU time 150.61 seconds
Started Jan 14 02:20:51 PM PST 24
Finished Jan 14 02:23:23 PM PST 24
Peak memory 218492 kb
Host smart-10a87cc4-7d19-4fe6-a2d5-db8b4e1c2185
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008582017 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.sram_ctrl_mem_partial_access.2008582017
Directory /workspace/17.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/17.sram_ctrl_mem_walk.2015405158
Short name T546
Test name
Test status
Simulation time 57350882014 ps
CPU time 303.98 seconds
Started Jan 14 02:20:51 PM PST 24
Finished Jan 14 02:25:56 PM PST 24
Peak memory 202568 kb
Host smart-3df03d08-7748-49b2-923b-d67e3ef5d198
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015405158 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctr
l_mem_walk.2015405158
Directory /workspace/17.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/17.sram_ctrl_multiple_keys.1773615659
Short name T826
Test name
Test status
Simulation time 33717997534 ps
CPU time 690.12 seconds
Started Jan 14 02:20:31 PM PST 24
Finished Jan 14 02:32:02 PM PST 24
Peak memory 376024 kb
Host smart-88612218-a0a0-47e9-b22d-40bc3db9d742
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773615659 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multi
ple_keys.1773615659
Directory /workspace/17.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/17.sram_ctrl_partial_access.833809286
Short name T272
Test name
Test status
Simulation time 14000922605 ps
CPU time 23.88 seconds
Started Jan 14 02:20:38 PM PST 24
Finished Jan 14 02:21:02 PM PST 24
Peak memory 202168 kb
Host smart-5ad74e06-4d93-4cec-88b9-92a432ad6c3a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833809286 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.s
ram_ctrl_partial_access.833809286
Directory /workspace/17.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.1087503326
Short name T686
Test name
Test status
Simulation time 21699151581 ps
CPU time 248.9 seconds
Started Jan 14 02:20:37 PM PST 24
Finished Jan 14 02:24:47 PM PST 24
Peak memory 202024 kb
Host smart-8cfd8a7f-e8bf-4daa-95f4-772edb03ea71
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087503326 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 17.sram_ctrl_partial_access_b2b.1087503326
Directory /workspace/17.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/17.sram_ctrl_ram_cfg.3730084387
Short name T232
Test name
Test status
Simulation time 362345059 ps
CPU time 13.72 seconds
Started Jan 14 02:20:44 PM PST 24
Finished Jan 14 02:20:58 PM PST 24
Peak memory 202376 kb
Host smart-e3e2366f-6401-4874-bac6-508b3ae635ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730084387 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.3730084387
Directory /workspace/17.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/17.sram_ctrl_regwen.1991912305
Short name T439
Test name
Test status
Simulation time 6160985803 ps
CPU time 85.28 seconds
Started Jan 14 02:20:45 PM PST 24
Finished Jan 14 02:22:11 PM PST 24
Peak memory 270608 kb
Host smart-3b92bdbd-0f73-4f0b-9204-2090d8dd4dfe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991912305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.1991912305
Directory /workspace/17.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/17.sram_ctrl_smoke.4249477139
Short name T11
Test name
Test status
Simulation time 847547378 ps
CPU time 36.45 seconds
Started Jan 14 02:20:31 PM PST 24
Finished Jan 14 02:21:08 PM PST 24
Peak memory 202008 kb
Host smart-98f56e36-3db3-4d31-b686-9c92dc9cf399
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249477139 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.4249477139
Directory /workspace/17.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.389019616
Short name T789
Test name
Test status
Simulation time 4333725439 ps
CPU time 6419.44 seconds
Started Jan 14 02:20:52 PM PST 24
Finished Jan 14 04:07:53 PM PST 24
Peak memory 697580 kb
Host smart-ca906b3e-426e-480f-a9fb-658f9e5e1bce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=389019616 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all_with_rand_reset.389019616
Directory /workspace/17.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.sram_ctrl_stress_pipeline.143504252
Short name T359
Test name
Test status
Simulation time 17524712611 ps
CPU time 388.13 seconds
Started Jan 14 02:20:36 PM PST 24
Finished Jan 14 02:27:04 PM PST 24
Peak memory 202188 kb
Host smart-05cbeda3-b8b4-4bb4-a797-8635a5f3d5ad
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143504252 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.sram_ctrl_stress_pipeline.143504252
Directory /workspace/17.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.2049431585
Short name T443
Test name
Test status
Simulation time 3256940076 ps
CPU time 173.26 seconds
Started Jan 14 02:20:36 PM PST 24
Finished Jan 14 02:23:30 PM PST 24
Peak memory 371844 kb
Host smart-300833e2-0c9a-4b51-b817-8afdd6d06ac8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049431585 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.sram_ctrl_throughput_w_partial_write.2049431585
Directory /workspace/17.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/18.sram_ctrl_access_during_key_req.588719524
Short name T629
Test name
Test status
Simulation time 4020652669 ps
CPU time 685.79 seconds
Started Jan 14 02:21:13 PM PST 24
Finished Jan 14 02:32:40 PM PST 24
Peak memory 370540 kb
Host smart-80a806b0-b343-428f-9e63-2561f9e66cc6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588719524 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 18.sram_ctrl_access_during_key_req.588719524
Directory /workspace/18.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/18.sram_ctrl_alert_test.3387900728
Short name T841
Test name
Test status
Simulation time 20530231 ps
CPU time 0.65 seconds
Started Jan 14 02:21:25 PM PST 24
Finished Jan 14 02:21:27 PM PST 24
Peak memory 201900 kb
Host smart-537504d0-0bc3-433f-8784-a04e94855344
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387900728 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.sram_ctrl_alert_test.3387900728
Directory /workspace/18.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.sram_ctrl_bijection.1568831336
Short name T12
Test name
Test status
Simulation time 24237161072 ps
CPU time 520.78 seconds
Started Jan 14 02:21:01 PM PST 24
Finished Jan 14 02:29:43 PM PST 24
Peak memory 202164 kb
Host smart-537268b7-c141-4a79-88d4-02acb1e74222
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568831336 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection
.1568831336
Directory /workspace/18.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/18.sram_ctrl_executable.1399270426
Short name T121
Test name
Test status
Simulation time 18292665774 ps
CPU time 1293.57 seconds
Started Jan 14 02:21:13 PM PST 24
Finished Jan 14 02:42:47 PM PST 24
Peak memory 373944 kb
Host smart-687983d7-e7d7-46f9-9be9-c1801460fdf4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399270426 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_executab
le.1399270426
Directory /workspace/18.sram_ctrl_executable/latest

Test location /workspace/coverage/default/18.sram_ctrl_lc_escalation.974105387
Short name T720
Test name
Test status
Simulation time 67609753337 ps
CPU time 192.8 seconds
Started Jan 14 02:21:14 PM PST 24
Finished Jan 14 02:24:28 PM PST 24
Peak memory 210412 kb
Host smart-d9a6da0c-7e0d-4716-b745-54cd316e65d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974105387 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_esc
alation.974105387
Directory /workspace/18.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/18.sram_ctrl_max_throughput.4116978346
Short name T534
Test name
Test status
Simulation time 1899166314 ps
CPU time 189.84 seconds
Started Jan 14 02:21:07 PM PST 24
Finished Jan 14 02:24:17 PM PST 24
Peak memory 361584 kb
Host smart-c24b195d-b434-4df2-ad19-0c5080028112
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116978346 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 18.sram_ctrl_max_throughput.4116978346
Directory /workspace/18.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/18.sram_ctrl_mem_partial_access.3932930001
Short name T270
Test name
Test status
Simulation time 19308692315 ps
CPU time 143.64 seconds
Started Jan 14 02:21:30 PM PST 24
Finished Jan 14 02:23:55 PM PST 24
Peak memory 218492 kb
Host smart-4f32e5d5-aa28-4400-8a5a-5b590256d556
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932930001 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.sram_ctrl_mem_partial_access.3932930001
Directory /workspace/18.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/18.sram_ctrl_mem_walk.111799762
Short name T391
Test name
Test status
Simulation time 8042847047 ps
CPU time 251.06 seconds
Started Jan 14 02:21:26 PM PST 24
Finished Jan 14 02:25:38 PM PST 24
Peak memory 202228 kb
Host smart-42fad47e-b0e0-48bf-951f-fac2c52be017
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111799762 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl
_mem_walk.111799762
Directory /workspace/18.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/18.sram_ctrl_multiple_keys.646459637
Short name T659
Test name
Test status
Simulation time 5497151587 ps
CPU time 935 seconds
Started Jan 14 02:21:00 PM PST 24
Finished Jan 14 02:36:35 PM PST 24
Peak memory 378072 kb
Host smart-7200a9f3-1f1f-4fcb-967e-f309bf8ff27b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646459637 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multip
le_keys.646459637
Directory /workspace/18.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/18.sram_ctrl_partial_access.2091523106
Short name T341
Test name
Test status
Simulation time 2823025801 ps
CPU time 10.66 seconds
Started Jan 14 02:21:00 PM PST 24
Finished Jan 14 02:21:11 PM PST 24
Peak memory 202188 kb
Host smart-ff1af8e7-b2af-48a8-9c46-60fdf8983834
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091523106 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
sram_ctrl_partial_access.2091523106
Directory /workspace/18.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.3529281120
Short name T685
Test name
Test status
Simulation time 4270359063 ps
CPU time 262.39 seconds
Started Jan 14 02:21:06 PM PST 24
Finished Jan 14 02:25:29 PM PST 24
Peak memory 202168 kb
Host smart-0776b0d2-4595-42c4-aad3-5a76af52ca26
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529281120 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 18.sram_ctrl_partial_access_b2b.3529281120
Directory /workspace/18.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/18.sram_ctrl_ram_cfg.637382161
Short name T611
Test name
Test status
Simulation time 1343241842 ps
CPU time 6.07 seconds
Started Jan 14 02:21:31 PM PST 24
Finished Jan 14 02:21:39 PM PST 24
Peak memory 202452 kb
Host smart-934937f9-c07b-4d30-af64-d97e84da0acb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637382161 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.637382161
Directory /workspace/18.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/18.sram_ctrl_regwen.644972901
Short name T623
Test name
Test status
Simulation time 2907526440 ps
CPU time 178.46 seconds
Started Jan 14 02:21:14 PM PST 24
Finished Jan 14 02:24:13 PM PST 24
Peak memory 317628 kb
Host smart-b3830c86-6a89-4f7f-aa97-b75f38d5de9d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644972901 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.644972901
Directory /workspace/18.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/18.sram_ctrl_smoke.826045447
Short name T767
Test name
Test status
Simulation time 3767746103 ps
CPU time 18.24 seconds
Started Jan 14 02:21:01 PM PST 24
Finished Jan 14 02:21:20 PM PST 24
Peak memory 202108 kb
Host smart-e32714cb-b8c7-457b-a4f4-7e6e6eb70b6b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826045447 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.826045447
Directory /workspace/18.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/18.sram_ctrl_stress_all.1953320923
Short name T894
Test name
Test status
Simulation time 264483543124 ps
CPU time 4571.39 seconds
Started Jan 14 02:21:36 PM PST 24
Finished Jan 14 03:37:49 PM PST 24
Peak memory 346044 kb
Host smart-791b3f65-0269-4236-a56f-8f4da0486eaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953320923 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 18.sram_ctrl_stress_all.1953320923
Directory /workspace/18.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.305350354
Short name T865
Test name
Test status
Simulation time 5232028104 ps
CPU time 3960.5 seconds
Started Jan 14 02:21:29 PM PST 24
Finished Jan 14 03:27:31 PM PST 24
Peak memory 736396 kb
Host smart-d911720c-761e-4660-995d-47fe838ed2dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=305350354 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_all_with_rand_reset.305350354
Directory /workspace/18.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.sram_ctrl_stress_pipeline.1309583341
Short name T319
Test name
Test status
Simulation time 15972408829 ps
CPU time 279.16 seconds
Started Jan 14 02:21:01 PM PST 24
Finished Jan 14 02:25:41 PM PST 24
Peak memory 202160 kb
Host smart-12a4b2e6-381f-42cf-b8fd-c57a8d64ad93
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309583341 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.sram_ctrl_stress_pipeline.1309583341
Directory /workspace/18.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.695864971
Short name T370
Test name
Test status
Simulation time 1347904759 ps
CPU time 40.35 seconds
Started Jan 14 02:21:06 PM PST 24
Finished Jan 14 02:21:47 PM PST 24
Peak memory 251192 kb
Host smart-4c8e62dc-44cd-4980-8ac4-17024638c8d3
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695864971 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 18.sram_ctrl_throughput_w_partial_write.695864971
Directory /workspace/18.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/19.sram_ctrl_access_during_key_req.193926742
Short name T599
Test name
Test status
Simulation time 153353295396 ps
CPU time 1503.16 seconds
Started Jan 14 02:21:46 PM PST 24
Finished Jan 14 02:46:51 PM PST 24
Peak memory 373988 kb
Host smart-496b48ac-327c-49f4-a3d0-97ad385ac550
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193926742 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 19.sram_ctrl_access_during_key_req.193926742
Directory /workspace/19.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/19.sram_ctrl_alert_test.2585183774
Short name T343
Test name
Test status
Simulation time 14670027 ps
CPU time 0.66 seconds
Started Jan 14 02:21:58 PM PST 24
Finished Jan 14 02:22:05 PM PST 24
Peak memory 201440 kb
Host smart-ce7270f6-fedc-4f77-ae1f-c1371c45c017
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585183774 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.sram_ctrl_alert_test.2585183774
Directory /workspace/19.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.sram_ctrl_bijection.975480261
Short name T296
Test name
Test status
Simulation time 200802935662 ps
CPU time 1210.34 seconds
Started Jan 14 02:21:30 PM PST 24
Finished Jan 14 02:41:42 PM PST 24
Peak memory 202172 kb
Host smart-540d75b1-3732-4ae8-b31f-cffcc46685a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975480261 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection.
975480261
Directory /workspace/19.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/19.sram_ctrl_lc_escalation.1031767953
Short name T951
Test name
Test status
Simulation time 38903691270 ps
CPU time 88.81 seconds
Started Jan 14 02:21:46 PM PST 24
Finished Jan 14 02:23:17 PM PST 24
Peak memory 210488 kb
Host smart-2cf53053-c0b7-4278-96ab-f7afb0c3ce09
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031767953 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_es
calation.1031767953
Directory /workspace/19.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/19.sram_ctrl_max_throughput.1596928404
Short name T627
Test name
Test status
Simulation time 1396569844 ps
CPU time 26.5 seconds
Started Jan 14 02:21:41 PM PST 24
Finished Jan 14 02:22:13 PM PST 24
Peak memory 210348 kb
Host smart-29e3c2ce-cc28-4a23-b45d-cb192bbb9f78
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596928404 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 19.sram_ctrl_max_throughput.1596928404
Directory /workspace/19.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/19.sram_ctrl_mem_partial_access.1140175534
Short name T809
Test name
Test status
Simulation time 4737687397 ps
CPU time 73.84 seconds
Started Jan 14 02:21:47 PM PST 24
Finished Jan 14 02:23:04 PM PST 24
Peak memory 218512 kb
Host smart-f65fe04b-44d3-49fd-9328-a219505e5507
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140175534 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.sram_ctrl_mem_partial_access.1140175534
Directory /workspace/19.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/19.sram_ctrl_mem_walk.823528832
Short name T227
Test name
Test status
Simulation time 7583981654 ps
CPU time 146.31 seconds
Started Jan 14 02:21:48 PM PST 24
Finished Jan 14 02:24:20 PM PST 24
Peak memory 202292 kb
Host smart-dd7b873f-537f-4c2c-952a-ebfea4d7ba5e
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823528832 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl
_mem_walk.823528832
Directory /workspace/19.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/19.sram_ctrl_multiple_keys.3264507838
Short name T226
Test name
Test status
Simulation time 211605411559 ps
CPU time 1450.26 seconds
Started Jan 14 02:21:28 PM PST 24
Finished Jan 14 02:45:39 PM PST 24
Peak memory 379140 kb
Host smart-695d0562-38b1-4d77-8319-75783fa19e72
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264507838 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multi
ple_keys.3264507838
Directory /workspace/19.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/19.sram_ctrl_partial_access.3352984942
Short name T252
Test name
Test status
Simulation time 2738536768 ps
CPU time 29.09 seconds
Started Jan 14 02:21:42 PM PST 24
Finished Jan 14 02:22:15 PM PST 24
Peak memory 211256 kb
Host smart-430464b7-1fa1-4f41-a2ca-4f210966d7fa
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352984942 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
sram_ctrl_partial_access.3352984942
Directory /workspace/19.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.2038195122
Short name T350
Test name
Test status
Simulation time 22189972559 ps
CPU time 570.83 seconds
Started Jan 14 02:21:46 PM PST 24
Finished Jan 14 02:31:19 PM PST 24
Peak memory 202120 kb
Host smart-47e039b1-3372-4d46-aadc-bfffca843379
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038195122 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 19.sram_ctrl_partial_access_b2b.2038195122
Directory /workspace/19.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/19.sram_ctrl_ram_cfg.192854665
Short name T418
Test name
Test status
Simulation time 990914585 ps
CPU time 5.43 seconds
Started Jan 14 02:21:47 PM PST 24
Finished Jan 14 02:21:56 PM PST 24
Peak memory 202420 kb
Host smart-6eb30fe3-01a5-4f3b-9f73-493aa8977104
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192854665 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.192854665
Directory /workspace/19.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/19.sram_ctrl_smoke.517390935
Short name T356
Test name
Test status
Simulation time 640691755 ps
CPU time 27.52 seconds
Started Jan 14 02:21:26 PM PST 24
Finished Jan 14 02:21:54 PM PST 24
Peak memory 274732 kb
Host smart-90e4a8fc-c9d2-43eb-b150-4b9b5c02b5e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517390935 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.517390935
Directory /workspace/19.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.686340888
Short name T553
Test name
Test status
Simulation time 202539230 ps
CPU time 2818.06 seconds
Started Jan 14 02:21:48 PM PST 24
Finished Jan 14 03:08:54 PM PST 24
Peak memory 573088 kb
Host smart-2fec88fe-5730-442b-8138-93962f358523
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=686340888 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all_with_rand_reset.686340888
Directory /workspace/19.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.sram_ctrl_stress_pipeline.1998824335
Short name T576
Test name
Test status
Simulation time 4269758140 ps
CPU time 312.67 seconds
Started Jan 14 02:21:31 PM PST 24
Finished Jan 14 02:26:45 PM PST 24
Peak memory 202172 kb
Host smart-285bf94e-2625-4d41-aa10-8e9d13d3002d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998824335 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.sram_ctrl_stress_pipeline.1998824335
Directory /workspace/19.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.1244321409
Short name T947
Test name
Test status
Simulation time 3250486255 ps
CPU time 167.27 seconds
Started Jan 14 02:21:41 PM PST 24
Finished Jan 14 02:24:33 PM PST 24
Peak memory 362756 kb
Host smart-d4353a59-e4d6-47c0-98a9-3f104042e6a2
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244321409 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 19.sram_ctrl_throughput_w_partial_write.1244321409
Directory /workspace/19.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/2.sram_ctrl_access_during_key_req.3827352747
Short name T236
Test name
Test status
Simulation time 16163484877 ps
CPU time 849.52 seconds
Started Jan 14 02:12:53 PM PST 24
Finished Jan 14 02:27:03 PM PST 24
Peak memory 378956 kb
Host smart-67fbadd6-9b8c-4311-997a-aa6197a032c4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827352747 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.sram_ctrl_access_during_key_req.3827352747
Directory /workspace/2.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/2.sram_ctrl_alert_test.490921990
Short name T736
Test name
Test status
Simulation time 13374232 ps
CPU time 0.66 seconds
Started Jan 14 02:13:08 PM PST 24
Finished Jan 14 02:13:10 PM PST 24
Peak memory 201864 kb
Host smart-5e9ba335-f828-4174-a6d1-f743e4249200
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490921990 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.sram_ctrl_alert_test.490921990
Directory /workspace/2.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.sram_ctrl_bijection.188425619
Short name T437
Test name
Test status
Simulation time 427730963394 ps
CPU time 1527.98 seconds
Started Jan 14 02:12:47 PM PST 24
Finished Jan 14 02:38:16 PM PST 24
Peak memory 202104 kb
Host smart-3a0c53b7-41a1-4be2-bf44-c20c393d2eb9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188425619 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection.188425619
Directory /workspace/2.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/2.sram_ctrl_executable.3709868043
Short name T621
Test name
Test status
Simulation time 38967208038 ps
CPU time 1129.04 seconds
Started Jan 14 02:12:52 PM PST 24
Finished Jan 14 02:31:42 PM PST 24
Peak memory 365924 kb
Host smart-b7425d35-2736-40c0-a556-7b403136c4aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709868043 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_executabl
e.3709868043
Directory /workspace/2.sram_ctrl_executable/latest

Test location /workspace/coverage/default/2.sram_ctrl_lc_escalation.4019707730
Short name T425
Test name
Test status
Simulation time 9850128617 ps
CPU time 184.28 seconds
Started Jan 14 02:12:47 PM PST 24
Finished Jan 14 02:15:52 PM PST 24
Peak memory 210372 kb
Host smart-6a94bc9d-6d15-437d-a375-c91919564aa2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019707730 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_esc
alation.4019707730
Directory /workspace/2.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/2.sram_ctrl_max_throughput.2980505020
Short name T758
Test name
Test status
Simulation time 1357555483 ps
CPU time 26.67 seconds
Started Jan 14 02:12:47 PM PST 24
Finished Jan 14 02:13:15 PM PST 24
Peak memory 210352 kb
Host smart-7fe76895-9e5d-4829-a884-8448caed2aba
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980505020 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.sram_ctrl_max_throughput.2980505020
Directory /workspace/2.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/2.sram_ctrl_mem_partial_access.1625472878
Short name T47
Test name
Test status
Simulation time 9567787639 ps
CPU time 159.32 seconds
Started Jan 14 02:13:05 PM PST 24
Finished Jan 14 02:15:45 PM PST 24
Peak memory 211648 kb
Host smart-51c31111-bb75-442c-9d35-eed62973d7df
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625472878 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.sram_ctrl_mem_partial_access.1625472878
Directory /workspace/2.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/2.sram_ctrl_mem_walk.1855035713
Short name T322
Test name
Test status
Simulation time 49222694775 ps
CPU time 305.37 seconds
Started Jan 14 02:13:04 PM PST 24
Finished Jan 14 02:18:10 PM PST 24
Peak memory 202344 kb
Host smart-0cce1d2d-cddd-421c-b920-d7f22c8d6579
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855035713 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl
_mem_walk.1855035713
Directory /workspace/2.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/2.sram_ctrl_multiple_keys.3787130543
Short name T907
Test name
Test status
Simulation time 15091855772 ps
CPU time 1394.92 seconds
Started Jan 14 02:12:46 PM PST 24
Finished Jan 14 02:36:02 PM PST 24
Peak memory 380172 kb
Host smart-2aa62699-eb4d-4ed1-8ebc-3b179c8e391f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787130543 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multip
le_keys.3787130543
Directory /workspace/2.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/2.sram_ctrl_partial_access.1558771765
Short name T275
Test name
Test status
Simulation time 3367731111 ps
CPU time 22.5 seconds
Started Jan 14 02:12:52 PM PST 24
Finished Jan 14 02:13:16 PM PST 24
Peak memory 250984 kb
Host smart-82e96c38-3e9c-4656-bdba-2c27a6b0ad83
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558771765 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.s
ram_ctrl_partial_access.1558771765
Directory /workspace/2.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.933452535
Short name T699
Test name
Test status
Simulation time 32196443106 ps
CPU time 207.21 seconds
Started Jan 14 02:12:46 PM PST 24
Finished Jan 14 02:16:14 PM PST 24
Peak memory 202176 kb
Host smart-fdffc178-8772-43e3-9cd9-ce6277605194
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933452535 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.sram_ctrl_partial_access_b2b.933452535
Directory /workspace/2.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/2.sram_ctrl_ram_cfg.125834066
Short name T665
Test name
Test status
Simulation time 1436589109 ps
CPU time 6.82 seconds
Started Jan 14 02:13:04 PM PST 24
Finished Jan 14 02:13:11 PM PST 24
Peak memory 202400 kb
Host smart-94afb023-4cde-4dea-932c-b86bb40251ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125834066 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.125834066
Directory /workspace/2.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/2.sram_ctrl_regwen.3307473523
Short name T28
Test name
Test status
Simulation time 20155910152 ps
CPU time 266.46 seconds
Started Jan 14 02:12:53 PM PST 24
Finished Jan 14 02:17:21 PM PST 24
Peak memory 378000 kb
Host smart-efd098f2-a25c-42df-b138-d2879704d1cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307473523 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.3307473523
Directory /workspace/2.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/2.sram_ctrl_sec_cm.3223138849
Short name T40
Test name
Test status
Simulation time 85070760 ps
CPU time 1.66 seconds
Started Jan 14 02:13:06 PM PST 24
Finished Jan 14 02:13:08 PM PST 24
Peak memory 220988 kb
Host smart-c6272f30-e656-4d8a-a4f4-ee2564d060e4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223138849 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.sram_ctrl_sec_cm.3223138849
Directory /workspace/2.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.sram_ctrl_smoke.4079595048
Short name T986
Test name
Test status
Simulation time 2953827323 ps
CPU time 53.5 seconds
Started Jan 14 02:12:44 PM PST 24
Finished Jan 14 02:13:38 PM PST 24
Peak memory 286864 kb
Host smart-e91ec209-efac-48de-8338-9659ab1c7e47
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079595048 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.4079595048
Directory /workspace/2.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/2.sram_ctrl_stress_all.1802723293
Short name T300
Test name
Test status
Simulation time 227683555121 ps
CPU time 5510.52 seconds
Started Jan 14 02:13:05 PM PST 24
Finished Jan 14 03:44:57 PM PST 24
Peak memory 378076 kb
Host smart-ee3e021c-1891-4180-be68-63dbf8b4b54d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802723293 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 2.sram_ctrl_stress_all.1802723293
Directory /workspace/2.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.597114226
Short name T906
Test name
Test status
Simulation time 2621624580 ps
CPU time 4217.84 seconds
Started Jan 14 02:13:04 PM PST 24
Finished Jan 14 03:23:23 PM PST 24
Peak memory 729100 kb
Host smart-dbf2391f-3ed0-4596-957f-4d703c130589
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=597114226 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all_with_rand_reset.597114226
Directory /workspace/2.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.sram_ctrl_stress_pipeline.1119662788
Short name T945
Test name
Test status
Simulation time 14371370842 ps
CPU time 240.45 seconds
Started Jan 14 02:12:48 PM PST 24
Finished Jan 14 02:16:49 PM PST 24
Peak memory 202172 kb
Host smart-6fbb48a9-4e54-42c9-b00e-70ea8bb85720
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119662788 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.sram_ctrl_stress_pipeline.1119662788
Directory /workspace/2.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.3378369898
Short name T688
Test name
Test status
Simulation time 788914000 ps
CPU time 164.66 seconds
Started Jan 14 02:12:52 PM PST 24
Finished Jan 14 02:15:37 PM PST 24
Peak memory 367280 kb
Host smart-70b3d405-c867-48b5-92b4-f8156f7be956
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378369898 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.sram_ctrl_throughput_w_partial_write.3378369898
Directory /workspace/2.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/20.sram_ctrl_access_during_key_req.2417499437
Short name T352
Test name
Test status
Simulation time 43657525556 ps
CPU time 1471.51 seconds
Started Jan 14 02:22:10 PM PST 24
Finished Jan 14 02:46:43 PM PST 24
Peak memory 376876 kb
Host smart-8bf64635-e8b7-404f-885f-1a5068c54b1a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417499437 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.sram_ctrl_access_during_key_req.2417499437
Directory /workspace/20.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/20.sram_ctrl_alert_test.4260318139
Short name T404
Test name
Test status
Simulation time 29363476 ps
CPU time 0.7 seconds
Started Jan 14 02:22:39 PM PST 24
Finished Jan 14 02:22:40 PM PST 24
Peak memory 201740 kb
Host smart-4e723734-d909-4b76-a1ac-58fb6982ab7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260318139 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.sram_ctrl_alert_test.4260318139
Directory /workspace/20.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.sram_ctrl_bijection.572803045
Short name T451
Test name
Test status
Simulation time 17939994680 ps
CPU time 1239.16 seconds
Started Jan 14 02:21:55 PM PST 24
Finished Jan 14 02:42:36 PM PST 24
Peak memory 202040 kb
Host smart-31576e42-80dd-43b7-a53c-6dfea14103b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572803045 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection.
572803045
Directory /workspace/20.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/20.sram_ctrl_lc_escalation.2622823631
Short name T638
Test name
Test status
Simulation time 33169565401 ps
CPU time 95.64 seconds
Started Jan 14 02:22:08 PM PST 24
Finished Jan 14 02:23:45 PM PST 24
Peak memory 213752 kb
Host smart-0d37029d-8cd9-4442-b5c9-003a5ab32c80
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622823631 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_lc_es
calation.2622823631
Directory /workspace/20.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/20.sram_ctrl_max_throughput.3176609709
Short name T780
Test name
Test status
Simulation time 3632210089 ps
CPU time 77.46 seconds
Started Jan 14 02:22:01 PM PST 24
Finished Jan 14 02:23:22 PM PST 24
Peak memory 309204 kb
Host smart-68b38d38-6fcf-4ac3-83ed-2bdd6315d603
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176609709 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 20.sram_ctrl_max_throughput.3176609709
Directory /workspace/20.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/20.sram_ctrl_mem_partial_access.2830506577
Short name T276
Test name
Test status
Simulation time 1932959020 ps
CPU time 135.67 seconds
Started Jan 14 02:22:38 PM PST 24
Finished Jan 14 02:24:54 PM PST 24
Peak memory 218464 kb
Host smart-e5df1d19-794a-46af-a3f6-dcea31e665cc
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830506577 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.sram_ctrl_mem_partial_access.2830506577
Directory /workspace/20.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/20.sram_ctrl_mem_walk.1366207092
Short name T940
Test name
Test status
Simulation time 7271580988 ps
CPU time 157.15 seconds
Started Jan 14 02:22:23 PM PST 24
Finished Jan 14 02:25:01 PM PST 24
Peak memory 202236 kb
Host smart-3078aa8f-9239-48d3-8fb7-9b7c808f1a93
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366207092 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctr
l_mem_walk.1366207092
Directory /workspace/20.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/20.sram_ctrl_multiple_keys.521377336
Short name T896
Test name
Test status
Simulation time 3005627126 ps
CPU time 275.25 seconds
Started Jan 14 02:21:54 PM PST 24
Finished Jan 14 02:26:32 PM PST 24
Peak memory 370840 kb
Host smart-4b66b51d-1a85-411b-8e16-b6bd9688d2ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521377336 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multip
le_keys.521377336
Directory /workspace/20.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/20.sram_ctrl_partial_access.4067502089
Short name T827
Test name
Test status
Simulation time 2862318026 ps
CPU time 24.88 seconds
Started Jan 14 02:22:02 PM PST 24
Finished Jan 14 02:22:30 PM PST 24
Peak memory 202052 kb
Host smart-847a63b9-0a63-4c42-8d27-cc2b59bc144b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067502089 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
sram_ctrl_partial_access.4067502089
Directory /workspace/20.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/20.sram_ctrl_partial_access_b2b.2830531615
Short name T476
Test name
Test status
Simulation time 46614118993 ps
CPU time 310.17 seconds
Started Jan 14 02:22:01 PM PST 24
Finished Jan 14 02:27:15 PM PST 24
Peak memory 202152 kb
Host smart-fe68b95b-817d-4792-a074-5efd9e59d948
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830531615 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 20.sram_ctrl_partial_access_b2b.2830531615
Directory /workspace/20.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/20.sram_ctrl_ram_cfg.1277332160
Short name T892
Test name
Test status
Simulation time 342846291 ps
CPU time 6.71 seconds
Started Jan 14 02:22:08 PM PST 24
Finished Jan 14 02:22:16 PM PST 24
Peak memory 202444 kb
Host smart-cf0e6a04-2f87-448c-8546-7149d546bd5d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277332160 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.1277332160
Directory /workspace/20.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/20.sram_ctrl_regwen.2942399374
Short name T843
Test name
Test status
Simulation time 10950305909 ps
CPU time 1275.01 seconds
Started Jan 14 02:22:08 PM PST 24
Finished Jan 14 02:43:25 PM PST 24
Peak memory 380112 kb
Host smart-92bead5c-bae2-4e77-a32d-5ec7572f7251
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942399374 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.2942399374
Directory /workspace/20.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/20.sram_ctrl_smoke.449357201
Short name T516
Test name
Test status
Simulation time 5664926438 ps
CPU time 7.41 seconds
Started Jan 14 02:21:54 PM PST 24
Finished Jan 14 02:22:04 PM PST 24
Peak memory 202124 kb
Host smart-6d767b36-a221-495c-8f10-f85049b59713
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449357201 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.449357201
Directory /workspace/20.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/20.sram_ctrl_stress_all.3816624908
Short name T449
Test name
Test status
Simulation time 626578337205 ps
CPU time 3528.32 seconds
Started Jan 14 02:22:21 PM PST 24
Finished Jan 14 03:21:11 PM PST 24
Peak memory 381164 kb
Host smart-5cb24ff5-4e7a-4426-beb1-6445bc61484d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816624908 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 20.sram_ctrl_stress_all.3816624908
Directory /workspace/20.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.2522934714
Short name T502
Test name
Test status
Simulation time 6212888377 ps
CPU time 5269.01 seconds
Started Jan 14 02:22:22 PM PST 24
Finished Jan 14 03:50:14 PM PST 24
Peak memory 529200 kb
Host smart-1d55d6eb-db25-450f-ac06-246deb609601
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2522934714 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all_with_rand_reset.2522934714
Directory /workspace/20.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.sram_ctrl_stress_pipeline.2252472340
Short name T453
Test name
Test status
Simulation time 5840309921 ps
CPU time 227.9 seconds
Started Jan 14 02:21:54 PM PST 24
Finished Jan 14 02:25:45 PM PST 24
Peak memory 202172 kb
Host smart-a92acaf2-ee8b-46c0-bc36-111656cbf3c7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252472340 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.sram_ctrl_stress_pipeline.2252472340
Directory /workspace/20.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.1708654935
Short name T748
Test name
Test status
Simulation time 4229790032 ps
CPU time 54.56 seconds
Started Jan 14 02:22:03 PM PST 24
Finished Jan 14 02:23:00 PM PST 24
Peak memory 274892 kb
Host smart-816b2d33-f96b-405d-99f2-63cc0e3e619e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708654935 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 20.sram_ctrl_throughput_w_partial_write.1708654935
Directory /workspace/20.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/21.sram_ctrl_access_during_key_req.3342593836
Short name T15
Test name
Test status
Simulation time 35641414993 ps
CPU time 499.24 seconds
Started Jan 14 02:22:44 PM PST 24
Finished Jan 14 02:31:04 PM PST 24
Peak memory 371436 kb
Host smart-0b0acd03-911f-41dc-9674-9b3e1508e71c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342593836 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.sram_ctrl_access_during_key_req.3342593836
Directory /workspace/21.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/21.sram_ctrl_alert_test.2683664769
Short name T733
Test name
Test status
Simulation time 11918626 ps
CPU time 0.63 seconds
Started Jan 14 02:22:55 PM PST 24
Finished Jan 14 02:22:57 PM PST 24
Peak memory 201464 kb
Host smart-2abbeacf-c1cc-4e31-be9c-ba94995d17b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683664769 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.sram_ctrl_alert_test.2683664769
Directory /workspace/21.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.sram_ctrl_bijection.2938746146
Short name T108
Test name
Test status
Simulation time 101772601016 ps
CPU time 1965.3 seconds
Started Jan 14 02:22:28 PM PST 24
Finished Jan 14 02:55:14 PM PST 24
Peak memory 210376 kb
Host smart-4dd4792c-7079-4b22-8444-db8af98e502a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938746146 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection
.2938746146
Directory /workspace/21.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/21.sram_ctrl_executable.3119034035
Short name T533
Test name
Test status
Simulation time 41906271613 ps
CPU time 1253.75 seconds
Started Jan 14 02:22:43 PM PST 24
Finished Jan 14 02:43:38 PM PST 24
Peak memory 371880 kb
Host smart-cfeb4562-cc9c-4a8d-8b80-ef3ad4c753a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119034035 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_executab
le.3119034035
Directory /workspace/21.sram_ctrl_executable/latest

Test location /workspace/coverage/default/21.sram_ctrl_lc_escalation.2022847054
Short name T377
Test name
Test status
Simulation time 7398499697 ps
CPU time 182.06 seconds
Started Jan 14 02:22:39 PM PST 24
Finished Jan 14 02:25:41 PM PST 24
Peak memory 211656 kb
Host smart-8ad4d090-ae00-409d-8706-73a4b623d6c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022847054 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_lc_es
calation.2022847054
Directory /workspace/21.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/21.sram_ctrl_max_throughput.3922954940
Short name T450
Test name
Test status
Simulation time 1536369128 ps
CPU time 197.5 seconds
Started Jan 14 02:22:29 PM PST 24
Finished Jan 14 02:25:48 PM PST 24
Peak memory 373952 kb
Host smart-1d99a94b-1b81-4a1b-9563-77c245385b49
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922954940 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 21.sram_ctrl_max_throughput.3922954940
Directory /workspace/21.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/21.sram_ctrl_mem_partial_access.3818044351
Short name T523
Test name
Test status
Simulation time 5205025095 ps
CPU time 80.91 seconds
Started Jan 14 02:22:51 PM PST 24
Finished Jan 14 02:24:12 PM PST 24
Peak memory 211112 kb
Host smart-e0b8ef00-c6ad-4c39-b429-e58466985a70
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818044351 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.sram_ctrl_mem_partial_access.3818044351
Directory /workspace/21.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/21.sram_ctrl_mem_walk.2901108143
Short name T768
Test name
Test status
Simulation time 82525361209 ps
CPU time 329.04 seconds
Started Jan 14 02:22:51 PM PST 24
Finished Jan 14 02:28:21 PM PST 24
Peak memory 202156 kb
Host smart-4b518ead-f029-4a52-99ee-6890a8a1190b
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901108143 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctr
l_mem_walk.2901108143
Directory /workspace/21.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/21.sram_ctrl_multiple_keys.428989695
Short name T649
Test name
Test status
Simulation time 16140237314 ps
CPU time 1561.2 seconds
Started Jan 14 02:22:27 PM PST 24
Finished Jan 14 02:48:29 PM PST 24
Peak memory 381156 kb
Host smart-784673b2-113a-44b2-bc5b-19c1e26650fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428989695 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multip
le_keys.428989695
Directory /workspace/21.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/21.sram_ctrl_partial_access.4134207959
Short name T726
Test name
Test status
Simulation time 872522826 ps
CPU time 73.83 seconds
Started Jan 14 02:22:37 PM PST 24
Finished Jan 14 02:23:51 PM PST 24
Peak memory 320720 kb
Host smart-b3d064f0-180d-4b36-8725-0cf621a1d8a4
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134207959 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
sram_ctrl_partial_access.4134207959
Directory /workspace/21.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.1763010763
Short name T527
Test name
Test status
Simulation time 24931080060 ps
CPU time 319.34 seconds
Started Jan 14 02:22:27 PM PST 24
Finished Jan 14 02:27:48 PM PST 24
Peak memory 210368 kb
Host smart-62cf1b53-f5c7-4e22-9067-fa506492f51f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763010763 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 21.sram_ctrl_partial_access_b2b.1763010763
Directory /workspace/21.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/21.sram_ctrl_ram_cfg.3301380852
Short name T585
Test name
Test status
Simulation time 371958831 ps
CPU time 13.8 seconds
Started Jan 14 02:22:44 PM PST 24
Finished Jan 14 02:22:58 PM PST 24
Peak memory 202424 kb
Host smart-2219f292-f4cc-467e-b1bf-a4f74f25ed49
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301380852 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.3301380852
Directory /workspace/21.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/21.sram_ctrl_regwen.718309109
Short name T639
Test name
Test status
Simulation time 659917605 ps
CPU time 99.27 seconds
Started Jan 14 02:22:43 PM PST 24
Finished Jan 14 02:24:23 PM PST 24
Peak memory 321764 kb
Host smart-b0e42d83-55b2-46a2-b2ae-dfc920293fef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718309109 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.718309109
Directory /workspace/21.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/21.sram_ctrl_smoke.2204181950
Short name T313
Test name
Test status
Simulation time 1457626573 ps
CPU time 26.19 seconds
Started Jan 14 02:22:21 PM PST 24
Finished Jan 14 02:22:48 PM PST 24
Peak memory 202088 kb
Host smart-77bb1821-df21-4686-857d-5a35c12cfee8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204181950 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.2204181950
Directory /workspace/21.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.506709531
Short name T105
Test name
Test status
Simulation time 8573777704 ps
CPU time 3435.59 seconds
Started Jan 14 02:22:56 PM PST 24
Finished Jan 14 03:20:13 PM PST 24
Peak memory 749108 kb
Host smart-2e5bb82a-d6d5-408a-8214-535fb79e56cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=506709531 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all_with_rand_reset.506709531
Directory /workspace/21.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.sram_ctrl_stress_pipeline.1383105448
Short name T46
Test name
Test status
Simulation time 70968299113 ps
CPU time 328.6 seconds
Started Jan 14 02:22:36 PM PST 24
Finished Jan 14 02:28:06 PM PST 24
Peak memory 202192 kb
Host smart-88007831-745a-413e-adca-d061daa81876
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383105448 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.sram_ctrl_stress_pipeline.1383105448
Directory /workspace/21.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.996923780
Short name T251
Test name
Test status
Simulation time 2824294713 ps
CPU time 30.9 seconds
Started Jan 14 02:22:38 PM PST 24
Finished Jan 14 02:23:10 PM PST 24
Peak memory 219640 kb
Host smart-fc5e04f1-3cbb-4ece-a8a9-817336252d0e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996923780 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 21.sram_ctrl_throughput_w_partial_write.996923780
Directory /workspace/21.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/22.sram_ctrl_access_during_key_req.1537484742
Short name T2
Test name
Test status
Simulation time 7743184691 ps
CPU time 772 seconds
Started Jan 14 02:23:07 PM PST 24
Finished Jan 14 02:35:59 PM PST 24
Peak memory 376940 kb
Host smart-c0426094-3331-4e38-9fda-c187558d15e6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537484742 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.sram_ctrl_access_during_key_req.1537484742
Directory /workspace/22.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/22.sram_ctrl_alert_test.4118679719
Short name T508
Test name
Test status
Simulation time 36116802 ps
CPU time 0.66 seconds
Started Jan 14 02:23:22 PM PST 24
Finished Jan 14 02:23:23 PM PST 24
Peak memory 201852 kb
Host smart-94caa258-8f51-434d-8a44-9377702a748e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118679719 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.sram_ctrl_alert_test.4118679719
Directory /workspace/22.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.sram_ctrl_bijection.3784625788
Short name T856
Test name
Test status
Simulation time 14661939737 ps
CPU time 485.39 seconds
Started Jan 14 02:23:01 PM PST 24
Finished Jan 14 02:31:08 PM PST 24
Peak memory 202184 kb
Host smart-ee7d4c1c-8eeb-47f1-be36-0e1429fd2f9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784625788 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection
.3784625788
Directory /workspace/22.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/22.sram_ctrl_executable.4248415592
Short name T741
Test name
Test status
Simulation time 133348450259 ps
CPU time 975.67 seconds
Started Jan 14 02:23:06 PM PST 24
Finished Jan 14 02:39:23 PM PST 24
Peak memory 376008 kb
Host smart-dd57e244-4993-4a66-97f5-a48613a5364e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248415592 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_executab
le.4248415592
Directory /workspace/22.sram_ctrl_executable/latest

Test location /workspace/coverage/default/22.sram_ctrl_lc_escalation.1065122417
Short name T342
Test name
Test status
Simulation time 71281407125 ps
CPU time 184.66 seconds
Started Jan 14 02:22:59 PM PST 24
Finished Jan 14 02:26:05 PM PST 24
Peak memory 210388 kb
Host smart-f4c55b08-05cd-493f-ab5c-bccbef838cbc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065122417 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_es
calation.1065122417
Directory /workspace/22.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/22.sram_ctrl_max_throughput.1120027116
Short name T615
Test name
Test status
Simulation time 1427707201 ps
CPU time 32.57 seconds
Started Jan 14 02:23:00 PM PST 24
Finished Jan 14 02:23:33 PM PST 24
Peak memory 234668 kb
Host smart-5402e26b-507a-47b6-969d-d070c613b59e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120027116 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 22.sram_ctrl_max_throughput.1120027116
Directory /workspace/22.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/22.sram_ctrl_mem_partial_access.3330282468
Short name T967
Test name
Test status
Simulation time 2345200383 ps
CPU time 78.06 seconds
Started Jan 14 02:23:18 PM PST 24
Finished Jan 14 02:24:37 PM PST 24
Peak memory 211192 kb
Host smart-b832f9fb-9bed-455d-926e-84bcbf3a1d0c
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330282468 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.sram_ctrl_mem_partial_access.3330282468
Directory /workspace/22.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/22.sram_ctrl_mem_walk.3497388927
Short name T819
Test name
Test status
Simulation time 49681758714 ps
CPU time 155.11 seconds
Started Jan 14 02:23:16 PM PST 24
Finished Jan 14 02:25:52 PM PST 24
Peak memory 202248 kb
Host smart-05eb4c73-e7e9-4da3-b36a-b2910e49a803
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497388927 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctr
l_mem_walk.3497388927
Directory /workspace/22.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/22.sram_ctrl_multiple_keys.64135676
Short name T653
Test name
Test status
Simulation time 16149854723 ps
CPU time 1422.39 seconds
Started Jan 14 02:23:04 PM PST 24
Finished Jan 14 02:46:47 PM PST 24
Peak memory 371016 kb
Host smart-007b71e2-b59a-4a8c-8708-ed2264c73790
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64135676 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multip
le_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multipl
e_keys.64135676
Directory /workspace/22.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/22.sram_ctrl_partial_access.183280151
Short name T988
Test name
Test status
Simulation time 4212852962 ps
CPU time 57.43 seconds
Started Jan 14 02:23:00 PM PST 24
Finished Jan 14 02:23:59 PM PST 24
Peak memory 295212 kb
Host smart-0237bf55-3f3a-41aa-9712-50c64f58b2f4
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183280151 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.s
ram_ctrl_partial_access.183280151
Directory /workspace/22.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.1797048440
Short name T128
Test name
Test status
Simulation time 12910241404 ps
CPU time 298.74 seconds
Started Jan 14 02:23:00 PM PST 24
Finished Jan 14 02:27:59 PM PST 24
Peak memory 202116 kb
Host smart-b91115c2-5b77-4dbb-86ab-51ef13c8a4e4
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797048440 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 22.sram_ctrl_partial_access_b2b.1797048440
Directory /workspace/22.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/22.sram_ctrl_ram_cfg.813552671
Short name T667
Test name
Test status
Simulation time 2587833399 ps
CPU time 7.59 seconds
Started Jan 14 02:23:17 PM PST 24
Finished Jan 14 02:23:25 PM PST 24
Peak memory 202552 kb
Host smart-58453815-f6de-4ca8-987c-42809ac67dd4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813552671 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.813552671
Directory /workspace/22.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/22.sram_ctrl_regwen.1984045248
Short name T417
Test name
Test status
Simulation time 24877377179 ps
CPU time 432.7 seconds
Started Jan 14 02:24:17 PM PST 24
Finished Jan 14 02:31:37 PM PST 24
Peak memory 363636 kb
Host smart-b366dfb8-45e7-4071-b717-56af20af33de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984045248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.1984045248
Directory /workspace/22.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/22.sram_ctrl_smoke.3204948312
Short name T926
Test name
Test status
Simulation time 1400533489 ps
CPU time 37.2 seconds
Started Jan 14 02:22:55 PM PST 24
Finished Jan 14 02:23:33 PM PST 24
Peak memory 202088 kb
Host smart-03422480-96e1-4b72-901d-f3efe9e1b1bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204948312 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.3204948312
Directory /workspace/22.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.12658510
Short name T549
Test name
Test status
Simulation time 7908630803 ps
CPU time 6836.44 seconds
Started Jan 14 02:23:22 PM PST 24
Finished Jan 14 04:17:19 PM PST 24
Peak memory 698664 kb
Host smart-d8e14bc0-6a1b-4a12-a536-5d06d880bd0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=12658510 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all_with_rand_reset.12658510
Directory /workspace/22.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.sram_ctrl_stress_pipeline.83282908
Short name T462
Test name
Test status
Simulation time 3855359560 ps
CPU time 306.91 seconds
Started Jan 14 02:23:03 PM PST 24
Finished Jan 14 02:28:11 PM PST 24
Peak memory 202228 kb
Host smart-16765db1-dc91-48a7-9cd7-96e2bc208812
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83282908 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
sram_ctrl_stress_pipeline.83282908
Directory /workspace/22.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.76334241
Short name T515
Test name
Test status
Simulation time 706895916 ps
CPU time 25.37 seconds
Started Jan 14 02:23:00 PM PST 24
Finished Jan 14 02:23:26 PM PST 24
Peak memory 210368 kb
Host smart-c95930fa-5e8d-4d32-b2f1-f3a1609bce10
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76334241 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.sram_ctrl_throughput_w_partial_write.76334241
Directory /workspace/22.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/23.sram_ctrl_access_during_key_req.3471066342
Short name T431
Test name
Test status
Simulation time 41073301706 ps
CPU time 1282.81 seconds
Started Jan 14 02:23:41 PM PST 24
Finished Jan 14 02:45:04 PM PST 24
Peak memory 376980 kb
Host smart-dcd0a86e-2152-4d77-a22f-8f9336f8a158
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471066342 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 23.sram_ctrl_access_during_key_req.3471066342
Directory /workspace/23.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/23.sram_ctrl_alert_test.966004577
Short name T320
Test name
Test status
Simulation time 15045799 ps
CPU time 0.63 seconds
Started Jan 14 02:23:51 PM PST 24
Finished Jan 14 02:23:52 PM PST 24
Peak memory 201852 kb
Host smart-d59efeae-1c56-4522-a656-90009803abd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966004577 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.sram_ctrl_alert_test.966004577
Directory /workspace/23.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.sram_ctrl_bijection.3656878604
Short name T985
Test name
Test status
Simulation time 878980635005 ps
CPU time 2395.93 seconds
Started Jan 14 02:23:29 PM PST 24
Finished Jan 14 03:03:26 PM PST 24
Peak memory 202124 kb
Host smart-d904e60d-f705-4401-a8cf-ee7ce4fa3cd5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656878604 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection
.3656878604
Directory /workspace/23.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/23.sram_ctrl_executable.935311625
Short name T467
Test name
Test status
Simulation time 33942936408 ps
CPU time 501.76 seconds
Started Jan 14 02:23:39 PM PST 24
Finished Jan 14 02:32:01 PM PST 24
Peak memory 371996 kb
Host smart-4cd8bf10-d64c-4d83-828d-09ee814fd2e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935311625 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_executabl
e.935311625
Directory /workspace/23.sram_ctrl_executable/latest

Test location /workspace/coverage/default/23.sram_ctrl_lc_escalation.62135808
Short name T851
Test name
Test status
Simulation time 53209288578 ps
CPU time 129.45 seconds
Started Jan 14 02:24:23 PM PST 24
Finished Jan 14 02:26:36 PM PST 24
Peak memory 202112 kb
Host smart-a77545bd-d9e8-43d2-b560-1f6a344951b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62135808 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_esc
alation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_lc_esca
lation.62135808
Directory /workspace/23.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/23.sram_ctrl_max_throughput.62833560
Short name T759
Test name
Test status
Simulation time 1735159698 ps
CPU time 206.05 seconds
Started Jan 14 02:23:40 PM PST 24
Finished Jan 14 02:27:07 PM PST 24
Peak memory 365744 kb
Host smart-f4d3c078-ab7c-45c8-b45b-602601e6f846
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62833560 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.sram_ctrl_max_throughput.62833560
Directory /workspace/23.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/23.sram_ctrl_mem_partial_access.1650997757
Short name T448
Test name
Test status
Simulation time 4522359055 ps
CPU time 139.73 seconds
Started Jan 14 02:23:56 PM PST 24
Finished Jan 14 02:26:16 PM PST 24
Peak memory 211148 kb
Host smart-3ef01f1f-c0e2-4752-96ae-f7f3b5d729af
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650997757 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.sram_ctrl_mem_partial_access.1650997757
Directory /workspace/23.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/23.sram_ctrl_mem_walk.1136704402
Short name T690
Test name
Test status
Simulation time 74511797489 ps
CPU time 317.2 seconds
Started Jan 14 02:23:56 PM PST 24
Finished Jan 14 02:29:14 PM PST 24
Peak memory 202164 kb
Host smart-50cbf3aa-2b4e-4aa6-9e53-d7290d3c13f1
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136704402 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctr
l_mem_walk.1136704402
Directory /workspace/23.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/23.sram_ctrl_multiple_keys.2657654487
Short name T303
Test name
Test status
Simulation time 144592344442 ps
CPU time 847.7 seconds
Started Jan 14 02:23:28 PM PST 24
Finished Jan 14 02:37:37 PM PST 24
Peak memory 378872 kb
Host smart-dee75c1d-3f04-4f0e-a2f2-732e53c87d15
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657654487 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multi
ple_keys.2657654487
Directory /workspace/23.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/23.sram_ctrl_partial_access.3367810400
Short name T328
Test name
Test status
Simulation time 897560467 ps
CPU time 7.13 seconds
Started Jan 14 02:23:48 PM PST 24
Finished Jan 14 02:23:56 PM PST 24
Peak memory 202056 kb
Host smart-391e4f58-356f-4b48-adec-c0acec4202dd
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367810400 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
sram_ctrl_partial_access.3367810400
Directory /workspace/23.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.4034818953
Short name T360
Test name
Test status
Simulation time 66081727556 ps
CPU time 405.88 seconds
Started Jan 14 02:23:49 PM PST 24
Finished Jan 14 02:30:36 PM PST 24
Peak memory 202144 kb
Host smart-88e02076-84fd-4717-9c22-e0d3d08479db
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034818953 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 23.sram_ctrl_partial_access_b2b.4034818953
Directory /workspace/23.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/23.sram_ctrl_ram_cfg.2762897193
Short name T231
Test name
Test status
Simulation time 683708355 ps
CPU time 5.47 seconds
Started Jan 14 02:23:48 PM PST 24
Finished Jan 14 02:23:54 PM PST 24
Peak memory 202416 kb
Host smart-128c6f15-1551-4a11-8784-25ce5fe18c8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762897193 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.2762897193
Directory /workspace/23.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/23.sram_ctrl_smoke.3227401726
Short name T430
Test name
Test status
Simulation time 758369467 ps
CPU time 12.28 seconds
Started Jan 14 02:23:22 PM PST 24
Finished Jan 14 02:23:35 PM PST 24
Peak memory 208796 kb
Host smart-ea6d12a3-35eb-48d8-bb25-df32f9c923a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227401726 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.3227401726
Directory /workspace/23.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.3220622181
Short name T624
Test name
Test status
Simulation time 242463998 ps
CPU time 2760.78 seconds
Started Jan 14 02:23:51 PM PST 24
Finished Jan 14 03:09:53 PM PST 24
Peak memory 389588 kb
Host smart-32b302b6-1e18-465b-81f5-c458ca068a3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3220622181 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all_with_rand_reset.3220622181
Directory /workspace/23.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.sram_ctrl_stress_pipeline.4133351249
Short name T816
Test name
Test status
Simulation time 13015458655 ps
CPU time 491.35 seconds
Started Jan 14 02:23:28 PM PST 24
Finished Jan 14 02:31:40 PM PST 24
Peak memory 202196 kb
Host smart-2142a302-6387-4e7d-88e5-79d3b8e3472f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133351249 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.sram_ctrl_stress_pipeline.4133351249
Directory /workspace/23.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.838369707
Short name T958
Test name
Test status
Simulation time 2741012734 ps
CPU time 31.01 seconds
Started Jan 14 02:23:51 PM PST 24
Finished Jan 14 02:24:22 PM PST 24
Peak memory 226528 kb
Host smart-42b8fbfa-834b-421c-bfcc-4027b6ec5fc7
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838369707 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 23.sram_ctrl_throughput_w_partial_write.838369707
Directory /workspace/23.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/24.sram_ctrl_access_during_key_req.1104916845
Short name T583
Test name
Test status
Simulation time 14622163349 ps
CPU time 834.14 seconds
Started Jan 14 02:24:03 PM PST 24
Finished Jan 14 02:37:59 PM PST 24
Peak memory 374916 kb
Host smart-610e8caa-fcab-4512-8ead-274bb7ed2a91
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104916845 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 24.sram_ctrl_access_during_key_req.1104916845
Directory /workspace/24.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/24.sram_ctrl_alert_test.949321378
Short name T700
Test name
Test status
Simulation time 40584581 ps
CPU time 0.65 seconds
Started Jan 14 02:24:14 PM PST 24
Finished Jan 14 02:24:17 PM PST 24
Peak memory 201440 kb
Host smart-48224cdf-782a-4cfa-9fa2-7c5cd2eb8d04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949321378 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.sram_ctrl_alert_test.949321378
Directory /workspace/24.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.sram_ctrl_bijection.1180986336
Short name T282
Test name
Test status
Simulation time 30128675084 ps
CPU time 1018.83 seconds
Started Jan 14 02:23:57 PM PST 24
Finished Jan 14 02:40:56 PM PST 24
Peak memory 202192 kb
Host smart-e9b5cb52-59bc-4f30-a840-25363aa3bdb7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180986336 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection
.1180986336
Directory /workspace/24.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/24.sram_ctrl_executable.888204755
Short name T715
Test name
Test status
Simulation time 41735058978 ps
CPU time 250.77 seconds
Started Jan 14 02:24:04 PM PST 24
Finished Jan 14 02:28:15 PM PST 24
Peak memory 357324 kb
Host smart-e1cb98b2-1885-4eb7-a2cd-8176f4ee4a28
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888204755 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_executabl
e.888204755
Directory /workspace/24.sram_ctrl_executable/latest

Test location /workspace/coverage/default/24.sram_ctrl_max_throughput.124230659
Short name T333
Test name
Test status
Simulation time 1967410771 ps
CPU time 45.42 seconds
Started Jan 14 02:24:01 PM PST 24
Finished Jan 14 02:24:47 PM PST 24
Peak memory 274712 kb
Host smart-256b309d-7e3d-4b3a-9325-c58690de7b30
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124230659 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.sram_ctrl_max_throughput.124230659
Directory /workspace/24.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/24.sram_ctrl_mem_partial_access.348823341
Short name T129
Test name
Test status
Simulation time 2620302248 ps
CPU time 79.75 seconds
Started Jan 14 02:24:05 PM PST 24
Finished Jan 14 02:25:26 PM PST 24
Peak memory 211172 kb
Host smart-8e55c6c4-984e-41bc-9e04-831769b8865c
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348823341 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.sram_ctrl_mem_partial_access.348823341
Directory /workspace/24.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/24.sram_ctrl_mem_walk.4000501153
Short name T684
Test name
Test status
Simulation time 8568605579 ps
CPU time 244.75 seconds
Started Jan 14 02:24:07 PM PST 24
Finished Jan 14 02:28:13 PM PST 24
Peak memory 202240 kb
Host smart-ae721a59-d875-4e56-bb2b-39e76b0a9a3a
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000501153 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctr
l_mem_walk.4000501153
Directory /workspace/24.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/24.sram_ctrl_multiple_keys.1078446755
Short name T499
Test name
Test status
Simulation time 41271929803 ps
CPU time 608.86 seconds
Started Jan 14 02:23:56 PM PST 24
Finished Jan 14 02:34:05 PM PST 24
Peak memory 379392 kb
Host smart-6d4551a7-37d5-4a81-93f0-49223073ac77
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078446755 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multi
ple_keys.1078446755
Directory /workspace/24.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/24.sram_ctrl_partial_access.727638347
Short name T483
Test name
Test status
Simulation time 2388710231 ps
CPU time 24.63 seconds
Started Jan 14 02:23:56 PM PST 24
Finished Jan 14 02:24:21 PM PST 24
Peak memory 202172 kb
Host smart-c06c1524-9d7a-4fbb-bd0d-45fad033e177
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727638347 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.s
ram_ctrl_partial_access.727638347
Directory /workspace/24.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.1250388730
Short name T45
Test name
Test status
Simulation time 12069013158 ps
CPU time 308.01 seconds
Started Jan 14 02:23:58 PM PST 24
Finished Jan 14 02:29:07 PM PST 24
Peak memory 202160 kb
Host smart-f2eaf4db-a338-4968-a6ea-1fdb584ea4ba
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250388730 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 24.sram_ctrl_partial_access_b2b.1250388730
Directory /workspace/24.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/24.sram_ctrl_ram_cfg.3930527812
Short name T799
Test name
Test status
Simulation time 358812291 ps
CPU time 12.98 seconds
Started Jan 14 02:24:07 PM PST 24
Finished Jan 14 02:24:21 PM PST 24
Peak memory 202348 kb
Host smart-550d6742-344f-4dff-b6ae-ca2359256a4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930527812 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.3930527812
Directory /workspace/24.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/24.sram_ctrl_regwen.3101208526
Short name T415
Test name
Test status
Simulation time 3660503778 ps
CPU time 100.14 seconds
Started Jan 14 02:24:07 PM PST 24
Finished Jan 14 02:25:48 PM PST 24
Peak memory 298332 kb
Host smart-18b4be1b-27ad-4b92-98c9-080ba550e028
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101208526 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.3101208526
Directory /workspace/24.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/24.sram_ctrl_smoke.2502510736
Short name T329
Test name
Test status
Simulation time 3671149023 ps
CPU time 30.71 seconds
Started Jan 14 02:23:57 PM PST 24
Finished Jan 14 02:24:29 PM PST 24
Peak memory 202156 kb
Host smart-a9124202-39d2-4274-9c80-19e7688c504b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502510736 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.2502510736
Directory /workspace/24.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/24.sram_ctrl_stress_all.2831917823
Short name T122
Test name
Test status
Simulation time 205956507874 ps
CPU time 4674.72 seconds
Started Jan 14 02:24:14 PM PST 24
Finished Jan 14 03:42:11 PM PST 24
Peak memory 379112 kb
Host smart-1c510ff6-a9bf-4e34-bac8-cb25ddb520fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831917823 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 24.sram_ctrl_stress_all.2831917823
Directory /workspace/24.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.2080627898
Short name T955
Test name
Test status
Simulation time 8492222372 ps
CPU time 4157 seconds
Started Jan 14 02:24:14 PM PST 24
Finished Jan 14 03:33:34 PM PST 24
Peak memory 492480 kb
Host smart-5c693a66-8742-4576-aca2-714c3200908b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2080627898 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all_with_rand_reset.2080627898
Directory /workspace/24.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.sram_ctrl_stress_pipeline.183248568
Short name T475
Test name
Test status
Simulation time 4975057033 ps
CPU time 363.68 seconds
Started Jan 14 02:23:56 PM PST 24
Finished Jan 14 02:30:00 PM PST 24
Peak memory 202160 kb
Host smart-771affe0-6d73-43c1-892a-7c3470595c08
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183248568 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.sram_ctrl_stress_pipeline.183248568
Directory /workspace/24.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.2900752156
Short name T917
Test name
Test status
Simulation time 1591715785 ps
CPU time 118.93 seconds
Started Jan 14 02:24:03 PM PST 24
Finished Jan 14 02:26:03 PM PST 24
Peak memory 358512 kb
Host smart-e05fa408-c6f6-43bd-aa1a-b19983ac4ce2
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900752156 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 24.sram_ctrl_throughput_w_partial_write.2900752156
Directory /workspace/24.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/25.sram_ctrl_access_during_key_req.3473056641
Short name T392
Test name
Test status
Simulation time 11889633132 ps
CPU time 2416.21 seconds
Started Jan 14 02:24:35 PM PST 24
Finished Jan 14 03:04:54 PM PST 24
Peak memory 379084 kb
Host smart-14834e64-8cc3-4295-9f0b-d04e6c4ee94b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473056641 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.sram_ctrl_access_during_key_req.3473056641
Directory /workspace/25.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/25.sram_ctrl_alert_test.1869034328
Short name T740
Test name
Test status
Simulation time 18032838 ps
CPU time 0.62 seconds
Started Jan 14 02:24:36 PM PST 24
Finished Jan 14 02:24:38 PM PST 24
Peak memory 201884 kb
Host smart-8d307854-66c7-4597-88c7-fcb30eaa2912
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869034328 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.sram_ctrl_alert_test.1869034328
Directory /workspace/25.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.sram_ctrl_bijection.2677084299
Short name T406
Test name
Test status
Simulation time 90621109479 ps
CPU time 1749.41 seconds
Started Jan 14 02:24:14 PM PST 24
Finished Jan 14 02:53:25 PM PST 24
Peak memory 202252 kb
Host smart-98c48a31-48fd-4fa0-96e1-e716539cc61a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677084299 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection
.2677084299
Directory /workspace/25.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/25.sram_ctrl_executable.3942394976
Short name T570
Test name
Test status
Simulation time 64148562816 ps
CPU time 1081.77 seconds
Started Jan 14 02:24:30 PM PST 24
Finished Jan 14 02:42:34 PM PST 24
Peak memory 376040 kb
Host smart-6f87c243-5a00-4460-91c1-c546a3a4f6d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942394976 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_executab
le.3942394976
Directory /workspace/25.sram_ctrl_executable/latest

Test location /workspace/coverage/default/25.sram_ctrl_lc_escalation.768535828
Short name T981
Test name
Test status
Simulation time 5949805311 ps
CPU time 54.29 seconds
Started Jan 14 02:24:28 PM PST 24
Finished Jan 14 02:25:25 PM PST 24
Peak memory 210408 kb
Host smart-3212c7cb-f78c-467f-9625-a855cbf0ac9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768535828 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_lc_esc
alation.768535828
Directory /workspace/25.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/25.sram_ctrl_max_throughput.2718485157
Short name T782
Test name
Test status
Simulation time 868897736 ps
CPU time 70.24 seconds
Started Jan 14 02:24:25 PM PST 24
Finished Jan 14 02:25:37 PM PST 24
Peak memory 289660 kb
Host smart-9683b4c3-4e7c-49fe-87aa-4aa9846df17e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718485157 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 25.sram_ctrl_max_throughput.2718485157
Directory /workspace/25.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/25.sram_ctrl_mem_partial_access.2282061482
Short name T964
Test name
Test status
Simulation time 1962463255 ps
CPU time 75.23 seconds
Started Jan 14 02:24:34 PM PST 24
Finished Jan 14 02:25:53 PM PST 24
Peak memory 211172 kb
Host smart-c462ad1c-cdc7-4d64-8864-918f254c8f7f
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282061482 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.sram_ctrl_mem_partial_access.2282061482
Directory /workspace/25.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/25.sram_ctrl_mem_walk.4200148173
Short name T898
Test name
Test status
Simulation time 27550169068 ps
CPU time 157.75 seconds
Started Jan 14 02:24:38 PM PST 24
Finished Jan 14 02:27:18 PM PST 24
Peak memory 202380 kb
Host smart-b258c27c-e48a-4daa-8c4b-35da120ed4c9
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200148173 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctr
l_mem_walk.4200148173
Directory /workspace/25.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/25.sram_ctrl_multiple_keys.3356662223
Short name T604
Test name
Test status
Simulation time 66533767064 ps
CPU time 1453.73 seconds
Started Jan 14 02:24:15 PM PST 24
Finished Jan 14 02:48:33 PM PST 24
Peak memory 380176 kb
Host smart-e3ab207a-144f-40ca-b7b8-69338d393a13
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356662223 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multi
ple_keys.3356662223
Directory /workspace/25.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/25.sram_ctrl_partial_access.2622054498
Short name T711
Test name
Test status
Simulation time 3068633716 ps
CPU time 14.31 seconds
Started Jan 14 02:24:14 PM PST 24
Finished Jan 14 02:24:30 PM PST 24
Peak memory 202180 kb
Host smart-769a687f-e7d2-4118-b0c8-d42e0287553e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622054498 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
sram_ctrl_partial_access.2622054498
Directory /workspace/25.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.3394839451
Short name T98
Test name
Test status
Simulation time 88962604378 ps
CPU time 595.61 seconds
Started Jan 14 02:24:24 PM PST 24
Finished Jan 14 02:34:22 PM PST 24
Peak memory 210320 kb
Host smart-4885c63a-fd03-43d2-9206-66d92c9dde98
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394839451 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 25.sram_ctrl_partial_access_b2b.3394839451
Directory /workspace/25.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/25.sram_ctrl_ram_cfg.438637638
Short name T695
Test name
Test status
Simulation time 1472905153 ps
CPU time 5.95 seconds
Started Jan 14 02:24:36 PM PST 24
Finished Jan 14 02:24:44 PM PST 24
Peak memory 202460 kb
Host smart-06f86ccd-dd83-4c95-b99a-4fca15ff7df6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438637638 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.438637638
Directory /workspace/25.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/25.sram_ctrl_regwen.4195224917
Short name T586
Test name
Test status
Simulation time 1174961537 ps
CPU time 340.39 seconds
Started Jan 14 02:24:30 PM PST 24
Finished Jan 14 02:30:12 PM PST 24
Peak memory 377004 kb
Host smart-122374cd-016b-42c7-9e53-eac0542e9a02
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195224917 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.4195224917
Directory /workspace/25.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/25.sram_ctrl_smoke.2980864128
Short name T135
Test name
Test status
Simulation time 823355619 ps
CPU time 12.75 seconds
Started Jan 14 02:24:14 PM PST 24
Finished Jan 14 02:24:28 PM PST 24
Peak memory 202084 kb
Host smart-b513620d-9591-4c6f-8dde-cb19dee93bc1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980864128 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.2980864128
Directory /workspace/25.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/25.sram_ctrl_stress_all.2170176292
Short name T875
Test name
Test status
Simulation time 46397629882 ps
CPU time 3418.27 seconds
Started Jan 14 02:24:35 PM PST 24
Finished Jan 14 03:21:36 PM PST 24
Peak memory 382128 kb
Host smart-71221aca-b98d-4288-a416-40da239b1439
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170176292 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 25.sram_ctrl_stress_all.2170176292
Directory /workspace/25.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.2090137040
Short name T646
Test name
Test status
Simulation time 723464242 ps
CPU time 1885.72 seconds
Started Jan 14 02:24:35 PM PST 24
Finished Jan 14 02:56:04 PM PST 24
Peak memory 432188 kb
Host smart-6c46fdbe-e782-4a33-acdb-55ed0425aee7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2090137040 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all_with_rand_reset.2090137040
Directory /workspace/25.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.sram_ctrl_stress_pipeline.247629545
Short name T775
Test name
Test status
Simulation time 3293916148 ps
CPU time 245.43 seconds
Started Jan 14 02:24:14 PM PST 24
Finished Jan 14 02:28:22 PM PST 24
Peak memory 202048 kb
Host smart-a2c21173-57ee-4d62-a7fa-b5b29b2e142f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247629545 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.sram_ctrl_stress_pipeline.247629545
Directory /workspace/25.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.450866629
Short name T966
Test name
Test status
Simulation time 803343400 ps
CPU time 126.07 seconds
Started Jan 14 02:24:23 PM PST 24
Finished Jan 14 02:26:33 PM PST 24
Peak memory 349072 kb
Host smart-9b6756e7-7639-4c0c-8d42-336ded6d5922
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450866629 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 25.sram_ctrl_throughput_w_partial_write.450866629
Directory /workspace/25.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/26.sram_ctrl_access_during_key_req.1435896336
Short name T548
Test name
Test status
Simulation time 159358607164 ps
CPU time 2457.37 seconds
Started Jan 14 02:24:57 PM PST 24
Finished Jan 14 03:05:55 PM PST 24
Peak memory 380084 kb
Host smart-b7c16de9-8d5c-497e-a849-90cf96509f8b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435896336 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 26.sram_ctrl_access_during_key_req.1435896336
Directory /workspace/26.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/26.sram_ctrl_alert_test.2813910617
Short name T243
Test name
Test status
Simulation time 14056184 ps
CPU time 0.65 seconds
Started Jan 14 02:25:25 PM PST 24
Finished Jan 14 02:25:27 PM PST 24
Peak memory 201896 kb
Host smart-fff40e36-ffc9-43e4-9d47-f0cde0ea493f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813910617 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.sram_ctrl_alert_test.2813910617
Directory /workspace/26.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.sram_ctrl_bijection.2820880961
Short name T250
Test name
Test status
Simulation time 557656202680 ps
CPU time 680.55 seconds
Started Jan 14 02:24:46 PM PST 24
Finished Jan 14 02:36:08 PM PST 24
Peak memory 202052 kb
Host smart-114e984d-f25b-4f70-9d25-86ab74ffdcdb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820880961 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection
.2820880961
Directory /workspace/26.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/26.sram_ctrl_lc_escalation.3013274912
Short name T902
Test name
Test status
Simulation time 37196215769 ps
CPU time 248.29 seconds
Started Jan 14 02:24:56 PM PST 24
Finished Jan 14 02:29:05 PM PST 24
Peak memory 210304 kb
Host smart-4c50b57d-9b9a-4989-8287-7caa7e395a28
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013274912 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_es
calation.3013274912
Directory /workspace/26.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/26.sram_ctrl_max_throughput.1371256944
Short name T468
Test name
Test status
Simulation time 1596256939 ps
CPU time 178.02 seconds
Started Jan 14 02:24:49 PM PST 24
Finished Jan 14 02:27:49 PM PST 24
Peak memory 365752 kb
Host smart-1297f638-b4fd-4db7-bfe4-fbc3e95e825d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371256944 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 26.sram_ctrl_max_throughput.1371256944
Directory /workspace/26.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/26.sram_ctrl_mem_partial_access.3581459539
Short name T302
Test name
Test status
Simulation time 3785149979 ps
CPU time 78.26 seconds
Started Jan 14 02:25:08 PM PST 24
Finished Jan 14 02:26:27 PM PST 24
Peak memory 211316 kb
Host smart-cba2d9d5-2a1d-4a8f-a5b2-e97528ed3031
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581459539 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.sram_ctrl_mem_partial_access.3581459539
Directory /workspace/26.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/26.sram_ctrl_mem_walk.866349148
Short name T641
Test name
Test status
Simulation time 79594746650 ps
CPU time 162.43 seconds
Started Jan 14 02:25:11 PM PST 24
Finished Jan 14 02:27:54 PM PST 24
Peak memory 202188 kb
Host smart-2c53cd09-9e86-4a5b-9f6c-f4d1fe624a59
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866349148 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl
_mem_walk.866349148
Directory /workspace/26.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/26.sram_ctrl_multiple_keys.1929899182
Short name T652
Test name
Test status
Simulation time 5781230288 ps
CPU time 934.83 seconds
Started Jan 14 02:24:46 PM PST 24
Finished Jan 14 02:40:22 PM PST 24
Peak memory 381196 kb
Host smart-a23db5b5-bd78-4d7f-9b41-2d6e0077e229
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929899182 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multi
ple_keys.1929899182
Directory /workspace/26.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/26.sram_ctrl_partial_access.2575161328
Short name T507
Test name
Test status
Simulation time 1684670630 ps
CPU time 29.93 seconds
Started Jan 14 02:24:45 PM PST 24
Finished Jan 14 02:25:17 PM PST 24
Peak memory 202104 kb
Host smart-0abbcddb-a61d-4ec2-82bf-caebb21f9ae2
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575161328 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
sram_ctrl_partial_access.2575161328
Directory /workspace/26.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.1031207684
Short name T979
Test name
Test status
Simulation time 57224299627 ps
CPU time 385.27 seconds
Started Jan 14 02:24:45 PM PST 24
Finished Jan 14 02:31:12 PM PST 24
Peak memory 202116 kb
Host smart-bd1c359b-e5a0-4aa1-b5e2-a6ab6c436adb
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031207684 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 26.sram_ctrl_partial_access_b2b.1031207684
Directory /workspace/26.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/26.sram_ctrl_ram_cfg.256024397
Short name T803
Test name
Test status
Simulation time 704651214 ps
CPU time 6.94 seconds
Started Jan 14 02:25:09 PM PST 24
Finished Jan 14 02:25:17 PM PST 24
Peak memory 202436 kb
Host smart-25b609cd-d583-4af6-8282-58d28e670cbe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256024397 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.256024397
Directory /workspace/26.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/26.sram_ctrl_regwen.1452777669
Short name T636
Test name
Test status
Simulation time 9880932006 ps
CPU time 1278.6 seconds
Started Jan 14 02:24:57 PM PST 24
Finished Jan 14 02:46:16 PM PST 24
Peak memory 372928 kb
Host smart-cef98163-e0d1-4a07-b85d-0c8ff93cb264
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452777669 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.1452777669
Directory /workspace/26.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/26.sram_ctrl_smoke.3909416225
Short name T386
Test name
Test status
Simulation time 3957743709 ps
CPU time 154.35 seconds
Started Jan 14 02:24:47 PM PST 24
Finished Jan 14 02:27:22 PM PST 24
Peak memory 357572 kb
Host smart-50857071-7de4-4e2b-95ef-b1afdb5df61c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909416225 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.3909416225
Directory /workspace/26.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.2691551098
Short name T645
Test name
Test status
Simulation time 758587880 ps
CPU time 6541.31 seconds
Started Jan 14 02:25:09 PM PST 24
Finished Jan 14 04:14:12 PM PST 24
Peak memory 716928 kb
Host smart-5f4ccb2f-b34f-4cf1-a4ae-02f7d2954264
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2691551098 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all_with_rand_reset.2691551098
Directory /workspace/26.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.sram_ctrl_stress_pipeline.3808172506
Short name T984
Test name
Test status
Simulation time 1804535699 ps
CPU time 153.41 seconds
Started Jan 14 02:24:48 PM PST 24
Finished Jan 14 02:27:22 PM PST 24
Peak memory 202068 kb
Host smart-8b95bcf3-05b7-42df-b11e-66efba253337
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808172506 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.sram_ctrl_stress_pipeline.3808172506
Directory /workspace/26.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.2006952426
Short name T918
Test name
Test status
Simulation time 703575879 ps
CPU time 33.31 seconds
Started Jan 14 02:24:58 PM PST 24
Finished Jan 14 02:25:32 PM PST 24
Peak memory 234884 kb
Host smart-f408236d-3e0c-4ce8-a46c-1205189db619
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006952426 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 26.sram_ctrl_throughput_w_partial_write.2006952426
Directory /workspace/26.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/27.sram_ctrl_access_during_key_req.1908296800
Short name T514
Test name
Test status
Simulation time 41109404562 ps
CPU time 1728.72 seconds
Started Jan 14 02:25:25 PM PST 24
Finished Jan 14 02:54:15 PM PST 24
Peak memory 380156 kb
Host smart-88ccfa60-f802-4e16-ad10-0ab8a1cdde5a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908296800 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 27.sram_ctrl_access_during_key_req.1908296800
Directory /workspace/27.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/27.sram_ctrl_alert_test.14092194
Short name T948
Test name
Test status
Simulation time 43791628 ps
CPU time 0.63 seconds
Started Jan 14 02:25:25 PM PST 24
Finished Jan 14 02:25:28 PM PST 24
Peak memory 201904 kb
Host smart-58be7ebc-c0c2-40c9-b70c-1153ab9af046
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14092194 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.sram_ctrl_alert_test.14092194
Directory /workspace/27.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.sram_ctrl_bijection.3004909512
Short name T765
Test name
Test status
Simulation time 9940872689 ps
CPU time 683.16 seconds
Started Jan 14 02:26:04 PM PST 24
Finished Jan 14 02:37:28 PM PST 24
Peak memory 202100 kb
Host smart-0b0610ae-7873-4098-8aa6-2b2afcedde5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004909512 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection
.3004909512
Directory /workspace/27.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/27.sram_ctrl_executable.1527678999
Short name T125
Test name
Test status
Simulation time 33919014550 ps
CPU time 1001.67 seconds
Started Jan 14 02:25:25 PM PST 24
Finished Jan 14 02:42:08 PM PST 24
Peak memory 375844 kb
Host smart-a8a3fbab-d52b-4b43-a788-7a065da09cbb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527678999 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_executab
le.1527678999
Directory /workspace/27.sram_ctrl_executable/latest

Test location /workspace/coverage/default/27.sram_ctrl_lc_escalation.1689945465
Short name T245
Test name
Test status
Simulation time 39142351228 ps
CPU time 140.3 seconds
Started Jan 14 02:25:25 PM PST 24
Finished Jan 14 02:27:47 PM PST 24
Peak memory 210336 kb
Host smart-923e4a6c-c5a7-4ddf-b80b-6ff9ae6464be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689945465 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_lc_es
calation.1689945465
Directory /workspace/27.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/27.sram_ctrl_max_throughput.1434346420
Short name T651
Test name
Test status
Simulation time 779352090 ps
CPU time 106.4 seconds
Started Jan 14 02:25:25 PM PST 24
Finished Jan 14 02:27:13 PM PST 24
Peak memory 323832 kb
Host smart-adc5f66a-a4ac-4879-a678-433ecd3aa523
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434346420 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 27.sram_ctrl_max_throughput.1434346420
Directory /workspace/27.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/27.sram_ctrl_mem_partial_access.709653020
Short name T680
Test name
Test status
Simulation time 5001515663 ps
CPU time 164.91 seconds
Started Jan 14 02:25:25 PM PST 24
Finished Jan 14 02:28:11 PM PST 24
Peak memory 214640 kb
Host smart-96c2c069-09fc-4ab5-84da-85d626fa1976
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709653020 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.sram_ctrl_mem_partial_access.709653020
Directory /workspace/27.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/27.sram_ctrl_mem_walk.1137097414
Short name T517
Test name
Test status
Simulation time 3945547010 ps
CPU time 253.07 seconds
Started Jan 14 02:25:25 PM PST 24
Finished Jan 14 02:29:39 PM PST 24
Peak memory 202276 kb
Host smart-f7d10773-2d19-45d5-afeb-c104c2bb31dd
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137097414 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctr
l_mem_walk.1137097414
Directory /workspace/27.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/27.sram_ctrl_multiple_keys.2663602394
Short name T373
Test name
Test status
Simulation time 22671330481 ps
CPU time 236.06 seconds
Started Jan 14 02:25:24 PM PST 24
Finished Jan 14 02:29:21 PM PST 24
Peak memory 308884 kb
Host smart-5cc4c96d-7691-4a80-8ceb-ccf555d0bc24
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663602394 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multi
ple_keys.2663602394
Directory /workspace/27.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/27.sram_ctrl_partial_access.2386061185
Short name T447
Test name
Test status
Simulation time 3279631076 ps
CPU time 158.88 seconds
Started Jan 14 02:25:22 PM PST 24
Finished Jan 14 02:28:02 PM PST 24
Peak memory 373172 kb
Host smart-15c9be09-bd37-4632-83b1-9f4a8e6f3a41
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386061185 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
sram_ctrl_partial_access.2386061185
Directory /workspace/27.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.1741142247
Short name T835
Test name
Test status
Simulation time 70201454693 ps
CPU time 323.73 seconds
Started Jan 14 02:25:20 PM PST 24
Finished Jan 14 02:30:45 PM PST 24
Peak memory 202164 kb
Host smart-171364e6-a648-40d9-89b9-05519aadd062
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741142247 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 27.sram_ctrl_partial_access_b2b.1741142247
Directory /workspace/27.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/27.sram_ctrl_ram_cfg.1974519049
Short name T137
Test name
Test status
Simulation time 1406729428 ps
CPU time 5.68 seconds
Started Jan 14 02:25:26 PM PST 24
Finished Jan 14 02:25:33 PM PST 24
Peak memory 202420 kb
Host smart-deda49a3-c520-487e-b138-c19859a3f695
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974519049 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.1974519049
Directory /workspace/27.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/27.sram_ctrl_regwen.1809583004
Short name T930
Test name
Test status
Simulation time 37633843904 ps
CPU time 1363.26 seconds
Started Jan 14 02:25:25 PM PST 24
Finished Jan 14 02:48:10 PM PST 24
Peak memory 377028 kb
Host smart-2a876fcf-590c-4d77-8fe1-cd66c2bc528f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809583004 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.1809583004
Directory /workspace/27.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/27.sram_ctrl_smoke.422340003
Short name T257
Test name
Test status
Simulation time 2210831655 ps
CPU time 20.86 seconds
Started Jan 14 02:25:21 PM PST 24
Finished Jan 14 02:25:43 PM PST 24
Peak memory 202144 kb
Host smart-64908f72-3cbb-42d7-8cac-d1dda603fc57
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422340003 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.422340003
Directory /workspace/27.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.3312907481
Short name T931
Test name
Test status
Simulation time 1220734820 ps
CPU time 4849.5 seconds
Started Jan 14 02:25:25 PM PST 24
Finished Jan 14 03:46:16 PM PST 24
Peak memory 736284 kb
Host smart-91452328-9a51-4886-817c-346190856e74
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3312907481 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all_with_rand_reset.3312907481
Directory /workspace/27.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.sram_ctrl_stress_pipeline.2769328558
Short name T786
Test name
Test status
Simulation time 23469875681 ps
CPU time 419.99 seconds
Started Jan 14 02:25:20 PM PST 24
Finished Jan 14 02:32:21 PM PST 24
Peak memory 202248 kb
Host smart-dde2c4a2-2a8d-4ba5-b169-6ac12f8f6d31
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769328558 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.sram_ctrl_stress_pipeline.2769328558
Directory /workspace/27.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.2207012750
Short name T491
Test name
Test status
Simulation time 2906906211 ps
CPU time 91.87 seconds
Started Jan 14 02:25:25 PM PST 24
Finished Jan 14 02:26:59 PM PST 24
Peak memory 334032 kb
Host smart-1dd858bd-b504-4152-b3f1-92adbf3d1d61
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207012750 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 27.sram_ctrl_throughput_w_partial_write.2207012750
Directory /workspace/27.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/28.sram_ctrl_access_during_key_req.1513982377
Short name T493
Test name
Test status
Simulation time 9124094251 ps
CPU time 1644.45 seconds
Started Jan 14 02:25:42 PM PST 24
Finished Jan 14 02:53:07 PM PST 24
Peak memory 380088 kb
Host smart-c6bc1bc2-31ef-41f1-8308-7649a01b124a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513982377 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 28.sram_ctrl_access_during_key_req.1513982377
Directory /workspace/28.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/28.sram_ctrl_alert_test.1380212845
Short name T325
Test name
Test status
Simulation time 142119489 ps
CPU time 0.68 seconds
Started Jan 14 02:26:02 PM PST 24
Finished Jan 14 02:26:04 PM PST 24
Peak memory 201404 kb
Host smart-164b6c8e-3586-47b0-9004-128bd903283f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380212845 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.sram_ctrl_alert_test.1380212845
Directory /workspace/28.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.sram_ctrl_bijection.505963661
Short name T860
Test name
Test status
Simulation time 105263688344 ps
CPU time 1492.67 seconds
Started Jan 14 02:25:35 PM PST 24
Finished Jan 14 02:50:29 PM PST 24
Peak memory 202160 kb
Host smart-abb1d51c-bf3c-435f-ae6c-e7fbae729dc0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505963661 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection.
505963661
Directory /workspace/28.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/28.sram_ctrl_executable.2133565969
Short name T123
Test name
Test status
Simulation time 3775689413 ps
CPU time 204.31 seconds
Started Jan 14 02:25:43 PM PST 24
Finished Jan 14 02:29:08 PM PST 24
Peak memory 345512 kb
Host smart-2c39fb03-0523-4b92-9403-3605a0625a0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133565969 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_executab
le.2133565969
Directory /workspace/28.sram_ctrl_executable/latest

Test location /workspace/coverage/default/28.sram_ctrl_lc_escalation.2995913342
Short name T264
Test name
Test status
Simulation time 8541031011 ps
CPU time 197.95 seconds
Started Jan 14 02:25:43 PM PST 24
Finished Jan 14 02:29:01 PM PST 24
Peak memory 210428 kb
Host smart-741b5363-2cdf-4e19-acb9-73367a89caa6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995913342 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_lc_es
calation.2995913342
Directory /workspace/28.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/28.sram_ctrl_max_throughput.1466238607
Short name T581
Test name
Test status
Simulation time 800539165 ps
CPU time 177.94 seconds
Started Jan 14 02:25:37 PM PST 24
Finished Jan 14 02:28:35 PM PST 24
Peak memory 365712 kb
Host smart-5be461d2-e02f-47cf-b52d-56fa53933281
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466238607 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 28.sram_ctrl_max_throughput.1466238607
Directory /workspace/28.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/28.sram_ctrl_mem_partial_access.4042588994
Short name T697
Test name
Test status
Simulation time 2374978669 ps
CPU time 75.56 seconds
Started Jan 14 02:26:01 PM PST 24
Finished Jan 14 02:27:17 PM PST 24
Peak memory 211384 kb
Host smart-041aeb78-bd3d-4a1c-924d-8d44be6dfe63
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042588994 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
8.sram_ctrl_mem_partial_access.4042588994
Directory /workspace/28.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/28.sram_ctrl_mem_walk.1151231722
Short name T808
Test name
Test status
Simulation time 10464575572 ps
CPU time 159.29 seconds
Started Jan 14 02:26:05 PM PST 24
Finished Jan 14 02:28:45 PM PST 24
Peak memory 202268 kb
Host smart-b9fc7527-a233-40dd-a1eb-43198ba7d19e
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151231722 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctr
l_mem_walk.1151231722
Directory /workspace/28.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/28.sram_ctrl_multiple_keys.886453330
Short name T383
Test name
Test status
Simulation time 14366288726 ps
CPU time 950.06 seconds
Started Jan 14 02:25:36 PM PST 24
Finished Jan 14 02:41:27 PM PST 24
Peak memory 369924 kb
Host smart-cd000c72-df44-4000-8418-b08d9a3f5a10
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886453330 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multip
le_keys.886453330
Directory /workspace/28.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/28.sram_ctrl_partial_access.2029119709
Short name T416
Test name
Test status
Simulation time 6868593419 ps
CPU time 89.26 seconds
Started Jan 14 02:25:35 PM PST 24
Finished Jan 14 02:27:05 PM PST 24
Peak memory 332072 kb
Host smart-e55a21d8-f1bd-4f80-b586-fa13eec2cdce
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029119709 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
sram_ctrl_partial_access.2029119709
Directory /workspace/28.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.3109034137
Short name T849
Test name
Test status
Simulation time 19973523462 ps
CPU time 501.63 seconds
Started Jan 14 02:25:34 PM PST 24
Finished Jan 14 02:33:57 PM PST 24
Peak memory 202180 kb
Host smart-7fe61fba-2670-4786-b3ed-1ab61cba3c84
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109034137 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 28.sram_ctrl_partial_access_b2b.3109034137
Directory /workspace/28.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/28.sram_ctrl_ram_cfg.18977927
Short name T929
Test name
Test status
Simulation time 362641827 ps
CPU time 5.48 seconds
Started Jan 14 02:26:03 PM PST 24
Finished Jan 14 02:26:09 PM PST 24
Peak memory 202456 kb
Host smart-50709618-ab19-44ba-ad91-8f1e986bb477
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18977927 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cf
g_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.18977927
Directory /workspace/28.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/28.sram_ctrl_regwen.3628039688
Short name T610
Test name
Test status
Simulation time 87567241800 ps
CPU time 1298.67 seconds
Started Jan 14 02:25:59 PM PST 24
Finished Jan 14 02:47:39 PM PST 24
Peak memory 379068 kb
Host smart-0b6ea7fe-7513-4fb1-9469-b05ee505eb5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628039688 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.3628039688
Directory /workspace/28.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/28.sram_ctrl_smoke.2733560783
Short name T838
Test name
Test status
Simulation time 4318463297 ps
CPU time 19.54 seconds
Started Jan 14 02:25:24 PM PST 24
Finished Jan 14 02:25:44 PM PST 24
Peak memory 210376 kb
Host smart-e33a1b43-921c-4d8c-bd22-d2cb79293e69
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733560783 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.2733560783
Directory /workspace/28.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.2585052118
Short name T494
Test name
Test status
Simulation time 3818914860 ps
CPU time 2621.85 seconds
Started Jan 14 02:26:03 PM PST 24
Finished Jan 14 03:09:46 PM PST 24
Peak memory 674512 kb
Host smart-7db7728d-d73b-4698-b9ef-41c25c692e2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2585052118 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all_with_rand_reset.2585052118
Directory /workspace/28.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.sram_ctrl_stress_pipeline.492296628
Short name T707
Test name
Test status
Simulation time 10702689982 ps
CPU time 190.01 seconds
Started Jan 14 02:25:34 PM PST 24
Finished Jan 14 02:28:45 PM PST 24
Peak memory 202036 kb
Host smart-807f3ae6-b74f-4aa4-bdc8-47a8b31dbf9c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492296628 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.sram_ctrl_stress_pipeline.492296628
Directory /workspace/28.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.2085873301
Short name T597
Test name
Test status
Simulation time 710696482 ps
CPU time 39.21 seconds
Started Jan 14 02:25:42 PM PST 24
Finished Jan 14 02:26:22 PM PST 24
Peak memory 251232 kb
Host smart-b7fb2515-b84c-483d-bc74-66939ddd9004
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085873301 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.sram_ctrl_throughput_w_partial_write.2085873301
Directory /workspace/28.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/29.sram_ctrl_access_during_key_req.2003617875
Short name T886
Test name
Test status
Simulation time 8733726754 ps
CPU time 196.94 seconds
Started Jan 14 02:26:16 PM PST 24
Finished Jan 14 02:29:34 PM PST 24
Peak memory 352452 kb
Host smart-5bb4426a-3304-4394-a955-e5f6f394e943
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003617875 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 29.sram_ctrl_access_during_key_req.2003617875
Directory /workspace/29.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/29.sram_ctrl_alert_test.1438002560
Short name T426
Test name
Test status
Simulation time 14907846 ps
CPU time 0.66 seconds
Started Jan 14 02:26:31 PM PST 24
Finished Jan 14 02:26:32 PM PST 24
Peak memory 201460 kb
Host smart-4982923c-1513-422f-b596-4647ee44d82d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438002560 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.sram_ctrl_alert_test.1438002560
Directory /workspace/29.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.sram_ctrl_bijection.689172067
Short name T942
Test name
Test status
Simulation time 175062570360 ps
CPU time 2096.92 seconds
Started Jan 14 02:26:09 PM PST 24
Finished Jan 14 03:01:08 PM PST 24
Peak memory 202228 kb
Host smart-e893fb06-f3ab-43c2-ad86-81db4ce4dbbd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689172067 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection.
689172067
Directory /workspace/29.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/29.sram_ctrl_executable.743200422
Short name T833
Test name
Test status
Simulation time 17083953376 ps
CPU time 1298.76 seconds
Started Jan 14 02:26:17 PM PST 24
Finished Jan 14 02:47:56 PM PST 24
Peak memory 378964 kb
Host smart-d8986a75-f817-4dc9-b293-c585b4c7da7e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743200422 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_executabl
e.743200422
Directory /workspace/29.sram_ctrl_executable/latest

Test location /workspace/coverage/default/29.sram_ctrl_max_throughput.1498755762
Short name T259
Test name
Test status
Simulation time 2994907346 ps
CPU time 53.93 seconds
Started Jan 14 02:26:16 PM PST 24
Finished Jan 14 02:27:10 PM PST 24
Peak memory 287028 kb
Host smart-31764abd-ec2e-446b-a9e7-d82c794d69e3
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498755762 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 29.sram_ctrl_max_throughput.1498755762
Directory /workspace/29.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/29.sram_ctrl_mem_partial_access.3626698162
Short name T717
Test name
Test status
Simulation time 6349145516 ps
CPU time 78.2 seconds
Started Jan 14 02:26:31 PM PST 24
Finished Jan 14 02:27:50 PM PST 24
Peak memory 218396 kb
Host smart-ff7d3cf2-cde8-471d-a07a-50e41e391651
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626698162 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.sram_ctrl_mem_partial_access.3626698162
Directory /workspace/29.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/29.sram_ctrl_mem_walk.521961101
Short name T916
Test name
Test status
Simulation time 10337071198 ps
CPU time 161.94 seconds
Started Jan 14 02:26:31 PM PST 24
Finished Jan 14 02:29:14 PM PST 24
Peak memory 202140 kb
Host smart-d68fe838-2a12-44dd-9ec9-84e79e26a52d
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521961101 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl
_mem_walk.521961101
Directory /workspace/29.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/29.sram_ctrl_multiple_keys.3953050410
Short name T938
Test name
Test status
Simulation time 132141392611 ps
CPU time 941.91 seconds
Started Jan 14 02:26:09 PM PST 24
Finished Jan 14 02:41:53 PM PST 24
Peak memory 377052 kb
Host smart-f606b86e-9b79-41c8-bff4-212824e54da2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953050410 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multi
ple_keys.3953050410
Directory /workspace/29.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/29.sram_ctrl_partial_access.1822032243
Short name T873
Test name
Test status
Simulation time 2550500542 ps
CPU time 31.47 seconds
Started Jan 14 02:26:17 PM PST 24
Finished Jan 14 02:26:49 PM PST 24
Peak memory 202160 kb
Host smart-f68cd12e-73cb-472e-bc20-d7cb7cf2850e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822032243 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
sram_ctrl_partial_access.1822032243
Directory /workspace/29.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.286265281
Short name T829
Test name
Test status
Simulation time 16120009185 ps
CPU time 406.73 seconds
Started Jan 14 02:26:17 PM PST 24
Finished Jan 14 02:33:04 PM PST 24
Peak memory 202156 kb
Host smart-9139b118-b315-4ee5-864e-862d5054b7ab
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286265281 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.sram_ctrl_partial_access_b2b.286265281
Directory /workspace/29.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/29.sram_ctrl_ram_cfg.4197003873
Short name T268
Test name
Test status
Simulation time 4770396930 ps
CPU time 8.32 seconds
Started Jan 14 02:26:30 PM PST 24
Finished Jan 14 02:26:39 PM PST 24
Peak memory 202436 kb
Host smart-a5054349-7b94-4614-86bd-4544aef45eef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197003873 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.4197003873
Directory /workspace/29.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/29.sram_ctrl_regwen.3320875560
Short name T407
Test name
Test status
Simulation time 4170151197 ps
CPU time 376.32 seconds
Started Jan 14 02:26:36 PM PST 24
Finished Jan 14 02:32:53 PM PST 24
Peak memory 373956 kb
Host smart-ae48bb2f-3c8b-4d84-99f1-06fd6ecd5a82
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320875560 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.3320875560
Directory /workspace/29.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/29.sram_ctrl_smoke.1697702654
Short name T77
Test name
Test status
Simulation time 3737748323 ps
CPU time 34.76 seconds
Started Jan 14 02:26:04 PM PST 24
Finished Jan 14 02:26:39 PM PST 24
Peak memory 261428 kb
Host smart-f75ea47c-b049-49c2-9f38-0f3e99b5d36f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697702654 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.1697702654
Directory /workspace/29.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/29.sram_ctrl_stress_all.773474519
Short name T893
Test name
Test status
Simulation time 290205361333 ps
CPU time 7183.09 seconds
Started Jan 14 02:26:32 PM PST 24
Finished Jan 14 04:26:16 PM PST 24
Peak memory 381108 kb
Host smart-d1bdc5c7-a68f-4f17-9864-486deb4d9415
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773474519 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 29.sram_ctrl_stress_all.773474519
Directory /workspace/29.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.sram_ctrl_stress_pipeline.3642996836
Short name T233
Test name
Test status
Simulation time 24335271153 ps
CPU time 449.18 seconds
Started Jan 14 02:26:09 PM PST 24
Finished Jan 14 02:33:40 PM PST 24
Peak memory 202188 kb
Host smart-9391ea44-ec40-4083-8f86-d62213e05dcc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642996836 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.sram_ctrl_stress_pipeline.3642996836
Directory /workspace/29.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.3707683864
Short name T345
Test name
Test status
Simulation time 822294520 ps
CPU time 123.63 seconds
Started Jan 14 02:26:17 PM PST 24
Finished Jan 14 02:28:21 PM PST 24
Peak memory 356524 kb
Host smart-21256ab7-16cd-4092-ad15-adb33bd0bd23
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707683864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 29.sram_ctrl_throughput_w_partial_write.3707683864
Directory /workspace/29.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/3.sram_ctrl_access_during_key_req.3221446807
Short name T80
Test name
Test status
Simulation time 1725870198 ps
CPU time 22.87 seconds
Started Jan 14 02:13:39 PM PST 24
Finished Jan 14 02:14:02 PM PST 24
Peak memory 206824 kb
Host smart-d0f25b58-f317-4761-9748-00883af9514a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221446807 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.sram_ctrl_access_during_key_req.3221446807
Directory /workspace/3.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/3.sram_ctrl_alert_test.587730082
Short name T21
Test name
Test status
Simulation time 15971826 ps
CPU time 0.64 seconds
Started Jan 14 02:13:45 PM PST 24
Finished Jan 14 02:13:47 PM PST 24
Peak memory 201868 kb
Host smart-b7a723be-608c-4b4d-bd04-75698a77062b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587730082 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.sram_ctrl_alert_test.587730082
Directory /workspace/3.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.sram_ctrl_bijection.2316392552
Short name T790
Test name
Test status
Simulation time 110638798366 ps
CPU time 1959.06 seconds
Started Jan 14 02:13:20 PM PST 24
Finished Jan 14 02:46:00 PM PST 24
Peak memory 202144 kb
Host smart-14272f5a-4af7-48a2-ad72-ab0c8d7636ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316392552 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection.
2316392552
Directory /workspace/3.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/3.sram_ctrl_executable.2285689350
Short name T288
Test name
Test status
Simulation time 3651106773 ps
CPU time 162.54 seconds
Started Jan 14 02:13:33 PM PST 24
Finished Jan 14 02:16:16 PM PST 24
Peak memory 311368 kb
Host smart-f0e782de-b290-4582-a11a-891f8d8fa3f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285689350 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_executabl
e.2285689350
Directory /workspace/3.sram_ctrl_executable/latest

Test location /workspace/coverage/default/3.sram_ctrl_lc_escalation.3992562996
Short name T705
Test name
Test status
Simulation time 11118520861 ps
CPU time 104.98 seconds
Started Jan 14 02:13:33 PM PST 24
Finished Jan 14 02:15:18 PM PST 24
Peak memory 210396 kb
Host smart-19cc6f77-432b-49b0-830e-fc9fb93bf79d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992562996 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_esc
alation.3992562996
Directory /workspace/3.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/3.sram_ctrl_max_throughput.4225593809
Short name T625
Test name
Test status
Simulation time 787959379 ps
CPU time 137.03 seconds
Started Jan 14 02:13:38 PM PST 24
Finished Jan 14 02:15:56 PM PST 24
Peak memory 349268 kb
Host smart-816afe42-e4b2-4727-a7e1-b0c82179b14c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225593809 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 3.sram_ctrl_max_throughput.4225593809
Directory /workspace/3.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/3.sram_ctrl_mem_partial_access.3253470797
Short name T334
Test name
Test status
Simulation time 2463765442 ps
CPU time 82.88 seconds
Started Jan 14 02:13:38 PM PST 24
Finished Jan 14 02:15:02 PM PST 24
Peak memory 211108 kb
Host smart-5964bb5c-25bf-4b65-8d99-6fab99fa7127
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253470797 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.sram_ctrl_mem_partial_access.3253470797
Directory /workspace/3.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/3.sram_ctrl_mem_walk.374447641
Short name T97
Test name
Test status
Simulation time 7845610277 ps
CPU time 150.84 seconds
Started Jan 14 02:13:38 PM PST 24
Finished Jan 14 02:16:10 PM PST 24
Peak memory 202236 kb
Host smart-a95ff388-a3bc-4543-b021-772888a5de95
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374447641 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_
mem_walk.374447641
Directory /workspace/3.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/3.sram_ctrl_multiple_keys.2928798048
Short name T677
Test name
Test status
Simulation time 29452380818 ps
CPU time 1227.45 seconds
Started Jan 14 02:13:19 PM PST 24
Finished Jan 14 02:33:48 PM PST 24
Peak memory 380524 kb
Host smart-614a2d49-7d0c-418c-883a-1243fec96e95
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928798048 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multip
le_keys.2928798048
Directory /workspace/3.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/3.sram_ctrl_partial_access.2742790594
Short name T490
Test name
Test status
Simulation time 528009766 ps
CPU time 172.28 seconds
Started Jan 14 02:13:19 PM PST 24
Finished Jan 14 02:16:12 PM PST 24
Peak memory 365712 kb
Host smart-1c91aea9-8fae-44a3-a641-8a4259f4599a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742790594 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.s
ram_ctrl_partial_access.2742790594
Directory /workspace/3.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.453096619
Short name T555
Test name
Test status
Simulation time 10583697045 ps
CPU time 265.25 seconds
Started Jan 14 02:13:39 PM PST 24
Finished Jan 14 02:18:05 PM PST 24
Peak memory 202148 kb
Host smart-9bf77fbb-3792-40d5-ac31-460288ba0582
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453096619 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.sram_ctrl_partial_access_b2b.453096619
Directory /workspace/3.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/3.sram_ctrl_ram_cfg.2371614464
Short name T708
Test name
Test status
Simulation time 1403617164 ps
CPU time 13.49 seconds
Started Jan 14 02:13:32 PM PST 24
Finished Jan 14 02:13:47 PM PST 24
Peak memory 202432 kb
Host smart-0d21bf5b-a646-4d92-8088-9d064beff7d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371614464 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.2371614464
Directory /workspace/3.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/3.sram_ctrl_regwen.875549399
Short name T777
Test name
Test status
Simulation time 24641972400 ps
CPU time 971.56 seconds
Started Jan 14 02:13:42 PM PST 24
Finished Jan 14 02:29:55 PM PST 24
Peak memory 374916 kb
Host smart-ff4e8c84-f2ce-44a2-a930-e4c4293dae88
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875549399 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.875549399
Directory /workspace/3.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/3.sram_ctrl_sec_cm.1348353715
Short name T25
Test name
Test status
Simulation time 170696328 ps
CPU time 1.71 seconds
Started Jan 14 02:13:48 PM PST 24
Finished Jan 14 02:13:50 PM PST 24
Peak memory 220992 kb
Host smart-a30abe82-d92f-47f0-a9dd-d99c7e245149
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348353715 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.sram_ctrl_sec_cm.1348353715
Directory /workspace/3.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.sram_ctrl_smoke.3869747197
Short name T630
Test name
Test status
Simulation time 1327464142 ps
CPU time 183.17 seconds
Started Jan 14 02:13:25 PM PST 24
Finished Jan 14 02:16:29 PM PST 24
Peak memory 361580 kb
Host smart-2865ac6f-0fa4-4ae6-90f7-c256939b09b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869747197 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.3869747197
Directory /workspace/3.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.2506510867
Short name T890
Test name
Test status
Simulation time 6096507516 ps
CPU time 10392.1 seconds
Started Jan 14 02:13:40 PM PST 24
Finished Jan 14 05:06:55 PM PST 24
Peak memory 707588 kb
Host smart-b7c8248a-d7f7-4be5-ba02-c42a81eb74a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2506510867 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all_with_rand_reset.2506510867
Directory /workspace/3.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.sram_ctrl_stress_pipeline.4282749751
Short name T235
Test name
Test status
Simulation time 3556250821 ps
CPU time 218.08 seconds
Started Jan 14 02:13:21 PM PST 24
Finished Jan 14 02:17:00 PM PST 24
Peak memory 202184 kb
Host smart-79fbc9f7-5098-406e-92aa-6793d6ce44ab
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282749751 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.sram_ctrl_stress_pipeline.4282749751
Directory /workspace/3.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.1933218958
Short name T791
Test name
Test status
Simulation time 3018793845 ps
CPU time 27.25 seconds
Started Jan 14 02:13:40 PM PST 24
Finished Jan 14 02:14:08 PM PST 24
Peak memory 210372 kb
Host smart-8f08dbb7-6c95-4b4e-9d66-cc7d45e3145c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933218958 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.sram_ctrl_throughput_w_partial_write.1933218958
Directory /workspace/3.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/30.sram_ctrl_access_during_key_req.2384540611
Short name T265
Test name
Test status
Simulation time 88395328250 ps
CPU time 1404.68 seconds
Started Jan 14 02:26:40 PM PST 24
Finished Jan 14 02:50:06 PM PST 24
Peak memory 380144 kb
Host smart-a6b23c09-3535-4bdb-be6b-14b48ba8d91f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384540611 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.sram_ctrl_access_during_key_req.2384540611
Directory /workspace/30.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/30.sram_ctrl_alert_test.498998482
Short name T912
Test name
Test status
Simulation time 154007625 ps
CPU time 0.68 seconds
Started Jan 14 02:26:52 PM PST 24
Finished Jan 14 02:26:59 PM PST 24
Peak memory 201884 kb
Host smart-943a29ca-4736-4743-a109-2ad24278f297
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498998482 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.sram_ctrl_alert_test.498998482
Directory /workspace/30.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.sram_ctrl_bijection.1900250306
Short name T501
Test name
Test status
Simulation time 26397654073 ps
CPU time 852.77 seconds
Started Jan 14 02:26:44 PM PST 24
Finished Jan 14 02:40:58 PM PST 24
Peak memory 202148 kb
Host smart-21fbcade-3efb-42b7-be00-d8bcb5b4e04d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900250306 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection
.1900250306
Directory /workspace/30.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/30.sram_ctrl_executable.3287861727
Short name T436
Test name
Test status
Simulation time 22036449406 ps
CPU time 1118.3 seconds
Started Jan 14 02:26:42 PM PST 24
Finished Jan 14 02:45:21 PM PST 24
Peak memory 378064 kb
Host smart-36e5ccc8-bc13-4273-9d0f-36b6159bb57e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287861727 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_executab
le.3287861727
Directory /workspace/30.sram_ctrl_executable/latest

Test location /workspace/coverage/default/30.sram_ctrl_lc_escalation.3982546025
Short name T27
Test name
Test status
Simulation time 5649976289 ps
CPU time 102.06 seconds
Started Jan 14 02:26:37 PM PST 24
Finished Jan 14 02:28:20 PM PST 24
Peak memory 202208 kb
Host smart-435dce71-3574-4f85-923f-132dbd1925dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982546025 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_es
calation.3982546025
Directory /workspace/30.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/30.sram_ctrl_max_throughput.115951498
Short name T560
Test name
Test status
Simulation time 2919349556 ps
CPU time 60.11 seconds
Started Jan 14 02:26:41 PM PST 24
Finished Jan 14 02:27:42 PM PST 24
Peak memory 292248 kb
Host smart-f02be54e-03d4-4f5a-a1f7-11cb6e501473
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115951498 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.sram_ctrl_max_throughput.115951498
Directory /workspace/30.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/30.sram_ctrl_mem_partial_access.3873341086
Short name T131
Test name
Test status
Simulation time 2557017344 ps
CPU time 83 seconds
Started Jan 14 02:26:54 PM PST 24
Finished Jan 14 02:28:25 PM PST 24
Peak memory 211200 kb
Host smart-93f38afd-f3da-46ec-9b6f-26ebcd0670cc
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873341086 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.sram_ctrl_mem_partial_access.3873341086
Directory /workspace/30.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/30.sram_ctrl_mem_walk.2601393673
Short name T622
Test name
Test status
Simulation time 14370608211 ps
CPU time 284.65 seconds
Started Jan 14 02:26:52 PM PST 24
Finished Jan 14 02:31:43 PM PST 24
Peak memory 202304 kb
Host smart-12e12460-ceca-486c-9202-fd9354e96873
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601393673 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctr
l_mem_walk.2601393673
Directory /workspace/30.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/30.sram_ctrl_multiple_keys.4280108214
Short name T419
Test name
Test status
Simulation time 44590225096 ps
CPU time 942.07 seconds
Started Jan 14 02:26:44 PM PST 24
Finished Jan 14 02:42:27 PM PST 24
Peak memory 371988 kb
Host smart-90baa4e1-4782-4588-a1a3-2a18a92ebd40
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280108214 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multi
ple_keys.4280108214
Directory /workspace/30.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/30.sram_ctrl_partial_access.3947882670
Short name T429
Test name
Test status
Simulation time 1927664696 ps
CPU time 44.19 seconds
Started Jan 14 02:26:39 PM PST 24
Finished Jan 14 02:27:24 PM PST 24
Peak memory 273932 kb
Host smart-4b767cc8-f473-42b4-83b0-0dc5db4c8330
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947882670 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
sram_ctrl_partial_access.3947882670
Directory /workspace/30.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.3516783984
Short name T544
Test name
Test status
Simulation time 38485507106 ps
CPU time 529.49 seconds
Started Jan 14 02:26:41 PM PST 24
Finished Jan 14 02:35:31 PM PST 24
Peak memory 202140 kb
Host smart-3b0e23ac-bcbf-46ed-8bb7-9e3e3fd5d9dc
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516783984 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 30.sram_ctrl_partial_access_b2b.3516783984
Directory /workspace/30.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/30.sram_ctrl_ram_cfg.3991454706
Short name T681
Test name
Test status
Simulation time 360681037 ps
CPU time 5.82 seconds
Started Jan 14 02:26:43 PM PST 24
Finished Jan 14 02:26:49 PM PST 24
Peak memory 202440 kb
Host smart-60a99272-7467-43cc-8506-bcce2e6e67bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991454706 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.3991454706
Directory /workspace/30.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/30.sram_ctrl_regwen.2040256071
Short name T989
Test name
Test status
Simulation time 8292283335 ps
CPU time 754.94 seconds
Started Jan 14 02:26:48 PM PST 24
Finished Jan 14 02:39:28 PM PST 24
Peak memory 375016 kb
Host smart-53edccda-9758-4bb9-be50-3724836a960f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040256071 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.2040256071
Directory /workspace/30.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/30.sram_ctrl_smoke.3912494292
Short name T924
Test name
Test status
Simulation time 2085489339 ps
CPU time 11.38 seconds
Started Jan 14 02:26:37 PM PST 24
Finished Jan 14 02:26:49 PM PST 24
Peak memory 202120 kb
Host smart-8aa6fda3-9422-4b60-a5f6-6a90a9a01a7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912494292 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.3912494292
Directory /workspace/30.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.1891655623
Short name T617
Test name
Test status
Simulation time 1199137945 ps
CPU time 3267.13 seconds
Started Jan 14 02:26:52 PM PST 24
Finished Jan 14 03:21:26 PM PST 24
Peak memory 698612 kb
Host smart-0ae1d1de-efeb-4608-aefe-20f092b78cfd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1891655623 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all_with_rand_reset.1891655623
Directory /workspace/30.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.sram_ctrl_stress_pipeline.2302054743
Short name T464
Test name
Test status
Simulation time 3693883343 ps
CPU time 280.11 seconds
Started Jan 14 02:26:38 PM PST 24
Finished Jan 14 02:31:19 PM PST 24
Peak memory 202176 kb
Host smart-3397a3e3-3b28-4bc8-b389-1fe49355a543
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302054743 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.sram_ctrl_stress_pipeline.2302054743
Directory /workspace/30.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.2342885160
Short name T434
Test name
Test status
Simulation time 926218961 ps
CPU time 28.56 seconds
Started Jan 14 02:26:39 PM PST 24
Finished Jan 14 02:27:08 PM PST 24
Peak memory 219588 kb
Host smart-e02161a7-52d6-43a6-9ea5-b0b3fc806429
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342885160 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.sram_ctrl_throughput_w_partial_write.2342885160
Directory /workspace/30.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/31.sram_ctrl_access_during_key_req.1973116837
Short name T857
Test name
Test status
Simulation time 18430387366 ps
CPU time 996.92 seconds
Started Jan 14 02:27:20 PM PST 24
Finished Jan 14 02:44:00 PM PST 24
Peak memory 381216 kb
Host smart-d2c3cdb6-f706-4f68-be40-f4ce8329b0e9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973116837 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 31.sram_ctrl_access_during_key_req.1973116837
Directory /workspace/31.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/31.sram_ctrl_alert_test.1598122348
Short name T489
Test name
Test status
Simulation time 15721945 ps
CPU time 0.65 seconds
Started Jan 14 02:27:26 PM PST 24
Finished Jan 14 02:27:28 PM PST 24
Peak memory 201800 kb
Host smart-8e423f8f-ecec-424c-ab55-1480f1f2d369
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598122348 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.sram_ctrl_alert_test.1598122348
Directory /workspace/31.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.sram_ctrl_bijection.1904847167
Short name T887
Test name
Test status
Simulation time 76819166138 ps
CPU time 1691.9 seconds
Started Jan 14 02:26:56 PM PST 24
Finished Jan 14 02:55:13 PM PST 24
Peak memory 210288 kb
Host smart-4d9fe598-24e4-4e23-8861-b13b27de9828
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904847167 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection
.1904847167
Directory /workspace/31.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/31.sram_ctrl_lc_escalation.1811616398
Short name T846
Test name
Test status
Simulation time 13675627325 ps
CPU time 45.83 seconds
Started Jan 14 02:27:23 PM PST 24
Finished Jan 14 02:28:10 PM PST 24
Peak memory 213848 kb
Host smart-e8ee33dd-9c22-4c5d-9e9b-25b45a9912d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811616398 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_lc_es
calation.1811616398
Directory /workspace/31.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/31.sram_ctrl_max_throughput.2969913181
Short name T956
Test name
Test status
Simulation time 2830699867 ps
CPU time 78.12 seconds
Started Jan 14 02:27:10 PM PST 24
Finished Jan 14 02:28:31 PM PST 24
Peak memory 323844 kb
Host smart-8d360212-c93b-42ef-9e3a-bea1eb0146f7
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969913181 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 31.sram_ctrl_max_throughput.2969913181
Directory /workspace/31.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/31.sram_ctrl_mem_partial_access.2743038873
Short name T706
Test name
Test status
Simulation time 43528615846 ps
CPU time 81.68 seconds
Started Jan 14 02:27:21 PM PST 24
Finished Jan 14 02:28:45 PM PST 24
Peak memory 211500 kb
Host smart-b643eeaf-0bc0-47e2-8569-a5dcdb3b03fb
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743038873 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.sram_ctrl_mem_partial_access.2743038873
Directory /workspace/31.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/31.sram_ctrl_mem_walk.1504363105
Short name T919
Test name
Test status
Simulation time 2251776687 ps
CPU time 128.66 seconds
Started Jan 14 02:27:22 PM PST 24
Finished Jan 14 02:29:32 PM PST 24
Peak memory 202104 kb
Host smart-c8b06240-fe8c-46d1-adae-60e7420109f7
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504363105 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctr
l_mem_walk.1504363105
Directory /workspace/31.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/31.sram_ctrl_multiple_keys.1575305449
Short name T840
Test name
Test status
Simulation time 131373769881 ps
CPU time 1283.05 seconds
Started Jan 14 02:26:56 PM PST 24
Finished Jan 14 02:48:24 PM PST 24
Peak memory 379068 kb
Host smart-907f64f6-2548-470c-b8b4-85874a883618
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575305449 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_multi
ple_keys.1575305449
Directory /workspace/31.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/31.sram_ctrl_partial_access.4164810081
Short name T968
Test name
Test status
Simulation time 3881803765 ps
CPU time 18.15 seconds
Started Jan 14 02:27:01 PM PST 24
Finished Jan 14 02:27:24 PM PST 24
Peak memory 202100 kb
Host smart-f5ca0827-3f98-42e0-b4aa-04397e60fe88
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164810081 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
sram_ctrl_partial_access.4164810081
Directory /workspace/31.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.3802030626
Short name T675
Test name
Test status
Simulation time 76962506917 ps
CPU time 457.09 seconds
Started Jan 14 02:27:11 PM PST 24
Finished Jan 14 02:34:51 PM PST 24
Peak memory 202156 kb
Host smart-e5ab519e-59fc-41bc-a649-4f2d1cbddaca
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802030626 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 31.sram_ctrl_partial_access_b2b.3802030626
Directory /workspace/31.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/31.sram_ctrl_ram_cfg.2638540894
Short name T246
Test name
Test status
Simulation time 2596451271 ps
CPU time 6.94 seconds
Started Jan 14 02:27:21 PM PST 24
Finished Jan 14 02:27:30 PM PST 24
Peak memory 202472 kb
Host smart-5497752e-627a-4867-a283-43b9f917987e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638540894 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.2638540894
Directory /workspace/31.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/31.sram_ctrl_regwen.1190784295
Short name T694
Test name
Test status
Simulation time 2463499459 ps
CPU time 569.44 seconds
Started Jan 14 02:27:20 PM PST 24
Finished Jan 14 02:36:52 PM PST 24
Peak memory 374952 kb
Host smart-2900b839-d314-491e-bc09-0530f56793b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190784295 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.1190784295
Directory /workspace/31.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/31.sram_ctrl_smoke.3636876154
Short name T671
Test name
Test status
Simulation time 944976860 ps
CPU time 38.12 seconds
Started Jan 14 02:26:54 PM PST 24
Finished Jan 14 02:27:39 PM PST 24
Peak memory 266492 kb
Host smart-e56e7cee-c3c9-4d16-a9b2-c797e3c86777
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636876154 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.3636876154
Directory /workspace/31.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/31.sram_ctrl_stress_all.970843364
Short name T573
Test name
Test status
Simulation time 86083534958 ps
CPU time 5074.26 seconds
Started Jan 14 02:27:31 PM PST 24
Finished Jan 14 03:52:07 PM PST 24
Peak memory 381192 kb
Host smart-55b5eb0a-84cc-48a4-bc73-9644afc170e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970843364 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 31.sram_ctrl_stress_all.970843364
Directory /workspace/31.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.4095859915
Short name T729
Test name
Test status
Simulation time 9841959466 ps
CPU time 4917.9 seconds
Started Jan 14 02:27:32 PM PST 24
Finished Jan 14 03:49:32 PM PST 24
Peak memory 713400 kb
Host smart-cbdeb105-597c-4320-8a32-f998360d57b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4095859915 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all_with_rand_reset.4095859915
Directory /workspace/31.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.sram_ctrl_stress_pipeline.3292208617
Short name T885
Test name
Test status
Simulation time 4441449317 ps
CPU time 356.51 seconds
Started Jan 14 02:27:01 PM PST 24
Finished Jan 14 02:33:02 PM PST 24
Peak memory 202180 kb
Host smart-578fe760-2810-4654-a3ba-6d540da100dc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292208617 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.sram_ctrl_stress_pipeline.3292208617
Directory /workspace/31.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.735638806
Short name T241
Test name
Test status
Simulation time 740855068 ps
CPU time 41.17 seconds
Started Jan 14 02:27:23 PM PST 24
Finished Jan 14 02:28:06 PM PST 24
Peak memory 257484 kb
Host smart-a9284b59-4c48-484d-82ea-0d0f22d7028f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735638806 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 31.sram_ctrl_throughput_w_partial_write.735638806
Directory /workspace/31.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/32.sram_ctrl_access_during_key_req.3532267762
Short name T331
Test name
Test status
Simulation time 10616417324 ps
CPU time 1415.11 seconds
Started Jan 14 02:27:42 PM PST 24
Finished Jan 14 02:51:18 PM PST 24
Peak memory 379504 kb
Host smart-1031eea6-bd08-4e82-a03a-72fa9dea5f6a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532267762 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 32.sram_ctrl_access_during_key_req.3532267762
Directory /workspace/32.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/32.sram_ctrl_alert_test.4157892251
Short name T897
Test name
Test status
Simulation time 15413429 ps
CPU time 0.64 seconds
Started Jan 14 02:27:51 PM PST 24
Finished Jan 14 02:27:53 PM PST 24
Peak memory 201448 kb
Host smart-76f8fa1d-5814-4a24-870b-becd5db8393d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157892251 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.sram_ctrl_alert_test.4157892251
Directory /workspace/32.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.sram_ctrl_bijection.925047435
Short name T460
Test name
Test status
Simulation time 181753054884 ps
CPU time 2830.61 seconds
Started Jan 14 02:27:36 PM PST 24
Finished Jan 14 03:14:48 PM PST 24
Peak memory 202168 kb
Host smart-94c358ea-dbf1-415d-9dfe-23de91865eeb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925047435 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection.
925047435
Directory /workspace/32.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/32.sram_ctrl_executable.970729611
Short name T661
Test name
Test status
Simulation time 23521197898 ps
CPU time 620.02 seconds
Started Jan 14 02:27:42 PM PST 24
Finished Jan 14 02:38:03 PM PST 24
Peak memory 361628 kb
Host smart-bc587cf2-fc89-4e8f-b2fe-8c6004c812ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970729611 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_executabl
e.970729611
Directory /workspace/32.sram_ctrl_executable/latest

Test location /workspace/coverage/default/32.sram_ctrl_lc_escalation.2388374601
Short name T292
Test name
Test status
Simulation time 60780933206 ps
CPU time 304.64 seconds
Started Jan 14 02:27:44 PM PST 24
Finished Jan 14 02:32:50 PM PST 24
Peak memory 210412 kb
Host smart-72d5b0c6-e6d4-4f1c-83d3-ff9f252cb179
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388374601 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_lc_es
calation.2388374601
Directory /workspace/32.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/32.sram_ctrl_max_throughput.3056375872
Short name T571
Test name
Test status
Simulation time 1590286087 ps
CPU time 118.88 seconds
Started Jan 14 02:27:35 PM PST 24
Finished Jan 14 02:29:36 PM PST 24
Peak memory 342760 kb
Host smart-f84a833b-4947-4ed3-adf4-613ff2f79af2
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056375872 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 32.sram_ctrl_max_throughput.3056375872
Directory /workspace/32.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/32.sram_ctrl_mem_partial_access.1400316549
Short name T766
Test name
Test status
Simulation time 3481399233 ps
CPU time 84.58 seconds
Started Jan 14 02:27:52 PM PST 24
Finished Jan 14 02:29:18 PM PST 24
Peak memory 211260 kb
Host smart-a226f41e-4398-47e2-b7da-b9994250ed73
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400316549 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.sram_ctrl_mem_partial_access.1400316549
Directory /workspace/32.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/32.sram_ctrl_mem_walk.3985181226
Short name T878
Test name
Test status
Simulation time 57301593713 ps
CPU time 292.37 seconds
Started Jan 14 02:27:50 PM PST 24
Finished Jan 14 02:32:44 PM PST 24
Peak memory 202276 kb
Host smart-d3731763-2c6b-43a1-a939-c816479118cf
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985181226 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctr
l_mem_walk.3985181226
Directory /workspace/32.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/32.sram_ctrl_multiple_keys.2505770538
Short name T532
Test name
Test status
Simulation time 11727678669 ps
CPU time 1269.84 seconds
Started Jan 14 02:27:33 PM PST 24
Finished Jan 14 02:48:44 PM PST 24
Peak memory 380076 kb
Host smart-7f716e3f-6a57-4684-b2d4-124d00fd32f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505770538 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multi
ple_keys.2505770538
Directory /workspace/32.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/32.sram_ctrl_partial_access.2880896561
Short name T882
Test name
Test status
Simulation time 20399325256 ps
CPU time 23.33 seconds
Started Jan 14 02:27:37 PM PST 24
Finished Jan 14 02:28:01 PM PST 24
Peak memory 202160 kb
Host smart-80b6f5fc-2f30-43cd-b4f0-988af01ee564
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880896561 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
sram_ctrl_partial_access.2880896561
Directory /workspace/32.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.4046438041
Short name T402
Test name
Test status
Simulation time 13421856697 ps
CPU time 218.29 seconds
Started Jan 14 02:27:36 PM PST 24
Finished Jan 14 02:31:15 PM PST 24
Peak memory 202128 kb
Host smart-11abd725-9829-4d66-91ea-30f4771a969c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046438041 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 32.sram_ctrl_partial_access_b2b.4046438041
Directory /workspace/32.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/32.sram_ctrl_ram_cfg.986635724
Short name T618
Test name
Test status
Simulation time 368061803 ps
CPU time 6.6 seconds
Started Jan 14 02:27:42 PM PST 24
Finished Jan 14 02:27:49 PM PST 24
Peak memory 202400 kb
Host smart-15f4ffc4-9c67-471d-8d4c-6b4c38b0c0b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986635724 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.986635724
Directory /workspace/32.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/32.sram_ctrl_regwen.245274852
Short name T969
Test name
Test status
Simulation time 7539373490 ps
CPU time 612.9 seconds
Started Jan 14 02:27:42 PM PST 24
Finished Jan 14 02:37:56 PM PST 24
Peak memory 369824 kb
Host smart-c69662a0-3cf4-4a67-aaf2-755be3dfe6f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245274852 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.245274852
Directory /workspace/32.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/32.sram_ctrl_smoke.3350705973
Short name T904
Test name
Test status
Simulation time 1620799484 ps
CPU time 25.68 seconds
Started Jan 14 02:27:29 PM PST 24
Finished Jan 14 02:27:57 PM PST 24
Peak memory 202072 kb
Host smart-0de4ee6e-92aa-4b7e-b4a2-9f4a98978461
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350705973 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.3350705973
Directory /workspace/32.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.450405747
Short name T295
Test name
Test status
Simulation time 697654735 ps
CPU time 3015.97 seconds
Started Jan 14 02:27:50 PM PST 24
Finished Jan 14 03:18:09 PM PST 24
Peak memory 694656 kb
Host smart-0bd5d66e-1728-4436-9560-3bc745861a57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=450405747 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all_with_rand_reset.450405747
Directory /workspace/32.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.sram_ctrl_stress_pipeline.343535169
Short name T862
Test name
Test status
Simulation time 10400793479 ps
CPU time 346.4 seconds
Started Jan 14 02:27:37 PM PST 24
Finished Jan 14 02:33:24 PM PST 24
Peak memory 202160 kb
Host smart-f48d5aca-745e-4bff-9723-2444b8651eda
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343535169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.sram_ctrl_stress_pipeline.343535169
Directory /workspace/32.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.3345931784
Short name T714
Test name
Test status
Simulation time 820724633 ps
CPU time 211.03 seconds
Started Jan 14 02:27:35 PM PST 24
Finished Jan 14 02:31:08 PM PST 24
Peak memory 368804 kb
Host smart-51c30ea7-785f-4b65-99ba-9543a76c75c9
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345931784 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.sram_ctrl_throughput_w_partial_write.3345931784
Directory /workspace/32.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/33.sram_ctrl_access_during_key_req.953993333
Short name T927
Test name
Test status
Simulation time 55445849502 ps
CPU time 1247.35 seconds
Started Jan 14 02:28:01 PM PST 24
Finished Jan 14 02:48:50 PM PST 24
Peak memory 379080 kb
Host smart-0d47ddb0-82e8-46bf-8686-f3dec250de58
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953993333 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 33.sram_ctrl_access_during_key_req.953993333
Directory /workspace/33.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/33.sram_ctrl_alert_test.2534881970
Short name T20
Test name
Test status
Simulation time 133338811 ps
CPU time 0.66 seconds
Started Jan 14 02:28:14 PM PST 24
Finished Jan 14 02:28:15 PM PST 24
Peak memory 201456 kb
Host smart-24677e3d-d5d1-4285-83db-bb7d2b804923
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534881970 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.sram_ctrl_alert_test.2534881970
Directory /workspace/33.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.sram_ctrl_bijection.2044884816
Short name T279
Test name
Test status
Simulation time 37633598613 ps
CPU time 704.54 seconds
Started Jan 14 02:27:57 PM PST 24
Finished Jan 14 02:39:43 PM PST 24
Peak memory 202256 kb
Host smart-0e62c999-ee9f-406c-9eaa-e8c5e16b09e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044884816 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection
.2044884816
Directory /workspace/33.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/33.sram_ctrl_executable.3909102671
Short name T825
Test name
Test status
Simulation time 113351476236 ps
CPU time 847.7 seconds
Started Jan 14 02:28:07 PM PST 24
Finished Jan 14 02:42:16 PM PST 24
Peak memory 365740 kb
Host smart-98e11782-e8f6-43e7-94c8-18209e6903ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909102671 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_executab
le.3909102671
Directory /workspace/33.sram_ctrl_executable/latest

Test location /workspace/coverage/default/33.sram_ctrl_lc_escalation.1297052592
Short name T7
Test name
Test status
Simulation time 34523174298 ps
CPU time 71.41 seconds
Started Jan 14 02:28:02 PM PST 24
Finished Jan 14 02:29:15 PM PST 24
Peak memory 214008 kb
Host smart-47e113c9-81ba-4420-96cf-ce12e9e4663f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297052592 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_es
calation.1297052592
Directory /workspace/33.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/33.sram_ctrl_max_throughput.1064863589
Short name T635
Test name
Test status
Simulation time 3137695414 ps
CPU time 69.69 seconds
Started Jan 14 02:28:02 PM PST 24
Finished Jan 14 02:29:13 PM PST 24
Peak memory 296328 kb
Host smart-7aa4cb8b-3897-43e0-af19-bdcd4ff46f67
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064863589 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 33.sram_ctrl_max_throughput.1064863589
Directory /workspace/33.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/33.sram_ctrl_mem_partial_access.884842342
Short name T274
Test name
Test status
Simulation time 17517681383 ps
CPU time 169.32 seconds
Started Jan 14 02:28:08 PM PST 24
Finished Jan 14 02:30:59 PM PST 24
Peak memory 211168 kb
Host smart-c7491ce3-d4f6-43ab-a0a3-f16588f99305
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884842342 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.sram_ctrl_mem_partial_access.884842342
Directory /workspace/33.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/33.sram_ctrl_mem_walk.2757491101
Short name T965
Test name
Test status
Simulation time 21753748365 ps
CPU time 318.44 seconds
Started Jan 14 02:28:08 PM PST 24
Finished Jan 14 02:33:27 PM PST 24
Peak memory 202168 kb
Host smart-138a6317-4d2a-40f1-a8ee-bbfa405d38f2
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757491101 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctr
l_mem_walk.2757491101
Directory /workspace/33.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/33.sram_ctrl_multiple_keys.3628721569
Short name T519
Test name
Test status
Simulation time 8958187539 ps
CPU time 673.59 seconds
Started Jan 14 02:27:51 PM PST 24
Finished Jan 14 02:39:07 PM PST 24
Peak memory 371848 kb
Host smart-7bc5cf6d-bdf1-4d1b-ad67-155b400f0da4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628721569 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multi
ple_keys.3628721569
Directory /workspace/33.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/33.sram_ctrl_partial_access.892346259
Short name T692
Test name
Test status
Simulation time 924714226 ps
CPU time 39.5 seconds
Started Jan 14 02:27:59 PM PST 24
Finished Jan 14 02:28:40 PM PST 24
Peak memory 202132 kb
Host smart-ba156f52-b614-4cda-8d46-a88ab6f5a443
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892346259 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.s
ram_ctrl_partial_access.892346259
Directory /workspace/33.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.929979967
Short name T574
Test name
Test status
Simulation time 77634130664 ps
CPU time 442.07 seconds
Started Jan 14 02:28:09 PM PST 24
Finished Jan 14 02:35:33 PM PST 24
Peak memory 202108 kb
Host smart-57aaf4f7-2e2f-40a2-a40a-9acee590e329
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929979967 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.sram_ctrl_partial_access_b2b.929979967
Directory /workspace/33.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/33.sram_ctrl_ram_cfg.1051211007
Short name T298
Test name
Test status
Simulation time 3713421274 ps
CPU time 14.64 seconds
Started Jan 14 02:28:03 PM PST 24
Finished Jan 14 02:28:19 PM PST 24
Peak memory 202484 kb
Host smart-0a9cc06f-cd5d-4ee3-a4b1-3dbcd8d65517
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051211007 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.1051211007
Directory /workspace/33.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/33.sram_ctrl_regwen.3967367918
Short name T127
Test name
Test status
Simulation time 3015980060 ps
CPU time 957.61 seconds
Started Jan 14 02:28:01 PM PST 24
Finished Jan 14 02:44:00 PM PST 24
Peak memory 374964 kb
Host smart-221e21e5-8864-4590-aadc-a63ac0e33ad6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967367918 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.3967367918
Directory /workspace/33.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/33.sram_ctrl_smoke.3499262013
Short name T9
Test name
Test status
Simulation time 568786695 ps
CPU time 29.34 seconds
Started Jan 14 02:27:55 PM PST 24
Finished Jan 14 02:28:25 PM PST 24
Peak memory 202084 kb
Host smart-1cc1ce08-92e9-4b0b-8d41-51f01aa3e07a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499262013 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.3499262013
Directory /workspace/33.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/33.sram_ctrl_stress_all.115575906
Short name T987
Test name
Test status
Simulation time 278317334559 ps
CPU time 4547.83 seconds
Started Jan 14 02:28:07 PM PST 24
Finished Jan 14 03:43:56 PM PST 24
Peak memory 381188 kb
Host smart-57659e2d-2e38-4ffd-b326-cfae84e7a278
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115575906 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 33.sram_ctrl_stress_all.115575906
Directory /workspace/33.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.1427446296
Short name T547
Test name
Test status
Simulation time 1072541442 ps
CPU time 2147.68 seconds
Started Jan 14 02:28:08 PM PST 24
Finished Jan 14 03:03:57 PM PST 24
Peak memory 402364 kb
Host smart-d6b702fd-8e9b-48d2-8986-bb31010aae02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1427446296 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all_with_rand_reset.1427446296
Directory /workspace/33.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.sram_ctrl_stress_pipeline.146488039
Short name T355
Test name
Test status
Simulation time 3568492643 ps
CPU time 284.11 seconds
Started Jan 14 02:27:51 PM PST 24
Finished Jan 14 02:32:37 PM PST 24
Peak memory 202164 kb
Host smart-4a8b98f8-972b-4dd0-9b8b-0d381b95d249
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146488039 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.sram_ctrl_stress_pipeline.146488039
Directory /workspace/33.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.942107631
Short name T96
Test name
Test status
Simulation time 1610302594 ps
CPU time 135.6 seconds
Started Jan 14 02:28:00 PM PST 24
Finished Jan 14 02:30:17 PM PST 24
Peak memory 353444 kb
Host smart-0828b2b0-0a63-45cd-a950-1684cb606a5f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942107631 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 33.sram_ctrl_throughput_w_partial_write.942107631
Directory /workspace/33.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/34.sram_ctrl_access_during_key_req.822630480
Short name T888
Test name
Test status
Simulation time 5598195763 ps
CPU time 777.7 seconds
Started Jan 14 02:28:19 PM PST 24
Finished Jan 14 02:41:17 PM PST 24
Peak memory 368892 kb
Host smart-a826dab5-c558-4791-a052-884be2840af3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822630480 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 34.sram_ctrl_access_during_key_req.822630480
Directory /workspace/34.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/34.sram_ctrl_alert_test.610607845
Short name T594
Test name
Test status
Simulation time 43498933 ps
CPU time 0.62 seconds
Started Jan 14 02:28:35 PM PST 24
Finished Jan 14 02:28:36 PM PST 24
Peak memory 201440 kb
Host smart-d14341ef-0125-4fb1-bbe9-5a22fa46ef46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610607845 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.sram_ctrl_alert_test.610607845
Directory /workspace/34.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.sram_ctrl_bijection.1986937538
Short name T495
Test name
Test status
Simulation time 121559375531 ps
CPU time 2216.71 seconds
Started Jan 14 02:28:14 PM PST 24
Finished Jan 14 03:05:11 PM PST 24
Peak memory 202176 kb
Host smart-8a560bc1-c0b8-4b2d-893d-8390a2c20f19
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986937538 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection
.1986937538
Directory /workspace/34.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/34.sram_ctrl_executable.76201016
Short name T522
Test name
Test status
Simulation time 140775367272 ps
CPU time 1037.55 seconds
Started Jan 14 02:28:25 PM PST 24
Finished Jan 14 02:45:43 PM PST 24
Peak memory 374964 kb
Host smart-99e96709-024b-49a7-a1af-a523546aeb17
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76201016 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execut
able_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_executable
.76201016
Directory /workspace/34.sram_ctrl_executable/latest

Test location /workspace/coverage/default/34.sram_ctrl_lc_escalation.3747971159
Short name T537
Test name
Test status
Simulation time 20166114604 ps
CPU time 121.55 seconds
Started Jan 14 02:28:20 PM PST 24
Finished Jan 14 02:30:22 PM PST 24
Peak memory 213592 kb
Host smart-6266f437-5326-474e-9645-dbaa0365943f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747971159 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_es
calation.3747971159
Directory /workspace/34.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/34.sram_ctrl_max_throughput.3706822387
Short name T424
Test name
Test status
Simulation time 2906212896 ps
CPU time 76.68 seconds
Started Jan 14 02:28:16 PM PST 24
Finished Jan 14 02:29:34 PM PST 24
Peak memory 302440 kb
Host smart-8ffdd36f-026c-492c-9b70-2de4bea8b516
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706822387 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 34.sram_ctrl_max_throughput.3706822387
Directory /workspace/34.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/34.sram_ctrl_mem_partial_access.876516664
Short name T384
Test name
Test status
Simulation time 1013866512 ps
CPU time 75.83 seconds
Started Jan 14 02:28:35 PM PST 24
Finished Jan 14 02:29:52 PM PST 24
Peak memory 211032 kb
Host smart-bda6e207-6cfe-41d4-bca5-09a951ac0f96
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876516664 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.sram_ctrl_mem_partial_access.876516664
Directory /workspace/34.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/34.sram_ctrl_mem_walk.1475056190
Short name T500
Test name
Test status
Simulation time 14099153874 ps
CPU time 126.73 seconds
Started Jan 14 02:28:26 PM PST 24
Finished Jan 14 02:30:34 PM PST 24
Peak memory 202224 kb
Host smart-32afc668-f8d1-4034-b66f-0c41f5783784
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475056190 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctr
l_mem_walk.1475056190
Directory /workspace/34.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/34.sram_ctrl_multiple_keys.1194088039
Short name T229
Test name
Test status
Simulation time 9843495372 ps
CPU time 1095.5 seconds
Started Jan 14 02:28:12 PM PST 24
Finished Jan 14 02:46:29 PM PST 24
Peak memory 375784 kb
Host smart-2eee5cbc-b6ae-40f8-b105-00e5518a8ee9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194088039 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multi
ple_keys.1194088039
Directory /workspace/34.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/34.sram_ctrl_partial_access.1917352105
Short name T335
Test name
Test status
Simulation time 7172310177 ps
CPU time 32.91 seconds
Started Jan 14 02:28:12 PM PST 24
Finished Jan 14 02:28:46 PM PST 24
Peak memory 202064 kb
Host smart-0912a10c-6abf-4d75-91b5-f75130454dcf
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917352105 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
sram_ctrl_partial_access.1917352105
Directory /workspace/34.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.1211840690
Short name T696
Test name
Test status
Simulation time 45378808578 ps
CPU time 384.48 seconds
Started Jan 14 02:28:15 PM PST 24
Finished Jan 14 02:34:40 PM PST 24
Peak memory 202180 kb
Host smart-ee2ebc60-bac4-4079-a8c6-02cf75515eba
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211840690 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 34.sram_ctrl_partial_access_b2b.1211840690
Directory /workspace/34.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/34.sram_ctrl_ram_cfg.3904204403
Short name T850
Test name
Test status
Simulation time 1365627353 ps
CPU time 6.6 seconds
Started Jan 14 02:28:29 PM PST 24
Finished Jan 14 02:28:36 PM PST 24
Peak memory 202432 kb
Host smart-657dff49-d1fa-4261-b7e9-f47f21f232cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904204403 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.3904204403
Directory /workspace/34.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/34.sram_ctrl_regwen.2747162105
Short name T582
Test name
Test status
Simulation time 32589282542 ps
CPU time 797.11 seconds
Started Jan 14 02:28:29 PM PST 24
Finished Jan 14 02:41:47 PM PST 24
Peak memory 380052 kb
Host smart-3a44f86e-e816-4dd4-ad2f-7c6def0d11ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747162105 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.2747162105
Directory /workspace/34.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/34.sram_ctrl_smoke.224721157
Short name T800
Test name
Test status
Simulation time 1303342403 ps
CPU time 21.23 seconds
Started Jan 14 02:28:07 PM PST 24
Finished Jan 14 02:28:29 PM PST 24
Peak memory 202060 kb
Host smart-2e10afe1-8b56-4702-b414-d006fcec2757
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224721157 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.224721157
Directory /workspace/34.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.478231901
Short name T771
Test name
Test status
Simulation time 1504414798 ps
CPU time 5006.9 seconds
Started Jan 14 02:28:35 PM PST 24
Finished Jan 14 03:52:04 PM PST 24
Peak memory 674680 kb
Host smart-c28b03cc-c681-45a0-8502-b74c80142f1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=478231901 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all_with_rand_reset.478231901
Directory /workspace/34.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.sram_ctrl_stress_pipeline.911813273
Short name T845
Test name
Test status
Simulation time 6809586560 ps
CPU time 228.89 seconds
Started Jan 14 02:28:12 PM PST 24
Finished Jan 14 02:32:02 PM PST 24
Peak memory 202124 kb
Host smart-72c649ba-8f85-439d-a7ee-ed48649a9f9f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911813273 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.sram_ctrl_stress_pipeline.911813273
Directory /workspace/34.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.3373702850
Short name T136
Test name
Test status
Simulation time 2939729949 ps
CPU time 65.06 seconds
Started Jan 14 02:28:19 PM PST 24
Finished Jan 14 02:29:25 PM PST 24
Peak memory 298316 kb
Host smart-978a9558-c0f1-4749-8100-d4d14cadf135
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373702850 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.sram_ctrl_throughput_w_partial_write.3373702850
Directory /workspace/34.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/35.sram_ctrl_access_during_key_req.2750807602
Short name T982
Test name
Test status
Simulation time 17083802100 ps
CPU time 896.82 seconds
Started Jan 14 02:28:52 PM PST 24
Finished Jan 14 02:43:49 PM PST 24
Peak memory 363828 kb
Host smart-33fba8f2-6d08-44d8-b8eb-5c3fb215e910
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750807602 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.sram_ctrl_access_during_key_req.2750807602
Directory /workspace/35.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/35.sram_ctrl_alert_test.487416593
Short name T911
Test name
Test status
Simulation time 21604173 ps
CPU time 0.65 seconds
Started Jan 14 02:28:52 PM PST 24
Finished Jan 14 02:28:53 PM PST 24
Peak memory 201844 kb
Host smart-20f20c07-30ae-4dc3-8719-56a293747987
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487416593 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.sram_ctrl_alert_test.487416593
Directory /workspace/35.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.sram_ctrl_bijection.2849756393
Short name T580
Test name
Test status
Simulation time 90481397073 ps
CPU time 1683.57 seconds
Started Jan 14 02:28:35 PM PST 24
Finished Jan 14 02:56:39 PM PST 24
Peak memory 202120 kb
Host smart-371be256-750c-4099-ae53-133f3b21cbcd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849756393 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection
.2849756393
Directory /workspace/35.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/35.sram_ctrl_lc_escalation.793677204
Short name T941
Test name
Test status
Simulation time 3517761627 ps
CPU time 35.99 seconds
Started Jan 14 02:28:52 PM PST 24
Finished Jan 14 02:29:29 PM PST 24
Peak memory 210404 kb
Host smart-4f19a405-7c2d-452f-b594-6f9113f587b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793677204 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_esc
alation.793677204
Directory /workspace/35.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/35.sram_ctrl_max_throughput.1005519739
Short name T654
Test name
Test status
Simulation time 767786827 ps
CPU time 170.48 seconds
Started Jan 14 02:28:48 PM PST 24
Finished Jan 14 02:31:39 PM PST 24
Peak memory 366832 kb
Host smart-a47280b2-048a-4aa7-859c-992955fcb918
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005519739 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 35.sram_ctrl_max_throughput.1005519739
Directory /workspace/35.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/35.sram_ctrl_mem_partial_access.1430975630
Short name T13
Test name
Test status
Simulation time 5043897437 ps
CPU time 82.07 seconds
Started Jan 14 02:28:52 PM PST 24
Finished Jan 14 02:30:14 PM PST 24
Peak memory 211088 kb
Host smart-a8f1702c-181b-4bb7-841d-64a78e1e0095
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430975630 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.sram_ctrl_mem_partial_access.1430975630
Directory /workspace/35.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/35.sram_ctrl_mem_walk.757355967
Short name T867
Test name
Test status
Simulation time 41337489798 ps
CPU time 164.82 seconds
Started Jan 14 02:28:53 PM PST 24
Finished Jan 14 02:31:39 PM PST 24
Peak memory 202140 kb
Host smart-c523dd36-f512-43da-bd8a-a1ad41870cec
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757355967 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl
_mem_walk.757355967
Directory /workspace/35.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/35.sram_ctrl_multiple_keys.2451835190
Short name T891
Test name
Test status
Simulation time 3286075589 ps
CPU time 57.31 seconds
Started Jan 14 02:28:35 PM PST 24
Finished Jan 14 02:29:34 PM PST 24
Peak memory 253688 kb
Host smart-863d33ea-713d-480d-8ced-ef76c41f7b5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451835190 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multi
ple_keys.2451835190
Directory /workspace/35.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/35.sram_ctrl_partial_access.4242894410
Short name T872
Test name
Test status
Simulation time 5330182902 ps
CPU time 27.85 seconds
Started Jan 14 02:28:58 PM PST 24
Finished Jan 14 02:29:27 PM PST 24
Peak memory 202204 kb
Host smart-4763ab98-7d51-40c7-b210-99d8fda3c3fc
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242894410 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
sram_ctrl_partial_access.4242894410
Directory /workspace/35.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/35.sram_ctrl_regwen.2868349540
Short name T567
Test name
Test status
Simulation time 59722952649 ps
CPU time 713.63 seconds
Started Jan 14 02:28:50 PM PST 24
Finished Jan 14 02:40:44 PM PST 24
Peak memory 377076 kb
Host smart-8e6d93cd-7787-4fb0-9ee9-94025a684615
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868349540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.2868349540
Directory /workspace/35.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/35.sram_ctrl_smoke.3066908077
Short name T286
Test name
Test status
Simulation time 956430471 ps
CPU time 19.12 seconds
Started Jan 14 02:28:39 PM PST 24
Finished Jan 14 02:28:59 PM PST 24
Peak memory 202088 kb
Host smart-522b1a15-b99f-459d-9641-3f656594e921
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066908077 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.3066908077
Directory /workspace/35.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/35.sram_ctrl_stress_all.3128416779
Short name T338
Test name
Test status
Simulation time 60482856692 ps
CPU time 5170.55 seconds
Started Jan 14 02:28:58 PM PST 24
Finished Jan 14 03:55:10 PM PST 24
Peak memory 380064 kb
Host smart-8e43f699-125c-4892-8ba7-3cd5e9559c96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128416779 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 35.sram_ctrl_stress_all.3128416779
Directory /workspace/35.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.1991846918
Short name T269
Test name
Test status
Simulation time 9035903963 ps
CPU time 4185.68 seconds
Started Jan 14 02:28:56 PM PST 24
Finished Jan 14 03:38:43 PM PST 24
Peak memory 555864 kb
Host smart-ff4453aa-00e4-4d92-bbde-12accbeb473e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1991846918 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all_with_rand_reset.1991846918
Directory /workspace/35.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.sram_ctrl_stress_pipeline.1015679701
Short name T291
Test name
Test status
Simulation time 3663704764 ps
CPU time 259.71 seconds
Started Jan 14 02:29:03 PM PST 24
Finished Jan 14 02:33:23 PM PST 24
Peak memory 202200 kb
Host smart-bb9d6de6-d25e-478a-8114-6ecbcff79340
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015679701 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.sram_ctrl_stress_pipeline.1015679701
Directory /workspace/35.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.3025816837
Short name T773
Test name
Test status
Simulation time 816840445 ps
CPU time 193.33 seconds
Started Jan 14 02:28:46 PM PST 24
Finished Jan 14 02:32:01 PM PST 24
Peak memory 365808 kb
Host smart-755051ab-0473-4fe2-a716-d0a9fa8e4052
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025816837 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.sram_ctrl_throughput_w_partial_write.3025816837
Directory /workspace/35.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/36.sram_ctrl_access_during_key_req.1797974321
Short name T394
Test name
Test status
Simulation time 10291588972 ps
CPU time 1150.36 seconds
Started Jan 14 02:29:06 PM PST 24
Finished Jan 14 02:48:17 PM PST 24
Peak memory 380284 kb
Host smart-e59b695b-536a-4ed5-9d2f-8d663cd99a8e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797974321 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 36.sram_ctrl_access_during_key_req.1797974321
Directory /workspace/36.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/36.sram_ctrl_alert_test.3640786793
Short name T266
Test name
Test status
Simulation time 16626374 ps
CPU time 0.68 seconds
Started Jan 14 02:29:14 PM PST 24
Finished Jan 14 02:29:15 PM PST 24
Peak memory 201820 kb
Host smart-983d0b1a-94a8-40b0-b345-97da30241c88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640786793 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.sram_ctrl_alert_test.3640786793
Directory /workspace/36.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.sram_ctrl_bijection.158381993
Short name T668
Test name
Test status
Simulation time 79110606004 ps
CPU time 1880.6 seconds
Started Jan 14 02:29:02 PM PST 24
Finished Jan 14 03:00:23 PM PST 24
Peak memory 202184 kb
Host smart-47eb0c4c-4496-460f-a103-605b6ef49a4c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158381993 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection.
158381993
Directory /workspace/36.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/36.sram_ctrl_executable.3266468869
Short name T858
Test name
Test status
Simulation time 14236266051 ps
CPU time 837.57 seconds
Started Jan 14 02:29:07 PM PST 24
Finished Jan 14 02:43:05 PM PST 24
Peak memory 376068 kb
Host smart-e5ef515c-a134-4de6-8e9f-169c973eb882
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266468869 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executab
le.3266468869
Directory /workspace/36.sram_ctrl_executable/latest

Test location /workspace/coverage/default/36.sram_ctrl_lc_escalation.61588309
Short name T905
Test name
Test status
Simulation time 13798969769 ps
CPU time 153.42 seconds
Started Jan 14 02:29:04 PM PST 24
Finished Jan 14 02:31:39 PM PST 24
Peak memory 210272 kb
Host smart-0829d8fa-42ac-46c6-9100-67d45f94f3df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61588309 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_esc
alation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_lc_esca
lation.61588309
Directory /workspace/36.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/36.sram_ctrl_max_throughput.2412184714
Short name T811
Test name
Test status
Simulation time 746528998 ps
CPU time 104.81 seconds
Started Jan 14 02:29:03 PM PST 24
Finished Jan 14 02:30:48 PM PST 24
Peak memory 337048 kb
Host smart-133da86a-3d85-4ec6-a656-31ea86623bf9
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412184714 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 36.sram_ctrl_max_throughput.2412184714
Directory /workspace/36.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/36.sram_ctrl_mem_partial_access.2880478987
Short name T42
Test name
Test status
Simulation time 3955266085 ps
CPU time 74.64 seconds
Started Jan 14 02:29:14 PM PST 24
Finished Jan 14 02:30:30 PM PST 24
Peak memory 211212 kb
Host smart-4b358fcf-e30e-407e-add1-294cdc94fc76
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880478987 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.sram_ctrl_mem_partial_access.2880478987
Directory /workspace/36.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/36.sram_ctrl_mem_walk.2241751460
Short name T389
Test name
Test status
Simulation time 76435970402 ps
CPU time 164.78 seconds
Started Jan 14 02:29:13 PM PST 24
Finished Jan 14 02:31:59 PM PST 24
Peak memory 202488 kb
Host smart-530c6d8a-8f4f-40c8-83e7-d96c8e54c70b
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241751460 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctr
l_mem_walk.2241751460
Directory /workspace/36.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/36.sram_ctrl_multiple_keys.2100290236
Short name T531
Test name
Test status
Simulation time 69587074956 ps
CPU time 1011.6 seconds
Started Jan 14 02:29:03 PM PST 24
Finished Jan 14 02:45:55 PM PST 24
Peak memory 379048 kb
Host smart-6aa93e4c-21d0-4bf1-97a5-b7f9843d993a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100290236 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multi
ple_keys.2100290236
Directory /workspace/36.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/36.sram_ctrl_partial_access.240709447
Short name T589
Test name
Test status
Simulation time 2760267327 ps
CPU time 11.07 seconds
Started Jan 14 02:29:02 PM PST 24
Finished Jan 14 02:29:14 PM PST 24
Peak memory 202164 kb
Host smart-82d33181-f960-44b6-9374-eb962fd75c4c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240709447 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.s
ram_ctrl_partial_access.240709447
Directory /workspace/36.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.3182468455
Short name T864
Test name
Test status
Simulation time 262820560919 ps
CPU time 631.72 seconds
Started Jan 14 02:29:03 PM PST 24
Finished Jan 14 02:39:36 PM PST 24
Peak memory 210364 kb
Host smart-05f728ae-30ab-4736-af76-a0f80e24c04a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182468455 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 36.sram_ctrl_partial_access_b2b.3182468455
Directory /workspace/36.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/36.sram_ctrl_ram_cfg.2247813270
Short name T440
Test name
Test status
Simulation time 362840799 ps
CPU time 6.04 seconds
Started Jan 14 02:29:05 PM PST 24
Finished Jan 14 02:29:12 PM PST 24
Peak memory 202300 kb
Host smart-2801e79b-1332-482b-9d2a-3f0b598b7d3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247813270 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.2247813270
Directory /workspace/36.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/36.sram_ctrl_regwen.3860539339
Short name T778
Test name
Test status
Simulation time 46951752061 ps
CPU time 841.14 seconds
Started Jan 14 02:29:04 PM PST 24
Finished Jan 14 02:43:07 PM PST 24
Peak memory 374976 kb
Host smart-7c90f20a-c069-43d8-bb5f-7b069cadd7eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860539339 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.3860539339
Directory /workspace/36.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/36.sram_ctrl_smoke.241035427
Short name T318
Test name
Test status
Simulation time 3647092003 ps
CPU time 127.62 seconds
Started Jan 14 02:29:04 PM PST 24
Finished Jan 14 02:31:12 PM PST 24
Peak memory 361588 kb
Host smart-9415ee7f-0d7b-44c0-b68e-452d581464ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241035427 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.241035427
Directory /workspace/36.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.1286995517
Short name T470
Test name
Test status
Simulation time 412554194 ps
CPU time 2948.04 seconds
Started Jan 14 02:29:14 PM PST 24
Finished Jan 14 03:18:24 PM PST 24
Peak memory 645224 kb
Host smart-108c497f-c8fd-4295-8ec3-3538cc36c449
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1286995517 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all_with_rand_reset.1286995517
Directory /workspace/36.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.sram_ctrl_stress_pipeline.3315430480
Short name T562
Test name
Test status
Simulation time 8860599681 ps
CPU time 383.85 seconds
Started Jan 14 02:29:05 PM PST 24
Finished Jan 14 02:35:30 PM PST 24
Peak memory 202196 kb
Host smart-b6afd472-a01e-41f8-871f-a0f7a1b7919a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315430480 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.sram_ctrl_stress_pipeline.3315430480
Directory /workspace/36.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.1544240354
Short name T390
Test name
Test status
Simulation time 708851394 ps
CPU time 39.51 seconds
Started Jan 14 02:29:06 PM PST 24
Finished Jan 14 02:29:47 PM PST 24
Peak memory 253408 kb
Host smart-5b78e563-c096-4459-84f5-7285a46c4857
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544240354 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 36.sram_ctrl_throughput_w_partial_write.1544240354
Directory /workspace/36.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/37.sram_ctrl_access_during_key_req.3168409392
Short name T784
Test name
Test status
Simulation time 4003769767 ps
CPU time 130.6 seconds
Started Jan 14 02:29:38 PM PST 24
Finished Jan 14 02:31:52 PM PST 24
Peak memory 287316 kb
Host smart-5294002f-7e8a-4a94-96b8-1747c7f28d2f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168409392 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 37.sram_ctrl_access_during_key_req.3168409392
Directory /workspace/37.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/37.sram_ctrl_alert_test.964112330
Short name T577
Test name
Test status
Simulation time 38823498 ps
CPU time 0.63 seconds
Started Jan 14 02:29:51 PM PST 24
Finished Jan 14 02:29:54 PM PST 24
Peak memory 201892 kb
Host smart-f5b32e13-8139-4f2b-a83d-75177a6d51c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964112330 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.sram_ctrl_alert_test.964112330
Directory /workspace/37.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.sram_ctrl_bijection.2677046570
Short name T551
Test name
Test status
Simulation time 499420351741 ps
CPU time 1316.05 seconds
Started Jan 14 02:29:25 PM PST 24
Finished Jan 14 02:51:22 PM PST 24
Peak memory 202184 kb
Host smart-74d79309-c511-46c9-841c-eb8bd34663b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677046570 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection
.2677046570
Directory /workspace/37.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/37.sram_ctrl_lc_escalation.1472058959
Short name T834
Test name
Test status
Simulation time 5566180884 ps
CPU time 163.99 seconds
Started Jan 14 02:29:38 PM PST 24
Finished Jan 14 02:32:24 PM PST 24
Peak memory 210416 kb
Host smart-33d82295-15e2-48b7-962d-38edae953952
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472058959 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_lc_es
calation.1472058959
Directory /workspace/37.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/37.sram_ctrl_max_throughput.1571855869
Short name T869
Test name
Test status
Simulation time 1513422859 ps
CPU time 149.33 seconds
Started Jan 14 02:29:29 PM PST 24
Finished Jan 14 02:31:59 PM PST 24
Peak memory 353356 kb
Host smart-3ffac74c-36e2-4258-9f19-1d81c08ad310
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571855869 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 37.sram_ctrl_max_throughput.1571855869
Directory /workspace/37.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/37.sram_ctrl_mem_partial_access.406999823
Short name T934
Test name
Test status
Simulation time 4967659150 ps
CPU time 150.47 seconds
Started Jan 14 02:29:47 PM PST 24
Finished Jan 14 02:32:20 PM PST 24
Peak memory 211196 kb
Host smart-7b7a47af-a40c-4596-8b32-54e0c5505e38
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406999823 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.sram_ctrl_mem_partial_access.406999823
Directory /workspace/37.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/37.sram_ctrl_mem_walk.3259082650
Short name T743
Test name
Test status
Simulation time 17938763274 ps
CPU time 306.16 seconds
Started Jan 14 02:29:42 PM PST 24
Finished Jan 14 02:34:50 PM PST 24
Peak memory 202124 kb
Host smart-ff72a5e6-c7e7-4b1c-ac3d-f3eb675ca38b
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259082650 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctr
l_mem_walk.3259082650
Directory /workspace/37.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/37.sram_ctrl_multiple_keys.3680996022
Short name T540
Test name
Test status
Simulation time 8520379522 ps
CPU time 440.61 seconds
Started Jan 14 02:29:25 PM PST 24
Finished Jan 14 02:36:46 PM PST 24
Peak memory 375008 kb
Host smart-27e999bd-8948-4657-8df7-00c954ac84bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680996022 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multi
ple_keys.3680996022
Directory /workspace/37.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/37.sram_ctrl_partial_access.3361897191
Short name T932
Test name
Test status
Simulation time 434899131 ps
CPU time 19.08 seconds
Started Jan 14 02:29:27 PM PST 24
Finished Jan 14 02:29:47 PM PST 24
Peak memory 202100 kb
Host smart-a5da74df-b725-4a38-acdb-0f78b5137852
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361897191 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
sram_ctrl_partial_access.3361897191
Directory /workspace/37.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.611170404
Short name T557
Test name
Test status
Simulation time 73729027843 ps
CPU time 455.62 seconds
Started Jan 14 02:29:29 PM PST 24
Finished Jan 14 02:37:05 PM PST 24
Peak memory 202148 kb
Host smart-39be8f8d-77f8-4efd-82b9-d21e345fe5c6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611170404 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.sram_ctrl_partial_access_b2b.611170404
Directory /workspace/37.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/37.sram_ctrl_ram_cfg.2488841602
Short name T505
Test name
Test status
Simulation time 366859439 ps
CPU time 13.65 seconds
Started Jan 14 02:29:47 PM PST 24
Finished Jan 14 02:30:03 PM PST 24
Peak memory 202424 kb
Host smart-11477e82-60f2-42da-af49-c0a3b9189c79
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488841602 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.2488841602
Directory /workspace/37.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/37.sram_ctrl_regwen.994793462
Short name T818
Test name
Test status
Simulation time 10225174269 ps
CPU time 566.44 seconds
Started Jan 14 02:29:43 PM PST 24
Finished Jan 14 02:39:15 PM PST 24
Peak memory 376844 kb
Host smart-4083f82e-6f34-4c38-bd7b-9a8ea463cdf7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994793462 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.994793462
Directory /workspace/37.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/37.sram_ctrl_smoke.3892288039
Short name T563
Test name
Test status
Simulation time 558715778 ps
CPU time 30.47 seconds
Started Jan 14 02:29:24 PM PST 24
Finished Jan 14 02:29:55 PM PST 24
Peak memory 202008 kb
Host smart-9513d748-86e0-4891-8524-89bf11634afe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892288039 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.3892288039
Directory /workspace/37.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/37.sram_ctrl_stress_all.457801926
Short name T568
Test name
Test status
Simulation time 17047656363 ps
CPU time 2155.02 seconds
Started Jan 14 02:29:52 PM PST 24
Finished Jan 14 03:05:50 PM PST 24
Peak memory 378108 kb
Host smart-5a716e32-20fd-4eed-a92e-1ed7901c6758
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457801926 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 37.sram_ctrl_stress_all.457801926
Directory /workspace/37.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.1733369039
Short name T913
Test name
Test status
Simulation time 1065742865 ps
CPU time 3125.04 seconds
Started Jan 14 02:29:52 PM PST 24
Finished Jan 14 03:21:59 PM PST 24
Peak memory 430504 kb
Host smart-bf49bed8-8f56-4cfc-8ff0-dc9d977c29c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1733369039 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all_with_rand_reset.1733369039
Directory /workspace/37.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.sram_ctrl_stress_pipeline.1821693578
Short name T861
Test name
Test status
Simulation time 4586530499 ps
CPU time 336.62 seconds
Started Jan 14 02:29:20 PM PST 24
Finished Jan 14 02:34:57 PM PST 24
Peak memory 202164 kb
Host smart-6aa02091-db7f-4253-af67-90389e254fb7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821693578 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.sram_ctrl_stress_pipeline.1821693578
Directory /workspace/37.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.1522681556
Short name T810
Test name
Test status
Simulation time 741786743 ps
CPU time 65.67 seconds
Started Jan 14 02:29:28 PM PST 24
Finished Jan 14 02:30:35 PM PST 24
Peak memory 308476 kb
Host smart-3278de91-9787-4435-9333-1e5dd1e40850
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522681556 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 37.sram_ctrl_throughput_w_partial_write.1522681556
Directory /workspace/37.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/38.sram_ctrl_access_during_key_req.3855895471
Short name T290
Test name
Test status
Simulation time 12994785764 ps
CPU time 670.33 seconds
Started Jan 14 02:30:05 PM PST 24
Finished Jan 14 02:41:17 PM PST 24
Peak memory 353696 kb
Host smart-b5e22eeb-17f9-4d15-bfa8-965ebc62bee8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855895471 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.sram_ctrl_access_during_key_req.3855895471
Directory /workspace/38.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/38.sram_ctrl_alert_test.3082288968
Short name T267
Test name
Test status
Simulation time 13118722 ps
CPU time 0.66 seconds
Started Jan 14 02:30:22 PM PST 24
Finished Jan 14 02:30:24 PM PST 24
Peak memory 201436 kb
Host smart-a9598c8e-21b0-491e-ac57-fafbba771c03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082288968 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.sram_ctrl_alert_test.3082288968
Directory /workspace/38.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.sram_ctrl_bijection.275212018
Short name T656
Test name
Test status
Simulation time 121565080927 ps
CPU time 2069.64 seconds
Started Jan 14 02:29:51 PM PST 24
Finished Jan 14 03:04:23 PM PST 24
Peak memory 202148 kb
Host smart-ffb14e51-ab94-48b7-91b0-e969033f28e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275212018 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection.
275212018
Directory /workspace/38.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/38.sram_ctrl_executable.1682911927
Short name T366
Test name
Test status
Simulation time 24953821682 ps
CPU time 1510 seconds
Started Jan 14 02:30:08 PM PST 24
Finished Jan 14 02:55:19 PM PST 24
Peak memory 378088 kb
Host smart-461226c4-a24e-4de3-aebb-14ad39421d79
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682911927 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_executab
le.1682911927
Directory /workspace/38.sram_ctrl_executable/latest

Test location /workspace/coverage/default/38.sram_ctrl_lc_escalation.1942141734
Short name T943
Test name
Test status
Simulation time 30361629268 ps
CPU time 106.23 seconds
Started Jan 14 02:30:03 PM PST 24
Finished Jan 14 02:31:53 PM PST 24
Peak memory 210392 kb
Host smart-161e69a3-0b83-481c-9a4a-019b383c4ff4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942141734 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_es
calation.1942141734
Directory /workspace/38.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/38.sram_ctrl_max_throughput.3663802491
Short name T744
Test name
Test status
Simulation time 749122618 ps
CPU time 60.85 seconds
Started Jan 14 02:30:02 PM PST 24
Finished Jan 14 02:31:06 PM PST 24
Peak memory 283992 kb
Host smart-1bde3c21-8b97-447d-baaf-ae9f92deecdd
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663802491 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 38.sram_ctrl_max_throughput.3663802491
Directory /workspace/38.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/38.sram_ctrl_mem_partial_access.3926696996
Short name T817
Test name
Test status
Simulation time 3326501841 ps
CPU time 138.95 seconds
Started Jan 14 02:30:13 PM PST 24
Finished Jan 14 02:32:34 PM PST 24
Peak memory 211228 kb
Host smart-d34c91ce-35bc-40c9-a6ce-c37eabb08e73
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926696996 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.sram_ctrl_mem_partial_access.3926696996
Directory /workspace/38.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/38.sram_ctrl_mem_walk.1843216264
Short name T510
Test name
Test status
Simulation time 57330540133 ps
CPU time 286.62 seconds
Started Jan 14 02:30:08 PM PST 24
Finished Jan 14 02:34:56 PM PST 24
Peak memory 202336 kb
Host smart-f8f4696c-5a1b-436b-a5f6-6fbbef5f47ec
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843216264 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctr
l_mem_walk.1843216264
Directory /workspace/38.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/38.sram_ctrl_multiple_keys.482863195
Short name T524
Test name
Test status
Simulation time 76312057729 ps
CPU time 1678.74 seconds
Started Jan 14 02:29:50 PM PST 24
Finished Jan 14 02:57:51 PM PST 24
Peak memory 381196 kb
Host smart-10991557-4408-4a7d-bf6a-9fc2265c835d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482863195 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multip
le_keys.482863195
Directory /workspace/38.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/38.sram_ctrl_partial_access.3718506527
Short name T920
Test name
Test status
Simulation time 3287653983 ps
CPU time 35.62 seconds
Started Jan 14 02:30:03 PM PST 24
Finished Jan 14 02:30:42 PM PST 24
Peak memory 202172 kb
Host smart-3ee5df6b-73d2-4729-8f60-637eb15416cb
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718506527 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
sram_ctrl_partial_access.3718506527
Directory /workspace/38.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.983490367
Short name T346
Test name
Test status
Simulation time 7779195218 ps
CPU time 500.92 seconds
Started Jan 14 02:30:04 PM PST 24
Finished Jan 14 02:38:28 PM PST 24
Peak memory 202056 kb
Host smart-da416a49-b4a7-4383-aad6-15234c218a10
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983490367 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.sram_ctrl_partial_access_b2b.983490367
Directory /workspace/38.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/38.sram_ctrl_ram_cfg.1346252077
Short name T311
Test name
Test status
Simulation time 5619075375 ps
CPU time 14.46 seconds
Started Jan 14 02:30:09 PM PST 24
Finished Jan 14 02:30:26 PM PST 24
Peak memory 202476 kb
Host smart-10a4ce80-b259-49f6-8e94-6db636741211
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346252077 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.1346252077
Directory /workspace/38.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/38.sram_ctrl_regwen.3259203170
Short name T349
Test name
Test status
Simulation time 1953103483 ps
CPU time 53.52 seconds
Started Jan 14 02:30:09 PM PST 24
Finished Jan 14 02:31:05 PM PST 24
Peak memory 296552 kb
Host smart-359582aa-9541-4c7a-a6da-b06e641237a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259203170 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.3259203170
Directory /workspace/38.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/38.sram_ctrl_smoke.3706238842
Short name T244
Test name
Test status
Simulation time 672703657 ps
CPU time 117.59 seconds
Started Jan 14 02:29:51 PM PST 24
Finished Jan 14 02:31:51 PM PST 24
Peak memory 354540 kb
Host smart-ac9b006e-b204-4008-92e0-567bd925f4aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706238842 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.3706238842
Directory /workspace/38.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/38.sram_ctrl_stress_all.4261735114
Short name T17
Test name
Test status
Simulation time 222055034440 ps
CPU time 7162.05 seconds
Started Jan 14 02:30:18 PM PST 24
Finished Jan 14 04:29:43 PM PST 24
Peak memory 382264 kb
Host smart-c32cbc32-8104-4eac-a54e-976a5ca12e9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261735114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 38.sram_ctrl_stress_all.4261735114
Directory /workspace/38.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.3838260875
Short name T412
Test name
Test status
Simulation time 19015145727 ps
CPU time 1436.03 seconds
Started Jan 14 02:30:18 PM PST 24
Finished Jan 14 02:54:16 PM PST 24
Peak memory 446928 kb
Host smart-48c03c40-ad1f-4b6f-a3f9-44a251c39ad1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3838260875 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all_with_rand_reset.3838260875
Directory /workspace/38.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.sram_ctrl_stress_pipeline.3618968988
Short name T103
Test name
Test status
Simulation time 6679319401 ps
CPU time 312.05 seconds
Started Jan 14 02:30:04 PM PST 24
Finished Jan 14 02:35:19 PM PST 24
Peak memory 202096 kb
Host smart-a25e7292-0fb7-4412-960d-9e2d83e71255
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618968988 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.sram_ctrl_stress_pipeline.3618968988
Directory /workspace/38.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.921058564
Short name T382
Test name
Test status
Simulation time 3085767830 ps
CPU time 87.79 seconds
Started Jan 14 02:30:05 PM PST 24
Finished Jan 14 02:31:35 PM PST 24
Peak memory 310820 kb
Host smart-0d5d1508-1a7a-464c-8caa-a02fedf0a197
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921058564 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 38.sram_ctrl_throughput_w_partial_write.921058564
Directory /workspace/38.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/39.sram_ctrl_access_during_key_req.1213526901
Short name T637
Test name
Test status
Simulation time 25001544488 ps
CPU time 764.18 seconds
Started Jan 14 02:30:29 PM PST 24
Finished Jan 14 02:43:14 PM PST 24
Peak memory 375864 kb
Host smart-6333acad-4899-4b8d-8f16-7b5a1619b00c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213526901 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.sram_ctrl_access_during_key_req.1213526901
Directory /workspace/39.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/39.sram_ctrl_alert_test.1685177118
Short name T277
Test name
Test status
Simulation time 45339538 ps
CPU time 0.66 seconds
Started Jan 14 02:30:37 PM PST 24
Finished Jan 14 02:30:38 PM PST 24
Peak memory 201864 kb
Host smart-a2cb72ed-77fd-482a-934c-84ce8b248968
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685177118 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.sram_ctrl_alert_test.1685177118
Directory /workspace/39.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.sram_ctrl_bijection.3059744540
Short name T368
Test name
Test status
Simulation time 109090927729 ps
CPU time 2131.55 seconds
Started Jan 14 02:30:23 PM PST 24
Finished Jan 14 03:05:56 PM PST 24
Peak memory 202172 kb
Host smart-2e75e66f-ca87-407e-8f4d-3b1a35cea0c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059744540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection
.3059744540
Directory /workspace/39.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/39.sram_ctrl_lc_escalation.3353489282
Short name T923
Test name
Test status
Simulation time 37557352819 ps
CPU time 105.65 seconds
Started Jan 14 02:30:29 PM PST 24
Finished Jan 14 02:32:16 PM PST 24
Peak memory 210360 kb
Host smart-be4a8a0a-33c6-46a6-8b66-1881c167c3fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353489282 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_es
calation.3353489282
Directory /workspace/39.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/39.sram_ctrl_max_throughput.4293129381
Short name T593
Test name
Test status
Simulation time 802839289 ps
CPU time 148.61 seconds
Started Jan 14 02:30:23 PM PST 24
Finished Jan 14 02:32:53 PM PST 24
Peak memory 360124 kb
Host smart-f7ca666f-b568-4e35-ac62-a850e300bca0
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293129381 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 39.sram_ctrl_max_throughput.4293129381
Directory /workspace/39.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/39.sram_ctrl_mem_partial_access.473080838
Short name T132
Test name
Test status
Simulation time 19578002879 ps
CPU time 151.11 seconds
Started Jan 14 02:30:30 PM PST 24
Finished Jan 14 02:33:02 PM PST 24
Peak memory 211164 kb
Host smart-66b35665-3612-4e94-8fa5-61ca413b8221
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473080838 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.sram_ctrl_mem_partial_access.473080838
Directory /workspace/39.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/39.sram_ctrl_mem_walk.4101183786
Short name T526
Test name
Test status
Simulation time 7173245467 ps
CPU time 138.44 seconds
Started Jan 14 02:30:29 PM PST 24
Finished Jan 14 02:32:48 PM PST 24
Peak memory 202216 kb
Host smart-5040993a-3f62-4fdd-ad51-5276b2910b3d
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101183786 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctr
l_mem_walk.4101183786
Directory /workspace/39.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/39.sram_ctrl_multiple_keys.2834813262
Short name T337
Test name
Test status
Simulation time 13693115330 ps
CPU time 816.14 seconds
Started Jan 14 02:30:23 PM PST 24
Finished Jan 14 02:44:01 PM PST 24
Peak memory 366864 kb
Host smart-2104ce40-b17c-47e1-a97d-a3d3a11a169c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834813262 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multi
ple_keys.2834813262
Directory /workspace/39.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/39.sram_ctrl_partial_access.3815465991
Short name T435
Test name
Test status
Simulation time 8018664257 ps
CPU time 115.52 seconds
Started Jan 14 02:30:19 PM PST 24
Finished Jan 14 02:32:16 PM PST 24
Peak memory 346288 kb
Host smart-7144b5d8-cc25-4ff7-9f3b-53969c0bec74
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815465991 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
sram_ctrl_partial_access.3815465991
Directory /workspace/39.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.1682757158
Short name T952
Test name
Test status
Simulation time 14709516495 ps
CPU time 383.84 seconds
Started Jan 14 02:30:21 PM PST 24
Finished Jan 14 02:36:46 PM PST 24
Peak memory 210340 kb
Host smart-a348be5d-580d-458b-8dd0-85f84d904301
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682757158 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 39.sram_ctrl_partial_access_b2b.1682757158
Directory /workspace/39.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/39.sram_ctrl_ram_cfg.1856109131
Short name T721
Test name
Test status
Simulation time 347642826 ps
CPU time 5.58 seconds
Started Jan 14 02:30:30 PM PST 24
Finished Jan 14 02:30:36 PM PST 24
Peak memory 202316 kb
Host smart-24334a7e-8533-43ef-bf23-f69835c2557d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856109131 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.1856109131
Directory /workspace/39.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/39.sram_ctrl_regwen.3562589327
Short name T420
Test name
Test status
Simulation time 3032604090 ps
CPU time 383.7 seconds
Started Jan 14 02:30:31 PM PST 24
Finished Jan 14 02:36:55 PM PST 24
Peak memory 371932 kb
Host smart-306bc3d6-5f41-4142-a251-a33c53c08136
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562589327 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.3562589327
Directory /workspace/39.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/39.sram_ctrl_smoke.667714018
Short name T936
Test name
Test status
Simulation time 1312414868 ps
CPU time 41.66 seconds
Started Jan 14 02:30:18 PM PST 24
Finished Jan 14 02:31:02 PM PST 24
Peak memory 285124 kb
Host smart-6e329a96-c4d9-4f41-a680-c7ae84dc54e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667714018 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.667714018
Directory /workspace/39.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.3002535808
Short name T871
Test name
Test status
Simulation time 6551079415 ps
CPU time 7687.14 seconds
Started Jan 14 02:30:31 PM PST 24
Finished Jan 14 04:38:40 PM PST 24
Peak memory 707280 kb
Host smart-de6d4913-ea8a-43bc-bd01-9df8ccfd4f9f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3002535808 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all_with_rand_reset.3002535808
Directory /workspace/39.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.sram_ctrl_stress_pipeline.180029004
Short name T396
Test name
Test status
Simulation time 36194590102 ps
CPU time 436.15 seconds
Started Jan 14 02:30:18 PM PST 24
Finished Jan 14 02:37:36 PM PST 24
Peak memory 202148 kb
Host smart-d0bbbeba-0a43-4686-8792-d31d77943d48
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180029004 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.sram_ctrl_stress_pipeline.180029004
Directory /workspace/39.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.3513503562
Short name T372
Test name
Test status
Simulation time 6674704803 ps
CPU time 64.75 seconds
Started Jan 14 02:30:28 PM PST 24
Finished Jan 14 02:31:34 PM PST 24
Peak memory 302332 kb
Host smart-08ea96c2-bc6c-433f-ba0f-bb1ddc055716
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513503562 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 39.sram_ctrl_throughput_w_partial_write.3513503562
Directory /workspace/39.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/4.sram_ctrl_access_during_key_req.3900646685
Short name T752
Test name
Test status
Simulation time 5581701251 ps
CPU time 1309.23 seconds
Started Jan 14 02:14:05 PM PST 24
Finished Jan 14 02:35:56 PM PST 24
Peak memory 380140 kb
Host smart-c3c1cc33-3c75-417b-884f-915c1ee787e3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900646685 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.sram_ctrl_access_during_key_req.3900646685
Directory /workspace/4.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/4.sram_ctrl_alert_test.3863810214
Short name T550
Test name
Test status
Simulation time 40027247 ps
CPU time 0.63 seconds
Started Jan 14 02:14:34 PM PST 24
Finished Jan 14 02:14:40 PM PST 24
Peak memory 201464 kb
Host smart-6ff777c6-f408-43c9-a154-1425708cbf1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863810214 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.sram_ctrl_alert_test.3863810214
Directory /workspace/4.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.sram_ctrl_bijection.2149077957
Short name T569
Test name
Test status
Simulation time 523250211273 ps
CPU time 2665.81 seconds
Started Jan 14 02:13:54 PM PST 24
Finished Jan 14 02:58:20 PM PST 24
Peak memory 202172 kb
Host smart-bd88ed47-3232-4ea6-889b-725d4e3c6427
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149077957 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection.
2149077957
Directory /workspace/4.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/4.sram_ctrl_lc_escalation.2170866501
Short name T26
Test name
Test status
Simulation time 22385755594 ps
CPU time 211.62 seconds
Started Jan 14 02:14:02 PM PST 24
Finished Jan 14 02:17:35 PM PST 24
Peak memory 202260 kb
Host smart-c908bc60-ca61-4988-a033-9f55ecd33271
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170866501 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_esc
alation.2170866501
Directory /workspace/4.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/4.sram_ctrl_max_throughput.1831582549
Short name T41
Test name
Test status
Simulation time 3039298942 ps
CPU time 157.01 seconds
Started Jan 14 02:14:02 PM PST 24
Finished Jan 14 02:16:40 PM PST 24
Peak memory 361380 kb
Host smart-36b80d4e-0b06-4f6a-9fb5-99fad99492b8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831582549 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 4.sram_ctrl_max_throughput.1831582549
Directory /workspace/4.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/4.sram_ctrl_mem_partial_access.2120893363
Short name T626
Test name
Test status
Simulation time 20410797509 ps
CPU time 162.81 seconds
Started Jan 14 02:14:20 PM PST 24
Finished Jan 14 02:17:08 PM PST 24
Peak memory 218460 kb
Host smart-10e09ae8-f71d-4a21-a9a5-7ec967112a8c
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120893363 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.sram_ctrl_mem_partial_access.2120893363
Directory /workspace/4.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/4.sram_ctrl_mem_walk.1701803414
Short name T732
Test name
Test status
Simulation time 8506294110 ps
CPU time 147.58 seconds
Started Jan 14 02:14:15 PM PST 24
Finished Jan 14 02:16:43 PM PST 24
Peak memory 202324 kb
Host smart-8ebdd95b-22a6-48e9-a569-54eb4ed6aecd
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701803414 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl
_mem_walk.1701803414
Directory /workspace/4.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/4.sram_ctrl_multiple_keys.206934336
Short name T239
Test name
Test status
Simulation time 77250527369 ps
CPU time 785.17 seconds
Started Jan 14 02:13:52 PM PST 24
Finished Jan 14 02:26:58 PM PST 24
Peak memory 380168 kb
Host smart-5e2a3fbe-e8bd-4e2a-83bf-e0dd03159e11
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206934336 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multipl
e_keys.206934336
Directory /workspace/4.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/4.sram_ctrl_partial_access.2840418654
Short name T414
Test name
Test status
Simulation time 11122725367 ps
CPU time 41.62 seconds
Started Jan 14 02:13:53 PM PST 24
Finished Jan 14 02:14:35 PM PST 24
Peak memory 210316 kb
Host smart-7f39552f-84af-4355-a497-41f83d10168f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840418654 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.s
ram_ctrl_partial_access.2840418654
Directory /workspace/4.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.465055104
Short name T220
Test name
Test status
Simulation time 16151336622 ps
CPU time 254.12 seconds
Started Jan 14 02:13:59 PM PST 24
Finished Jan 14 02:18:17 PM PST 24
Peak memory 202160 kb
Host smart-8b581d58-a32e-4df8-9143-3c6e71888e9c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465055104 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.sram_ctrl_partial_access_b2b.465055104
Directory /workspace/4.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/4.sram_ctrl_ram_cfg.3106037236
Short name T750
Test name
Test status
Simulation time 404022027 ps
CPU time 13.48 seconds
Started Jan 14 02:14:20 PM PST 24
Finished Jan 14 02:14:39 PM PST 24
Peak memory 202444 kb
Host smart-0e0efa24-7ce0-4b3b-983e-42bfdf2dafb8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106037236 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.3106037236
Directory /workspace/4.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/4.sram_ctrl_regwen.438158277
Short name T883
Test name
Test status
Simulation time 8709423798 ps
CPU time 1591.86 seconds
Started Jan 14 02:14:13 PM PST 24
Finished Jan 14 02:40:46 PM PST 24
Peak memory 378096 kb
Host smart-e40e2f1c-290c-46a7-9c5e-31621ae2a07e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438158277 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.438158277
Directory /workspace/4.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/4.sram_ctrl_sec_cm.503165873
Short name T39
Test name
Test status
Simulation time 278332750 ps
CPU time 2.03 seconds
Started Jan 14 02:14:24 PM PST 24
Finished Jan 14 02:14:29 PM PST 24
Peak memory 220932 kb
Host smart-f78eb31b-296d-4a98-bdcf-2a8eb4a49542
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503165873 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.sram_ctrl_sec_cm.503165873
Directory /workspace/4.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.sram_ctrl_smoke.3512340712
Short name T538
Test name
Test status
Simulation time 1277611680 ps
CPU time 109.01 seconds
Started Jan 14 02:13:48 PM PST 24
Finished Jan 14 02:15:38 PM PST 24
Peak memory 340100 kb
Host smart-06198e1a-95e1-46db-9a00-55367468e69f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512340712 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.3512340712
Directory /workspace/4.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.1900518298
Short name T837
Test name
Test status
Simulation time 964916789 ps
CPU time 3955.97 seconds
Started Jan 14 02:14:21 PM PST 24
Finished Jan 14 03:20:23 PM PST 24
Peak memory 584228 kb
Host smart-c7931283-dab3-49a0-aa8d-4986eab54f6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1900518298 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all_with_rand_reset.1900518298
Directory /workspace/4.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.sram_ctrl_stress_pipeline.2606073661
Short name T640
Test name
Test status
Simulation time 3341727796 ps
CPU time 261.65 seconds
Started Jan 14 02:13:55 PM PST 24
Finished Jan 14 02:18:17 PM PST 24
Peak memory 202068 kb
Host smart-316d2bb2-da27-40c8-8b1c-a25f9938c4cf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606073661 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.sram_ctrl_stress_pipeline.2606073661
Directory /workspace/4.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.2168346611
Short name T278
Test name
Test status
Simulation time 820465292 ps
CPU time 173.39 seconds
Started Jan 14 02:14:00 PM PST 24
Finished Jan 14 02:16:56 PM PST 24
Peak memory 364728 kb
Host smart-3f402117-8490-47e7-87e2-4a3af368e4a2
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168346611 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.sram_ctrl_throughput_w_partial_write.2168346611
Directory /workspace/4.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/40.sram_ctrl_alert_test.1603253224
Short name T324
Test name
Test status
Simulation time 12717016 ps
CPU time 0.66 seconds
Started Jan 14 02:31:05 PM PST 24
Finished Jan 14 02:31:07 PM PST 24
Peak memory 201856 kb
Host smart-1bb56e1e-c970-456d-a077-a125eee7e84a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603253224 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.sram_ctrl_alert_test.1603253224
Directory /workspace/40.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.sram_ctrl_bijection.3401884626
Short name T859
Test name
Test status
Simulation time 395495394644 ps
CPU time 1272.51 seconds
Started Jan 14 02:30:37 PM PST 24
Finished Jan 14 02:51:50 PM PST 24
Peak memory 202172 kb
Host smart-1b11924d-b8e5-408a-b857-d19c20f33f4c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401884626 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection
.3401884626
Directory /workspace/40.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/40.sram_ctrl_lc_escalation.3632939949
Short name T482
Test name
Test status
Simulation time 12632862524 ps
CPU time 128.63 seconds
Started Jan 14 02:30:46 PM PST 24
Finished Jan 14 02:32:55 PM PST 24
Peak memory 210416 kb
Host smart-26aece45-790d-469e-bdad-869ba6d131a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632939949 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_es
calation.3632939949
Directory /workspace/40.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/40.sram_ctrl_max_throughput.124278281
Short name T933
Test name
Test status
Simulation time 2927815509 ps
CPU time 45.36 seconds
Started Jan 14 02:30:45 PM PST 24
Finished Jan 14 02:31:31 PM PST 24
Peak memory 267688 kb
Host smart-be3fdbc6-aab3-48c0-b29e-f83d93c2762f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124278281 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.sram_ctrl_max_throughput.124278281
Directory /workspace/40.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/40.sram_ctrl_mem_partial_access.977221495
Short name T221
Test name
Test status
Simulation time 4472715905 ps
CPU time 147.26 seconds
Started Jan 14 02:31:06 PM PST 24
Finished Jan 14 02:33:35 PM PST 24
Peak memory 214672 kb
Host smart-8d33677f-718a-447e-b9ad-7927e6511e11
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977221495 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.sram_ctrl_mem_partial_access.977221495
Directory /workspace/40.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/40.sram_ctrl_mem_walk.2211328058
Short name T674
Test name
Test status
Simulation time 1998281873 ps
CPU time 124.75 seconds
Started Jan 14 02:31:05 PM PST 24
Finished Jan 14 02:33:11 PM PST 24
Peak memory 202152 kb
Host smart-e1830688-545f-4713-9c08-ebabe4bd1125
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211328058 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctr
l_mem_walk.2211328058
Directory /workspace/40.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/40.sram_ctrl_multiple_keys.1351625674
Short name T853
Test name
Test status
Simulation time 82441909493 ps
CPU time 1202.6 seconds
Started Jan 14 02:30:38 PM PST 24
Finished Jan 14 02:50:41 PM PST 24
Peak memory 381172 kb
Host smart-54302018-013d-4862-b774-0f743f7fee41
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351625674 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multi
ple_keys.1351625674
Directory /workspace/40.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/40.sram_ctrl_partial_access.1462826980
Short name T764
Test name
Test status
Simulation time 968495750 ps
CPU time 42.44 seconds
Started Jan 14 02:30:47 PM PST 24
Finished Jan 14 02:31:30 PM PST 24
Peak memory 202148 kb
Host smart-97a190ad-3a0f-4a7e-9dc3-77fc0dc96b3f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462826980 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
sram_ctrl_partial_access.1462826980
Directory /workspace/40.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.333996389
Short name T422
Test name
Test status
Simulation time 29464868736 ps
CPU time 191.97 seconds
Started Jan 14 02:30:46 PM PST 24
Finished Jan 14 02:33:59 PM PST 24
Peak memory 202160 kb
Host smart-48b3771f-12da-45dd-bbc5-b768806a9ab4
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333996389 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.sram_ctrl_partial_access_b2b.333996389
Directory /workspace/40.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/40.sram_ctrl_ram_cfg.1013049416
Short name T38
Test name
Test status
Simulation time 373285634 ps
CPU time 13.54 seconds
Started Jan 14 02:31:06 PM PST 24
Finished Jan 14 02:31:21 PM PST 24
Peak memory 202444 kb
Host smart-4ff87d33-3b03-4bbc-9818-1e533e002db6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013049416 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.1013049416
Directory /workspace/40.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/40.sram_ctrl_regwen.1360299900
Short name T658
Test name
Test status
Simulation time 148775074249 ps
CPU time 870.95 seconds
Started Jan 14 02:30:45 PM PST 24
Finished Jan 14 02:45:17 PM PST 24
Peak memory 370908 kb
Host smart-a5af1588-bc6d-4a2c-b375-594190942b49
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360299900 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.1360299900
Directory /workspace/40.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/40.sram_ctrl_smoke.3165973487
Short name T798
Test name
Test status
Simulation time 7933263575 ps
CPU time 16.98 seconds
Started Jan 14 02:30:37 PM PST 24
Finished Jan 14 02:30:55 PM PST 24
Peak memory 202148 kb
Host smart-1ab67603-aba4-4197-98f4-43c460e9347b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165973487 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.3165973487
Directory /workspace/40.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/40.sram_ctrl_stress_all.2674071741
Short name T980
Test name
Test status
Simulation time 627678749151 ps
CPU time 3902.49 seconds
Started Jan 14 02:31:05 PM PST 24
Finished Jan 14 03:36:09 PM PST 24
Peak memory 374976 kb
Host smart-9a1dfd7e-fc4d-45a7-bcb7-72e569f9284c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674071741 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 40.sram_ctrl_stress_all.2674071741
Directory /workspace/40.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.3127244427
Short name T608
Test name
Test status
Simulation time 4077452938 ps
CPU time 4461.64 seconds
Started Jan 14 02:31:04 PM PST 24
Finished Jan 14 03:45:28 PM PST 24
Peak memory 555820 kb
Host smart-e76e69a8-9948-4022-8754-2db324a0a62b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3127244427 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all_with_rand_reset.3127244427
Directory /workspace/40.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.sram_ctrl_stress_pipeline.2247188924
Short name T977
Test name
Test status
Simulation time 15722585930 ps
CPU time 321.48 seconds
Started Jan 14 02:30:45 PM PST 24
Finished Jan 14 02:36:08 PM PST 24
Peak memory 202164 kb
Host smart-35761f7f-d023-4baf-a7b3-8eac20afc03e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247188924 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.sram_ctrl_stress_pipeline.2247188924
Directory /workspace/40.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.820647151
Short name T222
Test name
Test status
Simulation time 811596531 ps
CPU time 143.83 seconds
Started Jan 14 02:30:46 PM PST 24
Finished Jan 14 02:33:10 PM PST 24
Peak memory 352528 kb
Host smart-0fdbe1b4-54be-478a-99e9-325bf2657c3c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820647151 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 40.sram_ctrl_throughput_w_partial_write.820647151
Directory /workspace/40.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/41.sram_ctrl_access_during_key_req.963053031
Short name T657
Test name
Test status
Simulation time 31874972037 ps
CPU time 1134.18 seconds
Started Jan 14 02:31:19 PM PST 24
Finished Jan 14 02:50:14 PM PST 24
Peak memory 378276 kb
Host smart-86a5605f-6d8c-4e47-a353-88f530324240
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963053031 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 41.sram_ctrl_access_during_key_req.963053031
Directory /workspace/41.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/41.sram_ctrl_alert_test.427920649
Short name T351
Test name
Test status
Simulation time 13518989 ps
CPU time 0.68 seconds
Started Jan 14 02:31:24 PM PST 24
Finished Jan 14 02:31:25 PM PST 24
Peak memory 201908 kb
Host smart-43bc4a51-7d39-41c7-9c8a-317c0355abbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427920649 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.sram_ctrl_alert_test.427920649
Directory /workspace/41.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.sram_ctrl_bijection.1767095719
Short name T481
Test name
Test status
Simulation time 28436078386 ps
CPU time 634.93 seconds
Started Jan 14 02:31:04 PM PST 24
Finished Jan 14 02:41:41 PM PST 24
Peak memory 202132 kb
Host smart-6daaab35-2c85-495d-9bbc-225badfe42aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767095719 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection
.1767095719
Directory /workspace/41.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/41.sram_ctrl_executable.2231641156
Short name T718
Test name
Test status
Simulation time 19145646956 ps
CPU time 96.54 seconds
Started Jan 14 02:31:17 PM PST 24
Finished Jan 14 02:32:55 PM PST 24
Peak memory 252916 kb
Host smart-6790fc4c-3a3f-40ed-a1cb-e7fd3fbd09db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231641156 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_executab
le.2231641156
Directory /workspace/41.sram_ctrl_executable/latest

Test location /workspace/coverage/default/41.sram_ctrl_lc_escalation.2554435503
Short name T458
Test name
Test status
Simulation time 157173908877 ps
CPU time 143.24 seconds
Started Jan 14 02:31:09 PM PST 24
Finished Jan 14 02:33:33 PM PST 24
Peak memory 210596 kb
Host smart-5a15a5a4-407c-4743-ab71-ec51d4081a87
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554435503 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_es
calation.2554435503
Directory /workspace/41.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/41.sram_ctrl_max_throughput.2445758295
Short name T379
Test name
Test status
Simulation time 800035983 ps
CPU time 126.65 seconds
Started Jan 14 02:31:16 PM PST 24
Finished Jan 14 02:33:23 PM PST 24
Peak memory 353484 kb
Host smart-b867a9f0-2e24-479e-82a8-c0216b4f491d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445758295 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 41.sram_ctrl_max_throughput.2445758295
Directory /workspace/41.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/41.sram_ctrl_mem_partial_access.1131397518
Short name T456
Test name
Test status
Simulation time 20714175576 ps
CPU time 157.6 seconds
Started Jan 14 02:31:17 PM PST 24
Finished Jan 14 02:33:55 PM PST 24
Peak memory 211168 kb
Host smart-83093260-c5c0-4760-b7ee-e1a5550ecca5
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131397518 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.sram_ctrl_mem_partial_access.1131397518
Directory /workspace/41.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/41.sram_ctrl_mem_walk.4144654894
Short name T289
Test name
Test status
Simulation time 17176497489 ps
CPU time 144.03 seconds
Started Jan 14 02:31:17 PM PST 24
Finished Jan 14 02:33:42 PM PST 24
Peak memory 202452 kb
Host smart-2b6d782d-5495-4a62-8257-7f9201788904
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144654894 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctr
l_mem_walk.4144654894
Directory /workspace/41.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/41.sram_ctrl_multiple_keys.367016410
Short name T395
Test name
Test status
Simulation time 28597052627 ps
CPU time 1036.56 seconds
Started Jan 14 02:31:11 PM PST 24
Finished Jan 14 02:48:28 PM PST 24
Peak memory 379628 kb
Host smart-f535431f-d300-4a0f-a5b3-3d535b2dc307
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367016410 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multip
le_keys.367016410
Directory /workspace/41.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/41.sram_ctrl_partial_access.542967556
Short name T444
Test name
Test status
Simulation time 1077030922 ps
CPU time 52.42 seconds
Started Jan 14 02:31:17 PM PST 24
Finished Jan 14 02:32:10 PM PST 24
Peak memory 300328 kb
Host smart-a16ee1bd-e310-46ff-9d92-b1cefbb4dcd5
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542967556 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.s
ram_ctrl_partial_access.542967556
Directory /workspace/41.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.2881881976
Short name T400
Test name
Test status
Simulation time 9244962915 ps
CPU time 166.2 seconds
Started Jan 14 02:31:11 PM PST 24
Finished Jan 14 02:33:58 PM PST 24
Peak memory 202120 kb
Host smart-7f6937d6-3c0b-4944-a1b4-4e750f734172
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881881976 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 41.sram_ctrl_partial_access_b2b.2881881976
Directory /workspace/41.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/41.sram_ctrl_ram_cfg.341276297
Short name T37
Test name
Test status
Simulation time 343687255 ps
CPU time 13.42 seconds
Started Jan 14 02:31:16 PM PST 24
Finished Jan 14 02:31:30 PM PST 24
Peak memory 202416 kb
Host smart-2c6a7cef-8f4e-4549-a1f3-067c5f11f97f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341276297 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.341276297
Directory /workspace/41.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/41.sram_ctrl_regwen.1589500417
Short name T554
Test name
Test status
Simulation time 9455665174 ps
CPU time 433.75 seconds
Started Jan 14 02:31:14 PM PST 24
Finished Jan 14 02:38:29 PM PST 24
Peak memory 368808 kb
Host smart-946673f5-6859-44e9-b4ab-f5e750b91e9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589500417 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.1589500417
Directory /workspace/41.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/41.sram_ctrl_smoke.1952405577
Short name T305
Test name
Test status
Simulation time 401093977 ps
CPU time 15.72 seconds
Started Jan 14 02:31:05 PM PST 24
Finished Jan 14 02:31:22 PM PST 24
Peak memory 202092 kb
Host smart-b5520b40-c94d-4aaa-96e2-3351475b1bd8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952405577 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.1952405577
Directory /workspace/41.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/41.sram_ctrl_stress_all.2740249739
Short name T939
Test name
Test status
Simulation time 51282901687 ps
CPU time 830.69 seconds
Started Jan 14 02:31:24 PM PST 24
Finished Jan 14 02:45:16 PM PST 24
Peak memory 371328 kb
Host smart-9b5c3993-ab92-4989-915f-c91995481579
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740249739 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 41.sram_ctrl_stress_all.2740249739
Directory /workspace/41.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.2130402420
Short name T824
Test name
Test status
Simulation time 270607490 ps
CPU time 3805.64 seconds
Started Jan 14 02:31:25 PM PST 24
Finished Jan 14 03:34:51 PM PST 24
Peak memory 554336 kb
Host smart-4effb12a-84e7-4213-8b93-237c0e4a496b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2130402420 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all_with_rand_reset.2130402420
Directory /workspace/41.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.sram_ctrl_stress_pipeline.3209740413
Short name T978
Test name
Test status
Simulation time 20754593562 ps
CPU time 345.62 seconds
Started Jan 14 02:31:06 PM PST 24
Finished Jan 14 02:36:53 PM PST 24
Peak memory 202164 kb
Host smart-ae8027f3-99cd-4f49-9a9c-a1402a2ad17f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209740413 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.sram_ctrl_stress_pipeline.3209740413
Directory /workspace/41.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.918959458
Short name T899
Test name
Test status
Simulation time 4605346318 ps
CPU time 163.22 seconds
Started Jan 14 02:31:15 PM PST 24
Finished Jan 14 02:33:59 PM PST 24
Peak memory 366728 kb
Host smart-624fa675-2c9a-48aa-9198-1e57829bdb87
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918959458 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 41.sram_ctrl_throughput_w_partial_write.918959458
Directory /workspace/41.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/42.sram_ctrl_access_during_key_req.1133086586
Short name T632
Test name
Test status
Simulation time 49491743156 ps
CPU time 1779.27 seconds
Started Jan 14 02:31:34 PM PST 24
Finished Jan 14 03:01:14 PM PST 24
Peak memory 379104 kb
Host smart-64bac755-f970-4cfe-a9b4-c378dcdc4988
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133086586 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.sram_ctrl_access_during_key_req.1133086586
Directory /workspace/42.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/42.sram_ctrl_alert_test.3850795021
Short name T812
Test name
Test status
Simulation time 17243658 ps
CPU time 0.64 seconds
Started Jan 14 02:31:50 PM PST 24
Finished Jan 14 02:31:51 PM PST 24
Peak memory 201888 kb
Host smart-9b4d1c18-f13d-4f14-a19c-2028700b95ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850795021 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.sram_ctrl_alert_test.3850795021
Directory /workspace/42.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.sram_ctrl_bijection.2860864931
Short name T944
Test name
Test status
Simulation time 251713216615 ps
CPU time 1328.75 seconds
Started Jan 14 02:31:25 PM PST 24
Finished Jan 14 02:53:35 PM PST 24
Peak memory 202200 kb
Host smart-c2a73482-e4c7-4045-bc9a-8f1f11ddfa77
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860864931 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection
.2860864931
Directory /workspace/42.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/42.sram_ctrl_lc_escalation.4257461343
Short name T806
Test name
Test status
Simulation time 19926521336 ps
CPU time 60.45 seconds
Started Jan 14 02:31:39 PM PST 24
Finished Jan 14 02:32:40 PM PST 24
Peak memory 210460 kb
Host smart-ed5c9d91-cb76-4069-9aa5-b7375ae53232
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257461343 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_es
calation.4257461343
Directory /workspace/42.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/42.sram_ctrl_max_throughput.851940320
Short name T472
Test name
Test status
Simulation time 1364203720 ps
CPU time 31.17 seconds
Started Jan 14 02:31:33 PM PST 24
Finished Jan 14 02:32:05 PM PST 24
Peak memory 226836 kb
Host smart-3ad2c128-48b4-412c-9d8a-be22c27fef64
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851940320 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.sram_ctrl_max_throughput.851940320
Directory /workspace/42.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/42.sram_ctrl_mem_partial_access.2534877317
Short name T347
Test name
Test status
Simulation time 8676307531 ps
CPU time 153.03 seconds
Started Jan 14 02:31:42 PM PST 24
Finished Jan 14 02:34:15 PM PST 24
Peak memory 211248 kb
Host smart-cb7c2e37-1429-43ed-baea-6404ca415096
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534877317 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.sram_ctrl_mem_partial_access.2534877317
Directory /workspace/42.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/42.sram_ctrl_mem_walk.3951677512
Short name T224
Test name
Test status
Simulation time 3945880450 ps
CPU time 253.57 seconds
Started Jan 14 02:31:42 PM PST 24
Finished Jan 14 02:35:56 PM PST 24
Peak memory 202152 kb
Host smart-48dc7d76-20fc-4972-8ae2-a8db4d030483
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951677512 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctr
l_mem_walk.3951677512
Directory /workspace/42.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/42.sram_ctrl_multiple_keys.1784747987
Short name T285
Test name
Test status
Simulation time 118200914986 ps
CPU time 1357.08 seconds
Started Jan 14 02:31:23 PM PST 24
Finished Jan 14 02:54:01 PM PST 24
Peak memory 378844 kb
Host smart-8a167b96-1ab2-49a9-a17e-a0a840b36763
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784747987 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multi
ple_keys.1784747987
Directory /workspace/42.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/42.sram_ctrl_partial_access.644133126
Short name T957
Test name
Test status
Simulation time 3716815831 ps
CPU time 110.84 seconds
Started Jan 14 02:31:34 PM PST 24
Finished Jan 14 02:33:25 PM PST 24
Peak memory 338144 kb
Host smart-c5f7e962-eec1-4d92-a553-3b30519e1257
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644133126 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.s
ram_ctrl_partial_access.644133126
Directory /workspace/42.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.280637215
Short name T130
Test name
Test status
Simulation time 65446327374 ps
CPU time 364.34 seconds
Started Jan 14 02:31:34 PM PST 24
Finished Jan 14 02:37:39 PM PST 24
Peak memory 202160 kb
Host smart-aa3499b3-e3cb-423c-8473-0577ffdbb13c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280637215 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.sram_ctrl_partial_access_b2b.280637215
Directory /workspace/42.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/42.sram_ctrl_ram_cfg.442374752
Short name T970
Test name
Test status
Simulation time 368304899 ps
CPU time 12.69 seconds
Started Jan 14 02:31:40 PM PST 24
Finished Jan 14 02:31:53 PM PST 24
Peak memory 202416 kb
Host smart-5074e36e-1a29-43c5-ad57-a63edbe8196e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442374752 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.442374752
Directory /workspace/42.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/42.sram_ctrl_regwen.1324724
Short name T312
Test name
Test status
Simulation time 22310911614 ps
CPU time 192.79 seconds
Started Jan 14 02:31:47 PM PST 24
Finished Jan 14 02:35:00 PM PST 24
Peak memory 311752 kb
Host smart-4ba8beb7-569d-4536-b8cc-adbcdbf11e9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324724 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.1324724
Directory /workspace/42.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/42.sram_ctrl_smoke.1937032056
Short name T273
Test name
Test status
Simulation time 1431553450 ps
CPU time 23.28 seconds
Started Jan 14 02:31:24 PM PST 24
Finished Jan 14 02:31:48 PM PST 24
Peak memory 202100 kb
Host smart-67fa0d79-e9a2-4f47-9140-bca13c42ff49
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937032056 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.1937032056
Directory /workspace/42.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/42.sram_ctrl_stress_all.1811760411
Short name T643
Test name
Test status
Simulation time 565770398502 ps
CPU time 5912.06 seconds
Started Jan 14 02:31:57 PM PST 24
Finished Jan 14 04:10:30 PM PST 24
Peak memory 373372 kb
Host smart-4a6cc1a2-6770-454f-a78d-f904c74aa52d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811760411 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 42.sram_ctrl_stress_all.1811760411
Directory /workspace/42.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.74879462
Short name T466
Test name
Test status
Simulation time 6846026294 ps
CPU time 5714.58 seconds
Started Jan 14 02:31:47 PM PST 24
Finished Jan 14 04:07:03 PM PST 24
Peak memory 698624 kb
Host smart-82e1ec75-676a-43f9-a2a4-0c529edcc853
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=74879462 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all_with_rand_reset.74879462
Directory /workspace/42.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.sram_ctrl_stress_pipeline.1195138448
Short name T578
Test name
Test status
Simulation time 7641706620 ps
CPU time 163.59 seconds
Started Jan 14 02:31:23 PM PST 24
Finished Jan 14 02:34:07 PM PST 24
Peak memory 202180 kb
Host smart-db62a169-b1bf-470a-be39-c9afd42b3102
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195138448 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.sram_ctrl_stress_pipeline.1195138448
Directory /workspace/42.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.1429588826
Short name T228
Test name
Test status
Simulation time 1303827585 ps
CPU time 68.63 seconds
Started Jan 14 02:31:31 PM PST 24
Finished Jan 14 02:32:41 PM PST 24
Peak memory 306492 kb
Host smart-b3acc5e0-6405-47b9-823c-8a140f174dce
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429588826 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 42.sram_ctrl_throughput_w_partial_write.1429588826
Directory /workspace/42.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/43.sram_ctrl_access_during_key_req.550183620
Short name T218
Test name
Test status
Simulation time 20555221409 ps
CPU time 773.23 seconds
Started Jan 14 02:31:57 PM PST 24
Finished Jan 14 02:44:51 PM PST 24
Peak memory 359356 kb
Host smart-dc7eddd9-0c9f-4b0c-977c-80d2eb706cfb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550183620 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 43.sram_ctrl_access_during_key_req.550183620
Directory /workspace/43.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/43.sram_ctrl_alert_test.3127291959
Short name T348
Test name
Test status
Simulation time 22905473 ps
CPU time 0.66 seconds
Started Jan 14 02:32:18 PM PST 24
Finished Jan 14 02:32:20 PM PST 24
Peak memory 201876 kb
Host smart-ba346fbd-3645-4f5d-be76-0985704834ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127291959 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.sram_ctrl_alert_test.3127291959
Directory /workspace/43.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.sram_ctrl_bijection.1428203146
Short name T704
Test name
Test status
Simulation time 132560739242 ps
CPU time 1084.92 seconds
Started Jan 14 02:31:50 PM PST 24
Finished Jan 14 02:49:56 PM PST 24
Peak memory 202236 kb
Host smart-e00fadb0-4b05-4d07-9e6f-ebe4fc8cd58f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428203146 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection
.1428203146
Directory /workspace/43.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/43.sram_ctrl_executable.3408367335
Short name T36
Test name
Test status
Simulation time 87755623774 ps
CPU time 496.37 seconds
Started Jan 14 02:31:58 PM PST 24
Finished Jan 14 02:40:15 PM PST 24
Peak memory 338144 kb
Host smart-3abf992c-8802-4586-b41d-e525194edfa6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408367335 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_executab
le.3408367335
Directory /workspace/43.sram_ctrl_executable/latest

Test location /workspace/coverage/default/43.sram_ctrl_max_throughput.1516931839
Short name T820
Test name
Test status
Simulation time 1359573137 ps
CPU time 27.33 seconds
Started Jan 14 02:31:57 PM PST 24
Finished Jan 14 02:32:25 PM PST 24
Peak memory 210352 kb
Host smart-f91bf72e-4ac5-4056-b0da-ea10738e90ee
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516931839 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 43.sram_ctrl_max_throughput.1516931839
Directory /workspace/43.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/43.sram_ctrl_mem_partial_access.4255112685
Short name T497
Test name
Test status
Simulation time 1986801982 ps
CPU time 75.65 seconds
Started Jan 14 02:32:06 PM PST 24
Finished Jan 14 02:33:23 PM PST 24
Peak memory 211008 kb
Host smart-732326e5-f015-403e-a69c-a4cd2cd72996
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255112685 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.sram_ctrl_mem_partial_access.4255112685
Directory /workspace/43.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/43.sram_ctrl_mem_walk.3946309661
Short name T682
Test name
Test status
Simulation time 28165556763 ps
CPU time 289.04 seconds
Started Jan 14 02:32:07 PM PST 24
Finished Jan 14 02:36:57 PM PST 24
Peak memory 202232 kb
Host smart-1977810a-12c3-436a-8103-831cb018f797
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946309661 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctr
l_mem_walk.3946309661
Directory /workspace/43.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/43.sram_ctrl_multiple_keys.2935076136
Short name T4
Test name
Test status
Simulation time 24040038888 ps
CPU time 1233.65 seconds
Started Jan 14 02:31:51 PM PST 24
Finished Jan 14 02:52:25 PM PST 24
Peak memory 379172 kb
Host smart-8b0c7b0c-db30-46a9-b4ae-3c44aaf4df5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935076136 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multi
ple_keys.2935076136
Directory /workspace/43.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/43.sram_ctrl_partial_access.3207042066
Short name T399
Test name
Test status
Simulation time 9944286608 ps
CPU time 24.03 seconds
Started Jan 14 02:31:50 PM PST 24
Finished Jan 14 02:32:15 PM PST 24
Peak memory 202088 kb
Host smart-c99e14e5-ec9a-4316-a462-5d0d209a4142
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207042066 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
sram_ctrl_partial_access.3207042066
Directory /workspace/43.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.1265892320
Short name T874
Test name
Test status
Simulation time 386754520985 ps
CPU time 478.19 seconds
Started Jan 14 02:31:58 PM PST 24
Finished Jan 14 02:39:57 PM PST 24
Peak memory 202168 kb
Host smart-053c3400-f062-4c8c-8d7c-b3f6cc740d03
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265892320 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 43.sram_ctrl_partial_access_b2b.1265892320
Directory /workspace/43.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/43.sram_ctrl_ram_cfg.183397795
Short name T575
Test name
Test status
Simulation time 1348373982 ps
CPU time 13.56 seconds
Started Jan 14 02:32:04 PM PST 24
Finished Jan 14 02:32:19 PM PST 24
Peak memory 202404 kb
Host smart-42eabdb3-cfeb-4070-bfde-24ab5697e40d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183397795 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.183397795
Directory /workspace/43.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/43.sram_ctrl_regwen.480332640
Short name T821
Test name
Test status
Simulation time 78346505674 ps
CPU time 1470.66 seconds
Started Jan 14 02:31:59 PM PST 24
Finished Jan 14 02:56:30 PM PST 24
Peak memory 373952 kb
Host smart-828dd211-efad-4a06-b450-b83fb163d544
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480332640 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.480332640
Directory /workspace/43.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/43.sram_ctrl_smoke.3890084122
Short name T410
Test name
Test status
Simulation time 3638752481 ps
CPU time 43.77 seconds
Started Jan 14 02:31:56 PM PST 24
Finished Jan 14 02:32:41 PM PST 24
Peak memory 202140 kb
Host smart-52d24990-4a98-4ebc-9a10-d6b6304bbbbb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890084122 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.3890084122
Directory /workspace/43.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/43.sram_ctrl_stress_all.796965116
Short name T722
Test name
Test status
Simulation time 242046730744 ps
CPU time 7620.88 seconds
Started Jan 14 02:32:05 PM PST 24
Finished Jan 14 04:39:07 PM PST 24
Peak memory 379180 kb
Host smart-968a0db5-2056-4c6b-bf1f-d53be8c3d152
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796965116 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 43.sram_ctrl_stress_all.796965116
Directory /workspace/43.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.3958939290
Short name T107
Test name
Test status
Simulation time 2955006057 ps
CPU time 4701.74 seconds
Started Jan 14 02:32:04 PM PST 24
Finished Jan 14 03:50:27 PM PST 24
Peak memory 418224 kb
Host smart-3a5c809c-7731-45b1-ae5e-978f9adbd62b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3958939290 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all_with_rand_reset.3958939290
Directory /workspace/43.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.sram_ctrl_stress_pipeline.3718296811
Short name T49
Test name
Test status
Simulation time 3737953537 ps
CPU time 295.83 seconds
Started Jan 14 02:31:52 PM PST 24
Finished Jan 14 02:36:48 PM PST 24
Peak memory 202188 kb
Host smart-4ea1e912-6c59-4df1-91b3-fba07369cbbe
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718296811 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.sram_ctrl_stress_pipeline.3718296811
Directory /workspace/43.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.3771306828
Short name T307
Test name
Test status
Simulation time 727367371 ps
CPU time 37.77 seconds
Started Jan 14 02:31:59 PM PST 24
Finished Jan 14 02:32:37 PM PST 24
Peak memory 250276 kb
Host smart-115da71f-db37-4bcd-9665-7127e67a03d9
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771306828 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.sram_ctrl_throughput_w_partial_write.3771306828
Directory /workspace/43.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/44.sram_ctrl_access_during_key_req.467791474
Short name T529
Test name
Test status
Simulation time 38174510161 ps
CPU time 1285.64 seconds
Started Jan 14 02:32:23 PM PST 24
Finished Jan 14 02:53:53 PM PST 24
Peak memory 376040 kb
Host smart-474ab675-2590-40aa-a8e0-1225305c2be3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467791474 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 44.sram_ctrl_access_during_key_req.467791474
Directory /workspace/44.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/44.sram_ctrl_alert_test.3821675488
Short name T237
Test name
Test status
Simulation time 14930512 ps
CPU time 0.65 seconds
Started Jan 14 02:32:38 PM PST 24
Finished Jan 14 02:32:42 PM PST 24
Peak memory 201912 kb
Host smart-f1fd0304-1ec6-4924-a891-a65eed08c472
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821675488 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.sram_ctrl_alert_test.3821675488
Directory /workspace/44.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.sram_ctrl_bijection.358601418
Short name T294
Test name
Test status
Simulation time 103822260230 ps
CPU time 1346.97 seconds
Started Jan 14 02:32:22 PM PST 24
Finished Jan 14 02:54:55 PM PST 24
Peak memory 202164 kb
Host smart-435b3c78-a10a-45ec-a7dc-76b65646d73e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358601418 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection.
358601418
Directory /workspace/44.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/44.sram_ctrl_executable.2394457923
Short name T427
Test name
Test status
Simulation time 120401963598 ps
CPU time 508.09 seconds
Started Jan 14 02:32:27 PM PST 24
Finished Jan 14 02:40:58 PM PST 24
Peak memory 359620 kb
Host smart-b2ebcb38-5ede-4c5f-83ce-c578580dd063
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394457923 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_executab
le.2394457923
Directory /workspace/44.sram_ctrl_executable/latest

Test location /workspace/coverage/default/44.sram_ctrl_lc_escalation.2093607178
Short name T822
Test name
Test status
Simulation time 3982043964 ps
CPU time 40.69 seconds
Started Jan 14 02:32:29 PM PST 24
Finished Jan 14 02:33:13 PM PST 24
Peak memory 210340 kb
Host smart-02e5b906-50d0-4e30-8e0f-6e13dc9536eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093607178 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_es
calation.2093607178
Directory /workspace/44.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/44.sram_ctrl_max_throughput.3410013893
Short name T344
Test name
Test status
Simulation time 3185110965 ps
CPU time 165.63 seconds
Started Jan 14 02:32:23 PM PST 24
Finished Jan 14 02:35:13 PM PST 24
Peak memory 366796 kb
Host smart-95800496-b2da-456e-8602-61241ece6548
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410013893 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 44.sram_ctrl_max_throughput.3410013893
Directory /workspace/44.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/44.sram_ctrl_mem_partial_access.581894995
Short name T398
Test name
Test status
Simulation time 9047008284 ps
CPU time 78.94 seconds
Started Jan 14 02:32:38 PM PST 24
Finished Jan 14 02:34:00 PM PST 24
Peak memory 211944 kb
Host smart-ecc8501d-5d06-4232-b51e-9ca57ccd5c87
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581894995 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.sram_ctrl_mem_partial_access.581894995
Directory /workspace/44.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/44.sram_ctrl_mem_walk.1345584792
Short name T848
Test name
Test status
Simulation time 14330938890 ps
CPU time 299.78 seconds
Started Jan 14 02:32:28 PM PST 24
Finished Jan 14 02:37:31 PM PST 24
Peak memory 202232 kb
Host smart-01cf6ad3-4617-4a30-af15-b09e2db855bf
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345584792 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctr
l_mem_walk.1345584792
Directory /workspace/44.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/44.sram_ctrl_multiple_keys.3167169642
Short name T340
Test name
Test status
Simulation time 22241921607 ps
CPU time 775.32 seconds
Started Jan 14 02:32:18 PM PST 24
Finished Jan 14 02:45:15 PM PST 24
Peak memory 377396 kb
Host smart-be69f9fc-b54f-494e-a67b-7c05cdb3c6af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167169642 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multi
ple_keys.3167169642
Directory /workspace/44.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/44.sram_ctrl_partial_access.2827403398
Short name T900
Test name
Test status
Simulation time 6520274734 ps
CPU time 32.86 seconds
Started Jan 14 02:32:17 PM PST 24
Finished Jan 14 02:32:52 PM PST 24
Peak memory 202148 kb
Host smart-7900343a-86a3-4c75-bf04-3a2f8edf619b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827403398 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
sram_ctrl_partial_access.2827403398
Directory /workspace/44.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.3832285626
Short name T831
Test name
Test status
Simulation time 15501127417 ps
CPU time 371.14 seconds
Started Jan 14 02:32:29 PM PST 24
Finished Jan 14 02:38:43 PM PST 24
Peak memory 202172 kb
Host smart-9ba9bd50-393d-4afa-af4a-17252c1c0b9f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832285626 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 44.sram_ctrl_partial_access_b2b.3832285626
Directory /workspace/44.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/44.sram_ctrl_ram_cfg.1972446007
Short name T378
Test name
Test status
Simulation time 1532261823 ps
CPU time 13.71 seconds
Started Jan 14 02:32:20 PM PST 24
Finished Jan 14 02:32:35 PM PST 24
Peak memory 202424 kb
Host smart-b1f70633-0b7f-4c92-8edf-07db50103b0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972446007 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.1972446007
Directory /workspace/44.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/44.sram_ctrl_regwen.4011127353
Short name T602
Test name
Test status
Simulation time 10491436768 ps
CPU time 387.47 seconds
Started Jan 14 02:32:30 PM PST 24
Finished Jan 14 02:39:00 PM PST 24
Peak memory 374908 kb
Host smart-a21b9cac-cb11-4b4a-a532-ebef36a801dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011127353 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.4011127353
Directory /workspace/44.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/44.sram_ctrl_smoke.215462286
Short name T877
Test name
Test status
Simulation time 8875120671 ps
CPU time 22.97 seconds
Started Jan 14 02:32:17 PM PST 24
Finished Jan 14 02:32:42 PM PST 24
Peak memory 202152 kb
Host smart-daebd6d3-784c-4fa3-a8cf-5a7467f92bc7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215462286 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.215462286
Directory /workspace/44.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/44.sram_ctrl_stress_all.3710256389
Short name T742
Test name
Test status
Simulation time 111160873097 ps
CPU time 5424.14 seconds
Started Jan 14 02:32:39 PM PST 24
Finished Jan 14 04:03:07 PM PST 24
Peak memory 378140 kb
Host smart-ccb6ad4b-16c0-47e4-a5b2-f2da41902cc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710256389 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 44.sram_ctrl_stress_all.3710256389
Directory /workspace/44.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.1708140935
Short name T543
Test name
Test status
Simulation time 1309040585 ps
CPU time 5681.98 seconds
Started Jan 14 02:32:38 PM PST 24
Finished Jan 14 04:07:24 PM PST 24
Peak memory 594280 kb
Host smart-ab64d19b-bf64-4ae1-b905-b704cae4d7c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1708140935 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_all_with_rand_reset.1708140935
Directory /workspace/44.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.sram_ctrl_stress_pipeline.3872184663
Short name T814
Test name
Test status
Simulation time 5174905024 ps
CPU time 404.56 seconds
Started Jan 14 02:32:20 PM PST 24
Finished Jan 14 02:39:06 PM PST 24
Peak memory 202108 kb
Host smart-2e8e0ce0-367c-4d27-b725-7c5eb7478446
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872184663 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.sram_ctrl_stress_pipeline.3872184663
Directory /workspace/44.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.367892041
Short name T648
Test name
Test status
Simulation time 3000703816 ps
CPU time 92.85 seconds
Started Jan 14 02:32:27 PM PST 24
Finished Jan 14 02:34:02 PM PST 24
Peak memory 329176 kb
Host smart-e3141a93-30bd-4dc3-9a91-b5193528fce5
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367892041 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 44.sram_ctrl_throughput_w_partial_write.367892041
Directory /workspace/44.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/45.sram_ctrl_access_during_key_req.2849211753
Short name T753
Test name
Test status
Simulation time 10819315864 ps
CPU time 835.72 seconds
Started Jan 14 02:32:39 PM PST 24
Finished Jan 14 02:46:38 PM PST 24
Peak memory 379044 kb
Host smart-050b0683-fec0-40e3-88a7-db7a03e8731e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849211753 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.sram_ctrl_access_during_key_req.2849211753
Directory /workspace/45.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/45.sram_ctrl_alert_test.3025004569
Short name T327
Test name
Test status
Simulation time 13522436 ps
CPU time 0.78 seconds
Started Jan 14 02:32:47 PM PST 24
Finished Jan 14 02:32:49 PM PST 24
Peak memory 201860 kb
Host smart-3241dfee-c8d2-4f32-8a58-161e23805687
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025004569 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.sram_ctrl_alert_test.3025004569
Directory /workspace/45.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.sram_ctrl_bijection.1006529361
Short name T614
Test name
Test status
Simulation time 399429215458 ps
CPU time 1503.76 seconds
Started Jan 14 02:32:31 PM PST 24
Finished Jan 14 02:57:36 PM PST 24
Peak memory 202180 kb
Host smart-f0da82d2-b459-4a13-8623-e0584e920352
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006529361 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection
.1006529361
Directory /workspace/45.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/45.sram_ctrl_lc_escalation.3243583384
Short name T797
Test name
Test status
Simulation time 13057349560 ps
CPU time 112.56 seconds
Started Jan 14 02:32:40 PM PST 24
Finished Jan 14 02:34:37 PM PST 24
Peak memory 210408 kb
Host smart-797f2b01-9bd0-425b-b901-45fe99a6554e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243583384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_lc_es
calation.3243583384
Directory /workspace/45.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/45.sram_ctrl_max_throughput.1563067351
Short name T438
Test name
Test status
Simulation time 1506898320 ps
CPU time 65.55 seconds
Started Jan 14 02:32:38 PM PST 24
Finished Jan 14 02:33:47 PM PST 24
Peak memory 294068 kb
Host smart-2868792a-d594-4d0f-a201-a28b97eb9074
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563067351 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 45.sram_ctrl_max_throughput.1563067351
Directory /workspace/45.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/45.sram_ctrl_mem_partial_access.3383849357
Short name T354
Test name
Test status
Simulation time 19512936646 ps
CPU time 159.81 seconds
Started Jan 14 02:32:46 PM PST 24
Finished Jan 14 02:35:27 PM PST 24
Peak memory 211720 kb
Host smart-75697cde-c40c-48e5-a675-407522cb3670
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383849357 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.sram_ctrl_mem_partial_access.3383849357
Directory /workspace/45.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/45.sram_ctrl_mem_walk.531692547
Short name T513
Test name
Test status
Simulation time 10658239525 ps
CPU time 149.05 seconds
Started Jan 14 02:32:47 PM PST 24
Finished Jan 14 02:35:18 PM PST 24
Peak memory 202188 kb
Host smart-5759510b-7e30-4ed8-90c9-02cd3a2e847e
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531692547 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl
_mem_walk.531692547
Directory /workspace/45.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/45.sram_ctrl_multiple_keys.3202616636
Short name T371
Test name
Test status
Simulation time 10633632445 ps
CPU time 782.75 seconds
Started Jan 14 02:32:37 PM PST 24
Finished Jan 14 02:45:44 PM PST 24
Peak memory 375656 kb
Host smart-c89da5fb-c6c8-43f4-a16d-3577263f64ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202616636 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multi
ple_keys.3202616636
Directory /workspace/45.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/45.sram_ctrl_partial_access.1011827677
Short name T868
Test name
Test status
Simulation time 1363449196 ps
CPU time 6.35 seconds
Started Jan 14 02:32:38 PM PST 24
Finished Jan 14 02:32:47 PM PST 24
Peak memory 202116 kb
Host smart-b53411cb-788a-4e0e-bdbc-c1868570c4fa
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011827677 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
sram_ctrl_partial_access.1011827677
Directory /workspace/45.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.3861887194
Short name T521
Test name
Test status
Simulation time 16720639846 ps
CPU time 244.25 seconds
Started Jan 14 02:32:39 PM PST 24
Finished Jan 14 02:36:46 PM PST 24
Peak memory 202156 kb
Host smart-7df02591-0d43-478d-985f-4a121e28ca0e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861887194 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 45.sram_ctrl_partial_access_b2b.3861887194
Directory /workspace/45.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/45.sram_ctrl_ram_cfg.3505045423
Short name T556
Test name
Test status
Simulation time 700907141 ps
CPU time 13.77 seconds
Started Jan 14 02:32:45 PM PST 24
Finished Jan 14 02:33:00 PM PST 24
Peak memory 202352 kb
Host smart-11f77cdc-23e7-4614-9856-a7c271abc215
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505045423 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.3505045423
Directory /workspace/45.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/45.sram_ctrl_regwen.2346970148
Short name T297
Test name
Test status
Simulation time 5442014293 ps
CPU time 222.65 seconds
Started Jan 14 02:32:48 PM PST 24
Finished Jan 14 02:36:32 PM PST 24
Peak memory 370836 kb
Host smart-bdcddec4-b4cf-4b5f-8343-eeb691a33b19
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346970148 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.2346970148
Directory /workspace/45.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/45.sram_ctrl_smoke.14346937
Short name T937
Test name
Test status
Simulation time 1068471677 ps
CPU time 26.14 seconds
Started Jan 14 02:32:37 PM PST 24
Finished Jan 14 02:33:07 PM PST 24
Peak memory 202096 kb
Host smart-40b1777b-b2df-4ec7-8ce3-bd726c90aafc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14346937 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.14346937
Directory /workspace/45.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/45.sram_ctrl_stress_all.945622423
Short name T545
Test name
Test status
Simulation time 764112781208 ps
CPU time 3565.88 seconds
Started Jan 14 02:32:47 PM PST 24
Finished Jan 14 03:32:14 PM PST 24
Peak memory 376968 kb
Host smart-a26bd4ee-f863-4a72-8ddb-617f3b7f338d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945622423 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 45.sram_ctrl_stress_all.945622423
Directory /workspace/45.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.2300561544
Short name T972
Test name
Test status
Simulation time 5621549189 ps
CPU time 4060.99 seconds
Started Jan 14 02:32:45 PM PST 24
Finished Jan 14 03:40:28 PM PST 24
Peak memory 632540 kb
Host smart-b2763171-f8f9-4e49-934b-8e54b2ff70ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2300561544 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all_with_rand_reset.2300561544
Directory /workspace/45.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.sram_ctrl_stress_pipeline.1527530463
Short name T428
Test name
Test status
Simulation time 3234410259 ps
CPU time 232.09 seconds
Started Jan 14 02:32:36 PM PST 24
Finished Jan 14 02:36:33 PM PST 24
Peak memory 202172 kb
Host smart-1e1c0f46-4c8d-4e2b-b4a5-3e05ebf90461
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527530463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.sram_ctrl_stress_pipeline.1527530463
Directory /workspace/45.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.403483479
Short name T1
Test name
Test status
Simulation time 722780723 ps
CPU time 33.13 seconds
Started Jan 14 02:32:41 PM PST 24
Finished Jan 14 02:33:18 PM PST 24
Peak memory 238496 kb
Host smart-1dadd5e4-58a7-41d2-b7d9-c80bdf97c788
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403483479 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 45.sram_ctrl_throughput_w_partial_write.403483479
Directory /workspace/45.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/46.sram_ctrl_access_during_key_req.1304179850
Short name T411
Test name
Test status
Simulation time 10052680154 ps
CPU time 1587.34 seconds
Started Jan 14 02:33:09 PM PST 24
Finished Jan 14 02:59:37 PM PST 24
Peak memory 378056 kb
Host smart-583bbbf1-2789-4e05-8102-426087b4b6a6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304179850 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 46.sram_ctrl_access_during_key_req.1304179850
Directory /workspace/46.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/46.sram_ctrl_alert_test.1622056168
Short name T698
Test name
Test status
Simulation time 32865549 ps
CPU time 0.67 seconds
Started Jan 14 02:33:17 PM PST 24
Finished Jan 14 02:33:19 PM PST 24
Peak memory 201960 kb
Host smart-12937a99-60b5-4c66-9fc0-5e4aeb5a8ad0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622056168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.sram_ctrl_alert_test.1622056168
Directory /workspace/46.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.sram_ctrl_bijection.122020114
Short name T498
Test name
Test status
Simulation time 25835670675 ps
CPU time 1839.02 seconds
Started Jan 14 02:32:45 PM PST 24
Finished Jan 14 03:03:25 PM PST 24
Peak memory 202268 kb
Host smart-90afa0bd-a306-4ca8-b5cc-a74774369223
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122020114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection.
122020114
Directory /workspace/46.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/46.sram_ctrl_executable.3819479441
Short name T749
Test name
Test status
Simulation time 3070936550 ps
CPU time 35.42 seconds
Started Jan 14 02:33:06 PM PST 24
Finished Jan 14 02:33:42 PM PST 24
Peak memory 244072 kb
Host smart-7d0e8957-f6b2-458d-ac7d-cc74ce3c4fc4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819479441 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_executab
le.3819479441
Directory /workspace/46.sram_ctrl_executable/latest

Test location /workspace/coverage/default/46.sram_ctrl_lc_escalation.3908513687
Short name T788
Test name
Test status
Simulation time 35332178939 ps
CPU time 50.48 seconds
Started Jan 14 02:33:08 PM PST 24
Finished Jan 14 02:34:00 PM PST 24
Peak memory 210484 kb
Host smart-52d101a0-76b0-48ee-9f35-431267e6b1fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908513687 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_es
calation.3908513687
Directory /workspace/46.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/46.sram_ctrl_max_throughput.3482668060
Short name T879
Test name
Test status
Simulation time 1564098583 ps
CPU time 143.08 seconds
Started Jan 14 02:32:50 PM PST 24
Finished Jan 14 02:35:15 PM PST 24
Peak memory 375068 kb
Host smart-9729d720-2f13-41b4-9431-8ca4196deaaf
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482668060 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 46.sram_ctrl_max_throughput.3482668060
Directory /workspace/46.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/46.sram_ctrl_mem_partial_access.2246777713
Short name T242
Test name
Test status
Simulation time 1673781202 ps
CPU time 134.43 seconds
Started Jan 14 02:33:11 PM PST 24
Finished Jan 14 02:35:27 PM PST 24
Peak memory 211140 kb
Host smart-2bbe3b75-e6b2-4f9a-ac46-7e939ff288be
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246777713 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.sram_ctrl_mem_partial_access.2246777713
Directory /workspace/46.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/46.sram_ctrl_mem_walk.317392866
Short name T332
Test name
Test status
Simulation time 4022778933 ps
CPU time 255.85 seconds
Started Jan 14 02:33:12 PM PST 24
Finished Jan 14 02:37:30 PM PST 24
Peak memory 202288 kb
Host smart-fead5437-eac8-4a60-a2f3-3fc9ef4932c2
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317392866 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl
_mem_walk.317392866
Directory /workspace/46.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/46.sram_ctrl_multiple_keys.1153863586
Short name T561
Test name
Test status
Simulation time 11406261038 ps
CPU time 924.77 seconds
Started Jan 14 02:32:46 PM PST 24
Finished Jan 14 02:48:12 PM PST 24
Peak memory 379184 kb
Host smart-c5003e01-bb8c-49f1-8fc5-e2e9fab59855
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153863586 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multi
ple_keys.1153863586
Directory /workspace/46.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/46.sram_ctrl_partial_access.949447637
Short name T815
Test name
Test status
Simulation time 1226164818 ps
CPU time 28.14 seconds
Started Jan 14 02:32:51 PM PST 24
Finished Jan 14 02:33:21 PM PST 24
Peak memory 202140 kb
Host smart-3a18723c-0779-4650-a0c4-c0babb48e4ff
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949447637 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.s
ram_ctrl_partial_access.949447637
Directory /workspace/46.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.3414750267
Short name T915
Test name
Test status
Simulation time 21867800495 ps
CPU time 399.63 seconds
Started Jan 14 02:32:51 PM PST 24
Finished Jan 14 02:39:32 PM PST 24
Peak memory 202188 kb
Host smart-753a0370-d3d0-4e67-a781-a32c73eb238a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414750267 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 46.sram_ctrl_partial_access_b2b.3414750267
Directory /workspace/46.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/46.sram_ctrl_ram_cfg.2262436337
Short name T801
Test name
Test status
Simulation time 800419770 ps
CPU time 14.92 seconds
Started Jan 14 02:33:13 PM PST 24
Finished Jan 14 02:33:29 PM PST 24
Peak memory 202528 kb
Host smart-1f8c4e72-960e-4d10-be92-3999c5ce5314
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262436337 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.2262436337
Directory /workspace/46.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/46.sram_ctrl_regwen.3919430472
Short name T772
Test name
Test status
Simulation time 39075450290 ps
CPU time 803.19 seconds
Started Jan 14 02:33:02 PM PST 24
Finished Jan 14 02:46:26 PM PST 24
Peak memory 374000 kb
Host smart-7da7afe6-499b-4761-a6ee-ed8304137aaa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919430472 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.3919430472
Directory /workspace/46.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/46.sram_ctrl_smoke.2635342228
Short name T734
Test name
Test status
Simulation time 2104380683 ps
CPU time 26.05 seconds
Started Jan 14 02:32:47 PM PST 24
Finished Jan 14 02:33:14 PM PST 24
Peak memory 202068 kb
Host smart-dd37644a-d461-47be-b2c0-2845d60e86db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635342228 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.2635342228
Directory /workspace/46.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/46.sram_ctrl_stress_all.193755914
Short name T770
Test name
Test status
Simulation time 372693894608 ps
CPU time 7067.98 seconds
Started Jan 14 02:33:13 PM PST 24
Finished Jan 14 04:31:03 PM PST 24
Peak memory 380124 kb
Host smart-bb4f7cea-69a3-4f83-8bf7-6f37c2018728
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193755914 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 46.sram_ctrl_stress_all.193755914
Directory /workspace/46.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.2809483824
Short name T785
Test name
Test status
Simulation time 3188170857 ps
CPU time 2653.61 seconds
Started Jan 14 02:33:13 PM PST 24
Finished Jan 14 03:17:28 PM PST 24
Peak memory 573032 kb
Host smart-1f23db0e-cc21-48fd-b597-13cac84a2935
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2809483824 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all_with_rand_reset.2809483824
Directory /workspace/46.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.sram_ctrl_stress_pipeline.1844082327
Short name T316
Test name
Test status
Simulation time 3840127771 ps
CPU time 310.96 seconds
Started Jan 14 02:32:48 PM PST 24
Finished Jan 14 02:38:01 PM PST 24
Peak memory 202188 kb
Host smart-d5fbc8b0-ed66-4cd6-94c2-312e647c4ec3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844082327 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.sram_ctrl_stress_pipeline.1844082327
Directory /workspace/46.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.3889269769
Short name T457
Test name
Test status
Simulation time 3415712414 ps
CPU time 52.95 seconds
Started Jan 14 02:32:52 PM PST 24
Finished Jan 14 02:33:46 PM PST 24
Peak memory 272788 kb
Host smart-11bf1a48-ea6e-4aa3-9896-0d3904f78b9a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889269769 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.sram_ctrl_throughput_w_partial_write.3889269769
Directory /workspace/46.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/47.sram_ctrl_access_during_key_req.2158088315
Short name T423
Test name
Test status
Simulation time 13298337531 ps
CPU time 2196.56 seconds
Started Jan 14 02:33:28 PM PST 24
Finished Jan 14 03:10:06 PM PST 24
Peak memory 380156 kb
Host smart-b9fd8295-0bca-4b80-b889-cf047917ee2e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158088315 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 47.sram_ctrl_access_during_key_req.2158088315
Directory /workspace/47.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/47.sram_ctrl_alert_test.1434910022
Short name T854
Test name
Test status
Simulation time 107781118 ps
CPU time 0.69 seconds
Started Jan 14 02:33:34 PM PST 24
Finished Jan 14 02:33:36 PM PST 24
Peak memory 201892 kb
Host smart-b8c40fd5-f5d6-4aca-9d74-6091090327d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434910022 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.sram_ctrl_alert_test.1434910022
Directory /workspace/47.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.sram_ctrl_bijection.2226315149
Short name T361
Test name
Test status
Simulation time 259408037295 ps
CPU time 1069.86 seconds
Started Jan 14 02:33:24 PM PST 24
Finished Jan 14 02:51:14 PM PST 24
Peak memory 202128 kb
Host smart-9162ca56-0b61-4069-ae41-e0a3f608c34e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226315149 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection
.2226315149
Directory /workspace/47.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/47.sram_ctrl_executable.2511083488
Short name T520
Test name
Test status
Simulation time 15312696782 ps
CPU time 590.34 seconds
Started Jan 14 02:33:27 PM PST 24
Finished Jan 14 02:43:19 PM PST 24
Peak memory 364784 kb
Host smart-a88bf0af-9d6d-4d2c-903f-907856c8de6d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511083488 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_executab
le.2511083488
Directory /workspace/47.sram_ctrl_executable/latest

Test location /workspace/coverage/default/47.sram_ctrl_lc_escalation.2299945552
Short name T960
Test name
Test status
Simulation time 4461196694 ps
CPU time 31.71 seconds
Started Jan 14 02:33:29 PM PST 24
Finished Jan 14 02:34:01 PM PST 24
Peak memory 210404 kb
Host smart-12db6de7-603b-4d25-bd09-46419aec4e19
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299945552 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_es
calation.2299945552
Directory /workspace/47.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/47.sram_ctrl_max_throughput.2545964336
Short name T613
Test name
Test status
Simulation time 776621779 ps
CPU time 85.09 seconds
Started Jan 14 02:33:26 PM PST 24
Finished Jan 14 02:34:52 PM PST 24
Peak memory 315540 kb
Host smart-06b31f34-7044-4527-8371-874782019a8a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545964336 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 47.sram_ctrl_max_throughput.2545964336
Directory /workspace/47.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/47.sram_ctrl_mem_partial_access.1693771186
Short name T492
Test name
Test status
Simulation time 9013821107 ps
CPU time 80.41 seconds
Started Jan 14 02:33:27 PM PST 24
Finished Jan 14 02:34:49 PM PST 24
Peak memory 211172 kb
Host smart-ba638354-7198-43be-afbf-1266dd88bf35
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693771186 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.sram_ctrl_mem_partial_access.1693771186
Directory /workspace/47.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/47.sram_ctrl_mem_walk.1569532082
Short name T99
Test name
Test status
Simulation time 10756155847 ps
CPU time 155.86 seconds
Started Jan 14 02:33:28 PM PST 24
Finished Jan 14 02:36:05 PM PST 24
Peak memory 202136 kb
Host smart-19ace62f-46a3-4d07-a423-cf01ace91afc
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569532082 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctr
l_mem_walk.1569532082
Directory /workspace/47.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/47.sram_ctrl_multiple_keys.3842887278
Short name T598
Test name
Test status
Simulation time 29679941307 ps
CPU time 871.51 seconds
Started Jan 14 02:33:25 PM PST 24
Finished Jan 14 02:47:58 PM PST 24
Peak memory 375964 kb
Host smart-bc04f493-338e-4f54-9dbb-5e22e6e8fc8e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842887278 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multi
ple_keys.3842887278
Directory /workspace/47.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/47.sram_ctrl_partial_access.2828111834
Short name T735
Test name
Test status
Simulation time 428037144 ps
CPU time 40.98 seconds
Started Jan 14 02:33:21 PM PST 24
Finished Jan 14 02:34:03 PM PST 24
Peak memory 268804 kb
Host smart-0f62b235-d2f2-4aa1-964c-394c1a752da0
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828111834 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
sram_ctrl_partial_access.2828111834
Directory /workspace/47.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.4219178917
Short name T842
Test name
Test status
Simulation time 37437884470 ps
CPU time 462.08 seconds
Started Jan 14 02:33:26 PM PST 24
Finished Jan 14 02:41:09 PM PST 24
Peak memory 202164 kb
Host smart-f96ef6bd-eee0-4c28-9ed3-fc462a6f76f1
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219178917 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 47.sram_ctrl_partial_access_b2b.4219178917
Directory /workspace/47.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/47.sram_ctrl_ram_cfg.1406079931
Short name T380
Test name
Test status
Simulation time 360037757 ps
CPU time 6.59 seconds
Started Jan 14 02:33:27 PM PST 24
Finished Jan 14 02:33:34 PM PST 24
Peak memory 202444 kb
Host smart-d29bb0e5-be45-4c6c-beb2-58db1cdb27d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406079931 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.1406079931
Directory /workspace/47.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/47.sram_ctrl_regwen.3088151557
Short name T353
Test name
Test status
Simulation time 12883198197 ps
CPU time 949.04 seconds
Started Jan 14 02:33:27 PM PST 24
Finished Jan 14 02:49:17 PM PST 24
Peak memory 373488 kb
Host smart-b8a2c4dc-a573-43f4-8a1a-39850dc03969
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088151557 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.3088151557
Directory /workspace/47.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/47.sram_ctrl_smoke.2277045401
Short name T104
Test name
Test status
Simulation time 873779482 ps
CPU time 20.05 seconds
Started Jan 14 02:33:27 PM PST 24
Finished Jan 14 02:33:48 PM PST 24
Peak memory 243184 kb
Host smart-fb072f88-c894-4620-aa47-71a7c126c067
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277045401 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.2277045401
Directory /workspace/47.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/47.sram_ctrl_stress_all.1506576150
Short name T828
Test name
Test status
Simulation time 132680689918 ps
CPU time 3763.87 seconds
Started Jan 14 02:33:35 PM PST 24
Finished Jan 14 03:36:20 PM PST 24
Peak memory 381180 kb
Host smart-6f64fdb4-5299-4a82-be9e-4d931e9ac075
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506576150 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 47.sram_ctrl_stress_all.1506576150
Directory /workspace/47.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1805905072
Short name T884
Test name
Test status
Simulation time 290951225 ps
CPU time 2713.49 seconds
Started Jan 14 02:33:36 PM PST 24
Finished Jan 14 03:18:50 PM PST 24
Peak memory 519252 kb
Host smart-5308f94d-77a4-4723-971d-fc70a351e2f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1805905072 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all_with_rand_reset.1805905072
Directory /workspace/47.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.sram_ctrl_stress_pipeline.2211464256
Short name T454
Test name
Test status
Simulation time 15455455592 ps
CPU time 263.78 seconds
Started Jan 14 02:33:27 PM PST 24
Finished Jan 14 02:37:52 PM PST 24
Peak memory 202164 kb
Host smart-4264ecd9-2fa6-4344-a8a5-ee6761d14af7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211464256 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.sram_ctrl_stress_pipeline.2211464256
Directory /workspace/47.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.734790372
Short name T901
Test name
Test status
Simulation time 2214426386 ps
CPU time 91.96 seconds
Started Jan 14 02:33:26 PM PST 24
Finished Jan 14 02:34:59 PM PST 24
Peak memory 327776 kb
Host smart-9720192a-1a80-4349-aed9-98f84016ca66
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734790372 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 47.sram_ctrl_throughput_w_partial_write.734790372
Directory /workspace/47.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/48.sram_ctrl_access_during_key_req.1620490964
Short name T315
Test name
Test status
Simulation time 1176818598 ps
CPU time 35.76 seconds
Started Jan 14 02:33:47 PM PST 24
Finished Jan 14 02:34:24 PM PST 24
Peak memory 202660 kb
Host smart-52ad48cb-dbd7-4413-884d-c27fe73570eb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620490964 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 48.sram_ctrl_access_during_key_req.1620490964
Directory /workspace/48.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/48.sram_ctrl_alert_test.2405579711
Short name T530
Test name
Test status
Simulation time 40393204 ps
CPU time 0.66 seconds
Started Jan 14 02:33:56 PM PST 24
Finished Jan 14 02:33:58 PM PST 24
Peak memory 201520 kb
Host smart-eec7d644-5fba-46fd-9b61-cf775d94197b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405579711 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.sram_ctrl_alert_test.2405579711
Directory /workspace/48.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.sram_ctrl_bijection.3720305841
Short name T713
Test name
Test status
Simulation time 12150515530 ps
CPU time 837.46 seconds
Started Jan 14 02:33:34 PM PST 24
Finished Jan 14 02:47:34 PM PST 24
Peak memory 202212 kb
Host smart-525cd072-b4e5-47bc-9be3-e81a1f18b7d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720305841 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection
.3720305841
Directory /workspace/48.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/48.sram_ctrl_lc_escalation.1972524500
Short name T487
Test name
Test status
Simulation time 2735207106 ps
CPU time 72.94 seconds
Started Jan 14 02:33:45 PM PST 24
Finished Jan 14 02:34:59 PM PST 24
Peak memory 202316 kb
Host smart-2a42775f-3165-466a-8de1-1c7c6e0cbf15
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972524500 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_es
calation.1972524500
Directory /workspace/48.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/48.sram_ctrl_max_throughput.1660975556
Short name T248
Test name
Test status
Simulation time 878519157 ps
CPU time 139.46 seconds
Started Jan 14 02:33:41 PM PST 24
Finished Jan 14 02:36:02 PM PST 24
Peak memory 344248 kb
Host smart-b60d6ac6-d570-4c7a-a69b-b84987be27ab
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660975556 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 48.sram_ctrl_max_throughput.1660975556
Directory /workspace/48.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/48.sram_ctrl_mem_partial_access.1100651521
Short name T802
Test name
Test status
Simulation time 19732703705 ps
CPU time 159.41 seconds
Started Jan 14 02:33:56 PM PST 24
Finished Jan 14 02:36:37 PM PST 24
Peak memory 211224 kb
Host smart-141c4bd2-fefb-4953-a6f7-2ed6a6b15316
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100651521 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.sram_ctrl_mem_partial_access.1100651521
Directory /workspace/48.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/48.sram_ctrl_mem_walk.2548851329
Short name T909
Test name
Test status
Simulation time 86019441094 ps
CPU time 337.84 seconds
Started Jan 14 02:33:47 PM PST 24
Finished Jan 14 02:39:26 PM PST 24
Peak memory 202304 kb
Host smart-b732aab6-b08a-492d-a5f1-40a0384fabdf
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548851329 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctr
l_mem_walk.2548851329
Directory /workspace/48.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/48.sram_ctrl_multiple_keys.2121929640
Short name T895
Test name
Test status
Simulation time 17341770061 ps
CPU time 1161.56 seconds
Started Jan 14 02:33:36 PM PST 24
Finished Jan 14 02:52:59 PM PST 24
Peak memory 368940 kb
Host smart-76d78011-6e70-4947-9f56-fe5f90fc9ba7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121929640 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multi
ple_keys.2121929640
Directory /workspace/48.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/48.sram_ctrl_partial_access.3352206748
Short name T5
Test name
Test status
Simulation time 5100886109 ps
CPU time 22.98 seconds
Started Jan 14 02:33:33 PM PST 24
Finished Jan 14 02:33:57 PM PST 24
Peak memory 202164 kb
Host smart-e69c9872-0e0c-48cc-a020-ffee7fe7bf90
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352206748 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
sram_ctrl_partial_access.3352206748
Directory /workspace/48.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.1139394851
Short name T433
Test name
Test status
Simulation time 21716868890 ps
CPU time 371.06 seconds
Started Jan 14 02:33:33 PM PST 24
Finished Jan 14 02:39:46 PM PST 24
Peak memory 202168 kb
Host smart-a74b9c09-7144-43c3-896e-c80945c149e3
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139394851 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 48.sram_ctrl_partial_access_b2b.1139394851
Directory /workspace/48.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/48.sram_ctrl_ram_cfg.1442123500
Short name T504
Test name
Test status
Simulation time 360407601 ps
CPU time 6.49 seconds
Started Jan 14 02:33:47 PM PST 24
Finished Jan 14 02:33:55 PM PST 24
Peak memory 202316 kb
Host smart-4715c905-ad5b-4df2-be4c-ec15f8fbbd30
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442123500 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.1442123500
Directory /workspace/48.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/48.sram_ctrl_regwen.1091047074
Short name T757
Test name
Test status
Simulation time 7821830756 ps
CPU time 971.98 seconds
Started Jan 14 02:33:42 PM PST 24
Finished Jan 14 02:49:55 PM PST 24
Peak memory 377080 kb
Host smart-4a632260-7771-4136-b120-b4f4ec37bb2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091047074 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.1091047074
Directory /workspace/48.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/48.sram_ctrl_smoke.1064280331
Short name T953
Test name
Test status
Simulation time 1989751140 ps
CPU time 25.21 seconds
Started Jan 14 02:33:33 PM PST 24
Finished Jan 14 02:33:59 PM PST 24
Peak memory 202084 kb
Host smart-91a9248e-9781-4e3d-b4bc-a0110dcb8283
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064280331 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.1064280331
Directory /workspace/48.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/48.sram_ctrl_stress_all.2303582753
Short name T564
Test name
Test status
Simulation time 488734037373 ps
CPU time 4835.74 seconds
Started Jan 14 02:33:51 PM PST 24
Finished Jan 14 03:54:28 PM PST 24
Peak memory 350796 kb
Host smart-ee01f3d0-48b4-49b6-8a31-d6d082e5d7c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303582753 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 48.sram_ctrl_stress_all.2303582753
Directory /workspace/48.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.3788420113
Short name T631
Test name
Test status
Simulation time 517021443 ps
CPU time 1477.42 seconds
Started Jan 14 02:33:48 PM PST 24
Finished Jan 14 02:58:26 PM PST 24
Peak memory 389668 kb
Host smart-9953e814-e96b-4ab9-8290-51c60a189729
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3788420113 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all_with_rand_reset.3788420113
Directory /workspace/48.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.sram_ctrl_stress_pipeline.3672176220
Short name T655
Test name
Test status
Simulation time 4786908052 ps
CPU time 361.39 seconds
Started Jan 14 02:33:33 PM PST 24
Finished Jan 14 02:39:36 PM PST 24
Peak memory 202192 kb
Host smart-fd07950d-dd80-4453-84eb-5b8a8ae28fee
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672176220 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.sram_ctrl_stress_pipeline.3672176220
Directory /workspace/48.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.3134986668
Short name T310
Test name
Test status
Simulation time 745578718 ps
CPU time 51.08 seconds
Started Jan 14 02:33:42 PM PST 24
Finished Jan 14 02:34:33 PM PST 24
Peak memory 278796 kb
Host smart-4abef24a-c617-417c-b821-96c9b9f0da82
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134986668 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 48.sram_ctrl_throughput_w_partial_write.3134986668
Directory /workspace/48.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/49.sram_ctrl_access_during_key_req.861584554
Short name T79
Test name
Test status
Simulation time 15274271251 ps
CPU time 487.2 seconds
Started Jan 14 02:33:56 PM PST 24
Finished Jan 14 02:42:05 PM PST 24
Peak memory 364776 kb
Host smart-9c8f8a87-b4f1-4b84-a0cf-37dde760e90d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861584554 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 49.sram_ctrl_access_during_key_req.861584554
Directory /workspace/49.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/49.sram_ctrl_alert_test.341917970
Short name T847
Test name
Test status
Simulation time 30898962 ps
CPU time 0.59 seconds
Started Jan 14 02:34:14 PM PST 24
Finished Jan 14 02:34:17 PM PST 24
Peak memory 201816 kb
Host smart-d59dda66-3118-4dc5-869d-510428bdacf0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341917970 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.sram_ctrl_alert_test.341917970
Directory /workspace/49.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.sram_ctrl_bijection.3507143604
Short name T134
Test name
Test status
Simulation time 16741834380 ps
CPU time 568.72 seconds
Started Jan 14 02:33:57 PM PST 24
Finished Jan 14 02:43:27 PM PST 24
Peak memory 202088 kb
Host smart-c9bad50f-7d1d-4d5e-81d0-9e54ae17c0ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507143604 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection
.3507143604
Directory /workspace/49.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/49.sram_ctrl_lc_escalation.2782614314
Short name T484
Test name
Test status
Simulation time 22997415139 ps
CPU time 117.11 seconds
Started Jan 14 02:33:59 PM PST 24
Finished Jan 14 02:35:57 PM PST 24
Peak memory 210392 kb
Host smart-5ccacc3a-614c-477c-b2a2-ad8277d9d3ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782614314 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_es
calation.2782614314
Directory /workspace/49.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/49.sram_ctrl_max_throughput.176218391
Short name T650
Test name
Test status
Simulation time 960482968 ps
CPU time 38.07 seconds
Started Jan 14 02:33:55 PM PST 24
Finished Jan 14 02:34:34 PM PST 24
Peak memory 255956 kb
Host smart-772c388a-6fd4-4b27-a6df-baad005a6c42
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176218391 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.sram_ctrl_max_throughput.176218391
Directory /workspace/49.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/49.sram_ctrl_mem_partial_access.1941044632
Short name T738
Test name
Test status
Simulation time 16281636691 ps
CPU time 143.92 seconds
Started Jan 14 02:34:13 PM PST 24
Finished Jan 14 02:36:39 PM PST 24
Peak memory 211156 kb
Host smart-be944f82-6ae8-42af-8650-22b901acf7b0
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941044632 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.sram_ctrl_mem_partial_access.1941044632
Directory /workspace/49.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/49.sram_ctrl_mem_walk.2723611674
Short name T369
Test name
Test status
Simulation time 8227817781 ps
CPU time 134.86 seconds
Started Jan 14 02:34:14 PM PST 24
Finished Jan 14 02:36:31 PM PST 24
Peak memory 202212 kb
Host smart-941350a5-8200-4af1-a48c-150a64595c3f
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723611674 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctr
l_mem_walk.2723611674
Directory /workspace/49.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/49.sram_ctrl_multiple_keys.733896062
Short name T971
Test name
Test status
Simulation time 10050826742 ps
CPU time 916.78 seconds
Started Jan 14 02:33:56 PM PST 24
Finished Jan 14 02:49:14 PM PST 24
Peak memory 379196 kb
Host smart-f9da9d45-646d-44d1-8df4-db2075f91687
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733896062 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multip
le_keys.733896062
Directory /workspace/49.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.3555932304
Short name T539
Test name
Test status
Simulation time 14313331959 ps
CPU time 353.54 seconds
Started Jan 14 02:33:59 PM PST 24
Finished Jan 14 02:39:53 PM PST 24
Peak memory 202092 kb
Host smart-dfff3d8b-fe34-45fe-aca6-55d02cf3db97
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555932304 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 49.sram_ctrl_partial_access_b2b.3555932304
Directory /workspace/49.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/49.sram_ctrl_ram_cfg.4260865991
Short name T401
Test name
Test status
Simulation time 1414448689 ps
CPU time 14.51 seconds
Started Jan 14 02:34:07 PM PST 24
Finished Jan 14 02:34:23 PM PST 24
Peak memory 202476 kb
Host smart-0d7d6e30-f5a2-4188-87f6-1f8640cd1801
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260865991 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.4260865991
Directory /workspace/49.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/49.sram_ctrl_regwen.393345629
Short name T731
Test name
Test status
Simulation time 10027188928 ps
CPU time 832.35 seconds
Started Jan 14 02:34:08 PM PST 24
Finished Jan 14 02:48:01 PM PST 24
Peak memory 379080 kb
Host smart-47ccf843-0799-4942-89ca-3485d78ad91e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393345629 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.393345629
Directory /workspace/49.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/49.sram_ctrl_smoke.1773531514
Short name T687
Test name
Test status
Simulation time 4326209543 ps
CPU time 18.1 seconds
Started Jan 14 02:33:49 PM PST 24
Finished Jan 14 02:34:08 PM PST 24
Peak memory 202012 kb
Host smart-9e318d71-e535-4ca2-bba0-64eff9ce297d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773531514 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.1773531514
Directory /workspace/49.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.3573075270
Short name T480
Test name
Test status
Simulation time 1197337228 ps
CPU time 4105.4 seconds
Started Jan 14 02:34:14 PM PST 24
Finished Jan 14 03:42:42 PM PST 24
Peak memory 535724 kb
Host smart-c93223bd-99b1-4008-8585-855dece7faa6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3573075270 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all_with_rand_reset.3573075270
Directory /workspace/49.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.sram_ctrl_stress_pipeline.4033978004
Short name T579
Test name
Test status
Simulation time 17602363403 ps
CPU time 302.17 seconds
Started Jan 14 02:33:50 PM PST 24
Finished Jan 14 02:38:53 PM PST 24
Peak memory 202152 kb
Host smart-83a10942-5400-4048-943c-2ebdf0ebde0e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033978004 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.sram_ctrl_stress_pipeline.4033978004
Directory /workspace/49.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.1419464741
Short name T293
Test name
Test status
Simulation time 4423025917 ps
CPU time 96.21 seconds
Started Jan 14 02:33:59 PM PST 24
Finished Jan 14 02:35:36 PM PST 24
Peak memory 330916 kb
Host smart-996f9c6f-5c8a-4206-914c-0b8f95cac7dd
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419464741 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.sram_ctrl_throughput_w_partial_write.1419464741
Directory /workspace/49.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/5.sram_ctrl_access_during_key_req.1490868383
Short name T469
Test name
Test status
Simulation time 7942767593 ps
CPU time 255.3 seconds
Started Jan 14 02:14:55 PM PST 24
Finished Jan 14 02:19:11 PM PST 24
Peak memory 295720 kb
Host smart-f6a65f9d-1217-416c-9a70-066c2eedd591
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490868383 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.sram_ctrl_access_during_key_req.1490868383
Directory /workspace/5.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/5.sram_ctrl_alert_test.2558579483
Short name T794
Test name
Test status
Simulation time 14924492 ps
CPU time 0.67 seconds
Started Jan 14 02:15:10 PM PST 24
Finished Jan 14 02:15:11 PM PST 24
Peak memory 201428 kb
Host smart-39e3e95d-30bf-4ab3-bcc7-9dd223b49f53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558579483 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.sram_ctrl_alert_test.2558579483
Directory /workspace/5.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.sram_ctrl_bijection.84417534
Short name T247
Test name
Test status
Simulation time 63470913477 ps
CPU time 664.26 seconds
Started Jan 14 02:14:34 PM PST 24
Finished Jan 14 02:25:44 PM PST 24
Peak memory 202172 kb
Host smart-739ba11c-b6f5-43c6-966f-751abb1316fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84417534 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_biject
ion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection.84417534
Directory /workspace/5.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/5.sram_ctrl_executable.3696582309
Short name T284
Test name
Test status
Simulation time 11942240427 ps
CPU time 182.3 seconds
Started Jan 14 02:14:57 PM PST 24
Finished Jan 14 02:18:00 PM PST 24
Peak memory 272928 kb
Host smart-910d2cf7-5f93-4e56-bdd7-8b99e481d16d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696582309 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_executabl
e.3696582309
Directory /workspace/5.sram_ctrl_executable/latest

Test location /workspace/coverage/default/5.sram_ctrl_max_throughput.2920036066
Short name T662
Test name
Test status
Simulation time 737599921 ps
CPU time 59.33 seconds
Started Jan 14 02:14:38 PM PST 24
Finished Jan 14 02:15:39 PM PST 24
Peak memory 287988 kb
Host smart-386b4bf9-c867-456b-83f4-dd6132eac3f0
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920036066 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 5.sram_ctrl_max_throughput.2920036066
Directory /workspace/5.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/5.sram_ctrl_mem_partial_access.1950189158
Short name T755
Test name
Test status
Simulation time 2411360548 ps
CPU time 78.36 seconds
Started Jan 14 02:15:01 PM PST 24
Finished Jan 14 02:16:20 PM PST 24
Peak memory 218472 kb
Host smart-78655780-edbd-446f-9b7d-066fcc7d90e8
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950189158 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.sram_ctrl_mem_partial_access.1950189158
Directory /workspace/5.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/5.sram_ctrl_mem_walk.3420299135
Short name T339
Test name
Test status
Simulation time 85988961028 ps
CPU time 362.2 seconds
Started Jan 14 02:15:05 PM PST 24
Finished Jan 14 02:21:08 PM PST 24
Peak memory 202276 kb
Host smart-2b8732df-f952-4e39-b81a-5f8b796cc6c7
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420299135 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl
_mem_walk.3420299135
Directory /workspace/5.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/5.sram_ctrl_multiple_keys.3968506516
Short name T935
Test name
Test status
Simulation time 36461914519 ps
CPU time 1032.69 seconds
Started Jan 14 02:14:29 PM PST 24
Finished Jan 14 02:31:46 PM PST 24
Peak memory 378048 kb
Host smart-fe185e3a-eefa-4cbd-bbe4-d3779034171d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968506516 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multip
le_keys.3968506516
Directory /workspace/5.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/5.sram_ctrl_partial_access.3647838135
Short name T261
Test name
Test status
Simulation time 390795909 ps
CPU time 7.23 seconds
Started Jan 14 02:14:37 PM PST 24
Finished Jan 14 02:14:47 PM PST 24
Peak memory 202204 kb
Host smart-3f13f0d9-03b3-47f4-88f3-92702ecb15ca
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647838135 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.s
ram_ctrl_partial_access.3647838135
Directory /workspace/5.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.882659660
Short name T807
Test name
Test status
Simulation time 77787766205 ps
CPU time 446.02 seconds
Started Jan 14 02:14:37 PM PST 24
Finished Jan 14 02:22:05 PM PST 24
Peak memory 202152 kb
Host smart-7d280226-6db7-4cfd-a1fe-e94542329b5c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882659660 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.sram_ctrl_partial_access_b2b.882659660
Directory /workspace/5.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/5.sram_ctrl_ram_cfg.4155242952
Short name T365
Test name
Test status
Simulation time 3369068984 ps
CPU time 14.54 seconds
Started Jan 14 02:14:55 PM PST 24
Finished Jan 14 02:15:10 PM PST 24
Peak memory 202484 kb
Host smart-37950fb6-8aae-450e-a56b-09ef24968ad3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155242952 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.4155242952
Directory /workspace/5.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/5.sram_ctrl_regwen.3084280093
Short name T962
Test name
Test status
Simulation time 3192879959 ps
CPU time 1075.88 seconds
Started Jan 14 02:14:56 PM PST 24
Finished Jan 14 02:32:53 PM PST 24
Peak memory 378060 kb
Host smart-9d8a3d59-ef43-42af-97ae-db480147128c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084280093 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.3084280093
Directory /workspace/5.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/5.sram_ctrl_smoke.3013489854
Short name T44
Test name
Test status
Simulation time 1357511813 ps
CPU time 7.1 seconds
Started Jan 14 02:14:33 PM PST 24
Finished Jan 14 02:14:46 PM PST 24
Peak memory 202076 kb
Host smart-afcbe02d-21ca-46cc-bc10-5428e703ff34
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013489854 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.3013489854
Directory /workspace/5.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/5.sram_ctrl_stress_all.3845850762
Short name T702
Test name
Test status
Simulation time 204707022085 ps
CPU time 3578.83 seconds
Started Jan 14 02:15:05 PM PST 24
Finished Jan 14 03:14:45 PM PST 24
Peak memory 380116 kb
Host smart-95838b73-b5d8-4446-aa08-57d82c25780c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845850762 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 5.sram_ctrl_stress_all.3845850762
Directory /workspace/5.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.2815110372
Short name T774
Test name
Test status
Simulation time 1890106369 ps
CPU time 4631.46 seconds
Started Jan 14 02:15:07 PM PST 24
Finished Jan 14 03:32:20 PM PST 24
Peak memory 674488 kb
Host smart-a9b73d45-2e09-4a21-b24f-7ebaafa9d1a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2815110372 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all_with_rand_reset.2815110372
Directory /workspace/5.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.sram_ctrl_stress_pipeline.90645354
Short name T959
Test name
Test status
Simulation time 2119109027 ps
CPU time 182.19 seconds
Started Jan 14 02:14:37 PM PST 24
Finished Jan 14 02:17:42 PM PST 24
Peak memory 202112 kb
Host smart-e6ca5ebe-7fd8-47ca-8e33-63abd0ad72bd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90645354 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.s
ram_ctrl_stress_pipeline.90645354
Directory /workspace/5.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.3923129835
Short name T595
Test name
Test status
Simulation time 2792625476 ps
CPU time 34.8 seconds
Started Jan 14 02:14:56 PM PST 24
Finished Jan 14 02:15:32 PM PST 24
Peak memory 241152 kb
Host smart-5a736092-32be-42c3-807e-78780140b084
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923129835 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.sram_ctrl_throughput_w_partial_write.3923129835
Directory /workspace/5.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/6.sram_ctrl_access_during_key_req.4149597946
Short name T367
Test name
Test status
Simulation time 7777311162 ps
CPU time 90.45 seconds
Started Jan 14 02:15:22 PM PST 24
Finished Jan 14 02:16:53 PM PST 24
Peak memory 206944 kb
Host smart-5542a85d-c0ad-4fb5-8e91-10d8a0eae9d9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149597946 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.sram_ctrl_access_during_key_req.4149597946
Directory /workspace/6.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/6.sram_ctrl_alert_test.3423001040
Short name T445
Test name
Test status
Simulation time 36362427 ps
CPU time 0.66 seconds
Started Jan 14 02:15:44 PM PST 24
Finished Jan 14 02:15:46 PM PST 24
Peak memory 201844 kb
Host smart-ab96bd98-28d0-418b-98d4-438a55b6df94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423001040 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.sram_ctrl_alert_test.3423001040
Directory /workspace/6.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.sram_ctrl_bijection.2885835527
Short name T832
Test name
Test status
Simulation time 48534623450 ps
CPU time 918.82 seconds
Started Jan 14 02:15:14 PM PST 24
Finished Jan 14 02:30:34 PM PST 24
Peak memory 202172 kb
Host smart-bd590dd7-1073-4479-bf13-f1664a9840a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885835527 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection.
2885835527
Directory /workspace/6.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/6.sram_ctrl_lc_escalation.1606132382
Short name T754
Test name
Test status
Simulation time 8800062600 ps
CPU time 82.75 seconds
Started Jan 14 02:15:23 PM PST 24
Finished Jan 14 02:16:47 PM PST 24
Peak memory 210372 kb
Host smart-894d379e-83ff-4183-b43e-708e7c566713
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606132382 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_lc_esc
alation.1606132382
Directory /workspace/6.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/6.sram_ctrl_max_throughput.165505246
Short name T928
Test name
Test status
Simulation time 2739755268 ps
CPU time 34.78 seconds
Started Jan 14 02:15:20 PM PST 24
Finished Jan 14 02:15:55 PM PST 24
Peak memory 234972 kb
Host smart-a53b0c4d-7748-4b28-9346-67b27c0838cf
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165505246 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.sram_ctrl_max_throughput.165505246
Directory /workspace/6.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/6.sram_ctrl_mem_partial_access.437055613
Short name T590
Test name
Test status
Simulation time 2070764092 ps
CPU time 80.4 seconds
Started Jan 14 02:15:31 PM PST 24
Finished Jan 14 02:16:52 PM PST 24
Peak memory 210948 kb
Host smart-ebc5889d-34b9-40c3-8fdd-928e542de3d8
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437055613 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
sram_ctrl_mem_partial_access.437055613
Directory /workspace/6.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/6.sram_ctrl_mem_walk.497966319
Short name T225
Test name
Test status
Simulation time 35797688472 ps
CPU time 326.18 seconds
Started Jan 14 02:15:23 PM PST 24
Finished Jan 14 02:20:50 PM PST 24
Peak memory 202580 kb
Host smart-250caa8c-6463-4abb-bef8-2cc4969b17de
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497966319 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_
mem_walk.497966319
Directory /workspace/6.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/6.sram_ctrl_multiple_keys.476793060
Short name T477
Test name
Test status
Simulation time 32898824602 ps
CPU time 2132.58 seconds
Started Jan 14 02:15:16 PM PST 24
Finished Jan 14 02:50:50 PM PST 24
Peak memory 379144 kb
Host smart-5f3f87e7-6adc-45dc-85ef-dda202a806d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476793060 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multipl
e_keys.476793060
Directory /workspace/6.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/6.sram_ctrl_partial_access.1798887568
Short name T679
Test name
Test status
Simulation time 3368600287 ps
CPU time 100.97 seconds
Started Jan 14 02:15:22 PM PST 24
Finished Jan 14 02:17:04 PM PST 24
Peak memory 328932 kb
Host smart-f65ffa28-1c59-4f46-9909-1b8fa863d54b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798887568 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.s
ram_ctrl_partial_access.1798887568
Directory /workspace/6.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.4093581103
Short name T465
Test name
Test status
Simulation time 28205297489 ps
CPU time 433.26 seconds
Started Jan 14 02:15:17 PM PST 24
Finished Jan 14 02:22:31 PM PST 24
Peak memory 202144 kb
Host smart-edb3f393-37c8-47ff-8f35-294442dded87
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093581103 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 6.sram_ctrl_partial_access_b2b.4093581103
Directory /workspace/6.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/6.sram_ctrl_ram_cfg.859683025
Short name T709
Test name
Test status
Simulation time 1349566133 ps
CPU time 5.71 seconds
Started Jan 14 02:15:28 PM PST 24
Finished Jan 14 02:15:35 PM PST 24
Peak memory 202464 kb
Host smart-46420d75-0502-420d-b4d5-30dd46e42f85
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859683025 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.859683025
Directory /workspace/6.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/6.sram_ctrl_regwen.3675508093
Short name T29
Test name
Test status
Simulation time 122707475475 ps
CPU time 917.56 seconds
Started Jan 14 02:15:24 PM PST 24
Finished Jan 14 02:30:43 PM PST 24
Peak memory 345356 kb
Host smart-c94bfaf3-fe41-4793-bfe0-c123c2d3ac10
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675508093 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.3675508093
Directory /workspace/6.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/6.sram_ctrl_smoke.281653079
Short name T725
Test name
Test status
Simulation time 823126533 ps
CPU time 13.94 seconds
Started Jan 14 02:15:05 PM PST 24
Finished Jan 14 02:15:20 PM PST 24
Peak memory 210320 kb
Host smart-2cbbd841-643f-4390-88d9-a23cb2942233
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281653079 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.281653079
Directory /workspace/6.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/6.sram_ctrl_stress_all.2541285109
Short name T737
Test name
Test status
Simulation time 23705450798 ps
CPU time 2145.12 seconds
Started Jan 14 02:15:57 PM PST 24
Finished Jan 14 02:51:43 PM PST 24
Peak memory 382124 kb
Host smart-ea5737a4-0651-4df8-ac3a-1f27f76be39e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541285109 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 6.sram_ctrl_stress_all.2541285109
Directory /workspace/6.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.1817300174
Short name T496
Test name
Test status
Simulation time 733095532 ps
CPU time 6264 seconds
Started Jan 14 02:15:31 PM PST 24
Finished Jan 14 03:59:57 PM PST 24
Peak memory 468920 kb
Host smart-6fe6f436-d93f-4499-a5c1-944a84f53193
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1817300174 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all_with_rand_reset.1817300174
Directory /workspace/6.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.sram_ctrl_stress_pipeline.909506021
Short name T587
Test name
Test status
Simulation time 3889275358 ps
CPU time 260.94 seconds
Started Jan 14 02:15:19 PM PST 24
Finished Jan 14 02:19:40 PM PST 24
Peak memory 202128 kb
Host smart-809e8fec-8213-4ae5-b2ac-165b77a3ce76
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909506021 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
sram_ctrl_stress_pipeline.909506021
Directory /workspace/6.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.3464220974
Short name T678
Test name
Test status
Simulation time 3261909824 ps
CPU time 176.84 seconds
Started Jan 14 02:15:16 PM PST 24
Finished Jan 14 02:18:13 PM PST 24
Peak memory 364796 kb
Host smart-6865ab6b-b3c7-4787-99d3-383220d4ea71
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464220974 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.sram_ctrl_throughput_w_partial_write.3464220974
Directory /workspace/6.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/7.sram_ctrl_access_during_key_req.3856665753
Short name T43
Test name
Test status
Simulation time 3170260889 ps
CPU time 526.53 seconds
Started Jan 14 02:16:02 PM PST 24
Finished Jan 14 02:24:49 PM PST 24
Peak memory 354584 kb
Host smart-6a6ab796-ba80-4dbb-b2c0-8db8a699a9ac
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856665753 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.sram_ctrl_access_during_key_req.3856665753
Directory /workspace/7.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/7.sram_ctrl_alert_test.3103211606
Short name T763
Test name
Test status
Simulation time 15925001 ps
CPU time 0.65 seconds
Started Jan 14 02:16:13 PM PST 24
Finished Jan 14 02:16:15 PM PST 24
Peak memory 201372 kb
Host smart-9f1e67b5-9874-4cf3-bb91-94785eac0ced
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103211606 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.sram_ctrl_alert_test.3103211606
Directory /workspace/7.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.sram_ctrl_bijection.289617284
Short name T219
Test name
Test status
Simulation time 165509282849 ps
CPU time 2806.33 seconds
Started Jan 14 02:15:52 PM PST 24
Finished Jan 14 03:02:39 PM PST 24
Peak memory 202148 kb
Host smart-7723c40b-a4ad-40e3-b715-d99cc179eabd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289617284 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection.289617284
Directory /workspace/7.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/7.sram_ctrl_executable.2999155112
Short name T321
Test name
Test status
Simulation time 61688685449 ps
CPU time 1691.45 seconds
Started Jan 14 02:16:11 PM PST 24
Finished Jan 14 02:44:23 PM PST 24
Peak memory 380088 kb
Host smart-6730037f-e874-41bf-8eab-194215e98a45
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999155112 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_executabl
e.2999155112
Directory /workspace/7.sram_ctrl_executable/latest

Test location /workspace/coverage/default/7.sram_ctrl_lc_escalation.1710339370
Short name T973
Test name
Test status
Simulation time 31880799784 ps
CPU time 111.08 seconds
Started Jan 14 02:16:01 PM PST 24
Finished Jan 14 02:17:53 PM PST 24
Peak memory 210408 kb
Host smart-1977b8d7-1b9c-484b-a0ef-b1f0ddae3ab1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710339370 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_lc_esc
alation.1710339370
Directory /workspace/7.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/7.sram_ctrl_max_throughput.152535662
Short name T260
Test name
Test status
Simulation time 969543832 ps
CPU time 72.23 seconds
Started Jan 14 02:16:02 PM PST 24
Finished Jan 14 02:17:16 PM PST 24
Peak memory 302328 kb
Host smart-f67e8b51-b6e3-453a-bdc3-a2722979504a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152535662 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.sram_ctrl_max_throughput.152535662
Directory /workspace/7.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/7.sram_ctrl_mem_partial_access.2925038900
Short name T393
Test name
Test status
Simulation time 2461047865 ps
CPU time 80.86 seconds
Started Jan 14 02:16:14 PM PST 24
Finished Jan 14 02:17:35 PM PST 24
Peak memory 210496 kb
Host smart-b7b07e91-a492-42d0-bc70-2bfb7b4138da
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925038900 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.sram_ctrl_mem_partial_access.2925038900
Directory /workspace/7.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/7.sram_ctrl_mem_walk.147550630
Short name T100
Test name
Test status
Simulation time 21496439363 ps
CPU time 169.9 seconds
Started Jan 14 02:16:12 PM PST 24
Finished Jan 14 02:19:03 PM PST 24
Peak memory 202168 kb
Host smart-92157ea7-df51-49e0-870a-5d12f5ca1d4b
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147550630 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_
mem_walk.147550630
Directory /workspace/7.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/7.sram_ctrl_multiple_keys.2716166764
Short name T258
Test name
Test status
Simulation time 46410399338 ps
CPU time 504.11 seconds
Started Jan 14 02:15:51 PM PST 24
Finished Jan 14 02:24:16 PM PST 24
Peak memory 378076 kb
Host smart-6097c81c-0e7e-4a6d-890d-f0c1dc52e075
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716166764 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multip
le_keys.2716166764
Directory /workspace/7.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/7.sram_ctrl_partial_access.2062625568
Short name T975
Test name
Test status
Simulation time 2495244333 ps
CPU time 31.88 seconds
Started Jan 14 02:15:57 PM PST 24
Finished Jan 14 02:16:30 PM PST 24
Peak memory 257212 kb
Host smart-fe6c9266-b816-4f38-b873-58863d8d5a21
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062625568 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.s
ram_ctrl_partial_access.2062625568
Directory /workspace/7.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.2838364700
Short name T689
Test name
Test status
Simulation time 11371133770 ps
CPU time 355.63 seconds
Started Jan 14 02:16:01 PM PST 24
Finished Jan 14 02:21:58 PM PST 24
Peak memory 202152 kb
Host smart-323ec48d-a493-41c0-99a7-e1919edef9f0
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838364700 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 7.sram_ctrl_partial_access_b2b.2838364700
Directory /workspace/7.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/7.sram_ctrl_ram_cfg.450710
Short name T471
Test name
Test status
Simulation time 1979454072 ps
CPU time 13.55 seconds
Started Jan 14 02:16:13 PM PST 24
Finished Jan 14 02:16:27 PM PST 24
Peak memory 202428 kb
Host smart-3b0f2805-94dc-4776-b5f3-b030c1c941bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450710 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.450710
Directory /workspace/7.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/7.sram_ctrl_regwen.2097545061
Short name T745
Test name
Test status
Simulation time 34755901560 ps
CPU time 1014.7 seconds
Started Jan 14 02:16:12 PM PST 24
Finished Jan 14 02:33:08 PM PST 24
Peak memory 376368 kb
Host smart-1df12a9c-0879-43b6-81c5-ca02ba132ae8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097545061 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.2097545061
Directory /workspace/7.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/7.sram_ctrl_smoke.3034024976
Short name T922
Test name
Test status
Simulation time 445921864 ps
CPU time 65.52 seconds
Started Jan 14 02:15:52 PM PST 24
Finished Jan 14 02:16:58 PM PST 24
Peak memory 314600 kb
Host smart-cf595f0a-0acb-4d1f-95be-e5b12a92f2ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034024976 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.3034024976
Directory /workspace/7.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.867717932
Short name T572
Test name
Test status
Simulation time 2355876062 ps
CPU time 4396.06 seconds
Started Jan 14 02:16:13 PM PST 24
Finished Jan 14 03:29:31 PM PST 24
Peak memory 696684 kb
Host smart-55be3163-d41f-4ed2-80c5-8881ec7adc68
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=867717932 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all_with_rand_reset.867717932
Directory /workspace/7.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.sram_ctrl_stress_pipeline.3677990895
Short name T605
Test name
Test status
Simulation time 3518574908 ps
CPU time 273.55 seconds
Started Jan 14 02:15:56 PM PST 24
Finished Jan 14 02:20:30 PM PST 24
Peak memory 202144 kb
Host smart-ea7d2752-7492-48c2-9bd9-2ddae1dcbc35
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677990895 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.sram_ctrl_stress_pipeline.3677990895
Directory /workspace/7.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.1391904445
Short name T409
Test name
Test status
Simulation time 790951629 ps
CPU time 195.59 seconds
Started Jan 14 02:16:04 PM PST 24
Finished Jan 14 02:19:21 PM PST 24
Peak memory 369876 kb
Host smart-33e577a5-10b9-4bb8-9536-3ef3cf42ea06
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391904445 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.sram_ctrl_throughput_w_partial_write.1391904445
Directory /workspace/7.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/8.sram_ctrl_access_during_key_req.2533223973
Short name T301
Test name
Test status
Simulation time 11798293291 ps
CPU time 1456.61 seconds
Started Jan 14 02:16:38 PM PST 24
Finished Jan 14 02:40:57 PM PST 24
Peak memory 360704 kb
Host smart-bb7250ed-9d1a-455b-b82b-9808e34340c1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533223973 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.sram_ctrl_access_during_key_req.2533223973
Directory /workspace/8.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/8.sram_ctrl_alert_test.3065071507
Short name T255
Test name
Test status
Simulation time 58199672 ps
CPU time 0.66 seconds
Started Jan 14 02:16:40 PM PST 24
Finished Jan 14 02:16:45 PM PST 24
Peak memory 201912 kb
Host smart-50444425-b1e7-45ac-9a2d-430c535cc4e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065071507 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.sram_ctrl_alert_test.3065071507
Directory /workspace/8.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.sram_ctrl_executable.369749155
Short name T126
Test name
Test status
Simulation time 59476445714 ps
CPU time 695.97 seconds
Started Jan 14 02:16:41 PM PST 24
Finished Jan 14 02:28:21 PM PST 24
Peak memory 369868 kb
Host smart-342e0cb1-6cf6-44ef-9248-3494c402bab5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369749155 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_executable
.369749155
Directory /workspace/8.sram_ctrl_executable/latest

Test location /workspace/coverage/default/8.sram_ctrl_lc_escalation.1124618521
Short name T672
Test name
Test status
Simulation time 31813088902 ps
CPU time 139.7 seconds
Started Jan 14 02:16:31 PM PST 24
Finished Jan 14 02:18:53 PM PST 24
Peak memory 210396 kb
Host smart-cbcf6aae-ca94-4165-aa5f-5d292acb8303
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124618521 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_esc
alation.1124618521
Directory /workspace/8.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/8.sram_ctrl_max_throughput.2789498180
Short name T723
Test name
Test status
Simulation time 3937565441 ps
CPU time 127.79 seconds
Started Jan 14 02:16:32 PM PST 24
Finished Jan 14 02:18:41 PM PST 24
Peak memory 350524 kb
Host smart-7dc5b4a9-4e7e-4f32-b9d5-3b50a620076c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789498180 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 8.sram_ctrl_max_throughput.2789498180
Directory /workspace/8.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/8.sram_ctrl_mem_partial_access.1263927971
Short name T403
Test name
Test status
Simulation time 43779562950 ps
CPU time 172.85 seconds
Started Jan 14 02:16:34 PM PST 24
Finished Jan 14 02:19:33 PM PST 24
Peak memory 214704 kb
Host smart-64b9da97-8fa5-4560-bb81-76d77cc7d6ab
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263927971 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.sram_ctrl_mem_partial_access.1263927971
Directory /workspace/8.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/8.sram_ctrl_mem_walk.2389925069
Short name T961
Test name
Test status
Simulation time 127770268747 ps
CPU time 186.99 seconds
Started Jan 14 02:16:38 PM PST 24
Finished Jan 14 02:19:47 PM PST 24
Peak memory 202092 kb
Host smart-e12dddcf-90ef-4f8c-9485-dba59af40793
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389925069 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl
_mem_walk.2389925069
Directory /workspace/8.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/8.sram_ctrl_multiple_keys.3998034928
Short name T478
Test name
Test status
Simulation time 20572303159 ps
CPU time 1864.8 seconds
Started Jan 14 02:16:13 PM PST 24
Finished Jan 14 02:47:19 PM PST 24
Peak memory 378036 kb
Host smart-18f5bf09-c1ea-463c-8998-c91e07cfae14
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998034928 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multip
le_keys.3998034928
Directory /workspace/8.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/8.sram_ctrl_partial_access.2028198178
Short name T326
Test name
Test status
Simulation time 5015881935 ps
CPU time 47.46 seconds
Started Jan 14 02:16:37 PM PST 24
Finished Jan 14 02:17:28 PM PST 24
Peak memory 309308 kb
Host smart-ea847f4e-ba7e-44f8-9ff1-71b5a0f13121
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028198178 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.s
ram_ctrl_partial_access.2028198178
Directory /workspace/8.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.2148383801
Short name T306
Test name
Test status
Simulation time 27614596989 ps
CPU time 472.27 seconds
Started Jan 14 02:16:39 PM PST 24
Finished Jan 14 02:24:34 PM PST 24
Peak memory 202080 kb
Host smart-5a5b8498-2cfc-4379-8664-63c0eeb9dc0f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148383801 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 8.sram_ctrl_partial_access_b2b.2148383801
Directory /workspace/8.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/8.sram_ctrl_ram_cfg.871880664
Short name T249
Test name
Test status
Simulation time 417791856 ps
CPU time 5.46 seconds
Started Jan 14 02:16:31 PM PST 24
Finished Jan 14 02:16:39 PM PST 24
Peak memory 202340 kb
Host smart-8827842c-18de-4b3c-a647-41fe55920571
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871880664 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.871880664
Directory /workspace/8.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/8.sram_ctrl_regwen.2603275433
Short name T299
Test name
Test status
Simulation time 98623749133 ps
CPU time 1048.32 seconds
Started Jan 14 02:16:32 PM PST 24
Finished Jan 14 02:34:02 PM PST 24
Peak memory 380340 kb
Host smart-3e657050-a22c-48b4-97ba-1a6a0dc91a9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603275433 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.2603275433
Directory /workspace/8.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/8.sram_ctrl_smoke.2450029165
Short name T628
Test name
Test status
Simulation time 1232833471 ps
CPU time 104.89 seconds
Started Jan 14 02:16:13 PM PST 24
Finished Jan 14 02:17:59 PM PST 24
Peak memory 344200 kb
Host smart-b235123e-3f2d-4624-96ac-7f9070773bc6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450029165 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.2450029165
Directory /workspace/8.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.1243848644
Short name T357
Test name
Test status
Simulation time 3932911743 ps
CPU time 4682.9 seconds
Started Jan 14 02:16:39 PM PST 24
Finished Jan 14 03:34:45 PM PST 24
Peak memory 707240 kb
Host smart-edaa4fb4-b2d5-43a9-95e6-e0bc18bafb22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1243848644 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all_with_rand_reset.1243848644
Directory /workspace/8.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.sram_ctrl_stress_pipeline.2796659135
Short name T660
Test name
Test status
Simulation time 2863860461 ps
CPU time 232.89 seconds
Started Jan 14 02:16:26 PM PST 24
Finished Jan 14 02:20:19 PM PST 24
Peak memory 202168 kb
Host smart-3e3e9b0c-bcfa-4ab6-b868-c98086015081
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796659135 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.sram_ctrl_stress_pipeline.2796659135
Directory /workspace/8.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.1727456277
Short name T908
Test name
Test status
Simulation time 979506494 ps
CPU time 36.6 seconds
Started Jan 14 02:16:39 PM PST 24
Finished Jan 14 02:17:17 PM PST 24
Peak memory 238544 kb
Host smart-c9a57599-0e2e-4d43-8a48-ccd0ba9c93bc
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727456277 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.sram_ctrl_throughput_w_partial_write.1727456277
Directory /workspace/8.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/9.sram_ctrl_access_during_key_req.894905162
Short name T78
Test name
Test status
Simulation time 3500864521 ps
CPU time 200.14 seconds
Started Jan 14 02:16:49 PM PST 24
Finished Jan 14 02:20:10 PM PST 24
Peak memory 262180 kb
Host smart-d5bd36c1-b6b9-43f3-aa08-4642ebddc962
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894905162 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 9.sram_ctrl_access_during_key_req.894905162
Directory /workspace/9.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/9.sram_ctrl_alert_test.4014828123
Short name T954
Test name
Test status
Simulation time 49771960 ps
CPU time 0.64 seconds
Started Jan 14 02:17:04 PM PST 24
Finished Jan 14 02:17:06 PM PST 24
Peak memory 201468 kb
Host smart-7846bcc4-246e-4b69-9bdb-2f8f21087852
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014828123 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.sram_ctrl_alert_test.4014828123
Directory /workspace/9.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.sram_ctrl_bijection.4190056694
Short name T308
Test name
Test status
Simulation time 60650693538 ps
CPU time 1412.12 seconds
Started Jan 14 02:16:41 PM PST 24
Finished Jan 14 02:40:17 PM PST 24
Peak memory 202044 kb
Host smart-6c0b20bb-a9ae-4afa-9db3-c77ba63ab271
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190056694 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection.
4190056694
Directory /workspace/9.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/9.sram_ctrl_executable.1891488166
Short name T619
Test name
Test status
Simulation time 5214450631 ps
CPU time 591.13 seconds
Started Jan 14 02:17:06 PM PST 24
Finished Jan 14 02:27:02 PM PST 24
Peak memory 364740 kb
Host smart-9571914c-4052-4364-ae22-396936f24b69
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891488166 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_executabl
e.1891488166
Directory /workspace/9.sram_ctrl_executable/latest

Test location /workspace/coverage/default/9.sram_ctrl_max_throughput.2539247197
Short name T558
Test name
Test status
Simulation time 726554713 ps
CPU time 28.71 seconds
Started Jan 14 02:16:41 PM PST 24
Finished Jan 14 02:17:14 PM PST 24
Peak memory 210396 kb
Host smart-ffacb071-8c12-4674-9d33-226b6d6ad5ad
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539247197 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 9.sram_ctrl_max_throughput.2539247197
Directory /workspace/9.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/9.sram_ctrl_mem_partial_access.2400337442
Short name T876
Test name
Test status
Simulation time 9141048213 ps
CPU time 163 seconds
Started Jan 14 02:17:04 PM PST 24
Finished Jan 14 02:19:49 PM PST 24
Peak memory 218488 kb
Host smart-e64b327a-bac3-4845-8575-6ee82748314b
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400337442 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.sram_ctrl_mem_partial_access.2400337442
Directory /workspace/9.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/9.sram_ctrl_mem_walk.1863568939
Short name T963
Test name
Test status
Simulation time 1979168464 ps
CPU time 127.49 seconds
Started Jan 14 02:17:06 PM PST 24
Finished Jan 14 02:19:19 PM PST 24
Peak memory 202064 kb
Host smart-ddf31437-c6c4-499f-903c-f2d5e0da80d8
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863568939 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl
_mem_walk.1863568939
Directory /workspace/9.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/9.sram_ctrl_multiple_keys.2922585234
Short name T776
Test name
Test status
Simulation time 92695540065 ps
CPU time 1710.71 seconds
Started Jan 14 02:16:40 PM PST 24
Finished Jan 14 02:45:15 PM PST 24
Peak memory 379116 kb
Host smart-1f63c9a8-95fc-4adc-8ebe-35a8f8eb9316
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922585234 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multip
le_keys.2922585234
Directory /workspace/9.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/9.sram_ctrl_partial_access.1933678084
Short name T552
Test name
Test status
Simulation time 992564570 ps
CPU time 45.24 seconds
Started Jan 14 02:16:39 PM PST 24
Finished Jan 14 02:17:27 PM PST 24
Peak memory 202160 kb
Host smart-1fa848d6-8ccd-4eb8-be73-e4fdbea7cc60
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933678084 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.s
ram_ctrl_partial_access.1933678084
Directory /workspace/9.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.43021694
Short name T405
Test name
Test status
Simulation time 22156066143 ps
CPU time 371.37 seconds
Started Jan 14 02:16:41 PM PST 24
Finished Jan 14 02:22:57 PM PST 24
Peak memory 202252 kb
Host smart-b91fd9ef-743c-4cc2-bd2c-b8cd0601f1ec
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43021694 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.sram_ctrl_partial_access_b2b.43021694
Directory /workspace/9.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/9.sram_ctrl_ram_cfg.1287128638
Short name T730
Test name
Test status
Simulation time 354202897 ps
CPU time 6.27 seconds
Started Jan 14 02:17:00 PM PST 24
Finished Jan 14 02:17:08 PM PST 24
Peak memory 202340 kb
Host smart-a29d1edc-aef7-4de9-817f-7ca65234457d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287128638 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.1287128638
Directory /workspace/9.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/9.sram_ctrl_regwen.2070665340
Short name T949
Test name
Test status
Simulation time 22399257028 ps
CPU time 1206.24 seconds
Started Jan 14 02:17:06 PM PST 24
Finished Jan 14 02:37:18 PM PST 24
Peak memory 377024 kb
Host smart-979baf04-d449-4c19-93e4-33a80e824546
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070665340 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.2070665340
Directory /workspace/9.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/9.sram_ctrl_smoke.1048084258
Short name T606
Test name
Test status
Simulation time 4628107141 ps
CPU time 22.78 seconds
Started Jan 14 02:16:39 PM PST 24
Finished Jan 14 02:17:04 PM PST 24
Peak memory 202100 kb
Host smart-8cc04c95-4454-4f34-aec4-863a64e2ee7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048084258 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.1048084258
Directory /workspace/9.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.4119543601
Short name T442
Test name
Test status
Simulation time 2346639569 ps
CPU time 5986.85 seconds
Started Jan 14 02:17:07 PM PST 24
Finished Jan 14 03:57:00 PM PST 24
Peak memory 610996 kb
Host smart-2ad04c22-ed89-4a0c-a9ea-ae90e110695c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4119543601 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all_with_rand_reset.4119543601
Directory /workspace/9.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.sram_ctrl_stress_pipeline.1753464877
Short name T441
Test name
Test status
Simulation time 13220381704 ps
CPU time 323.36 seconds
Started Jan 14 02:16:41 PM PST 24
Finished Jan 14 02:22:09 PM PST 24
Peak memory 202168 kb
Host smart-3123505c-d39c-4ad1-9f3e-09f9f2eba9d9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753464877 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.sram_ctrl_stress_pipeline.1753464877
Directory /workspace/9.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3646182846
Short name T479
Test name
Test status
Simulation time 2809028822 ps
CPU time 40.05 seconds
Started Jan 14 02:16:41 PM PST 24
Finished Jan 14 02:17:25 PM PST 24
Peak memory 251236 kb
Host smart-520f362f-5f0b-45bb-8414-010ef1607159
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646182846 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.sram_ctrl_throughput_w_partial_write.3646182846
Directory /workspace/9.sram_ctrl_throughput_w_partial_write/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%