Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	299410460	1			T1	20072		T2	117964		T3	17028
instr_valid_dis	274290382	1			T1	20072		T2	117964		T3	17028
instr_en	19399977	1			T25	578542		T38	119102		T53	32

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	7594686	1			T25	218160		T38	52704		T123	8248
sram_ifetch_valid_disable	275658032	1			T1	20072		T2	117964		T3	17028
sram_ifetch_enable	16157742	1			T25	265232		T38	129110		T136	12552

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	299410460	1			T1	20072		T2	117964		T3	17028
hw_debug_en_valid_off	270836869	1			T1	20072		T2	117964		T3	17028
hw_debug_en_on	18587705	1			T25	500590		T38	103618		T136	12552

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	275658032	1			T1	20072		T2	117964		T3	17028
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	264597814	1			T1	20072		T2	117964		T3	17028
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	8800012	1			T25	270848		T38	73048		T53	32
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	3079542	1			T25	84088		T124	72		T7	79760
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1320408	1			T124	72		T7	51020		T139	54536
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1471236	1			T25	19600		T7	28740		T137	62926
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	2686772	1			T25	117306		T38	52704		T123	8248
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	983116	1			T38	6650		T123	8248		T124	33430
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1445508	1			T25	62278		T38	46054		T7	20000
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	10299806	1			T25	192256		T38	50814		T123	38256
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	6477686	1			T38	50814		T123	38256		T7	8476
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3034120	1			T25	82718		T7	40746		T137	54018

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	7120431	1			T25	224136		T123	7902		T7	238752
lc_exec_en	5601127	1			T25	191028		T38	100		T136	12552
valid_exec_dis	268257370	1			T1	20072		T2	117964		T3	17028
invalid_exec_dis	23752428	1			T25	483392		T38	181814		T136	12552