Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.67 100.00 98.27 100.00 100.00 99.71 99.70 100.00


Total tests in report: 986
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
83.45 83.45 96.72 96.72 77.20 77.20 90.72 90.72 71.43 71.43 87.90 87.90 95.84 95.84 64.35 64.35 /workspace/coverage/default/17.sram_ctrl_access_during_key_req.53285938
89.96 6.51 97.90 1.19 80.09 2.89 91.93 1.21 100.00 28.57 90.78 2.88 95.84 0.00 73.17 8.82 /workspace/coverage/default/24.sram_ctrl_stress_all.567255026
94.29 4.33 98.91 1.00 87.16 7.07 98.26 6.33 100.00 0.00 92.80 2.02 97.18 1.34 85.74 12.57 /workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.192037293
96.21 1.92 99.36 0.46 90.91 3.75 98.90 0.64 100.00 0.00 95.68 2.88 97.62 0.45 90.99 5.25 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.685718936
97.41 1.20 99.64 0.27 93.94 3.03 98.90 0.00 100.00 0.00 97.98 2.31 97.62 0.00 93.81 2.81 /workspace/coverage/default/16.sram_ctrl_mem_partial_access.931066499
98.05 0.64 99.82 0.18 96.10 2.16 99.18 0.28 100.00 0.00 98.85 0.86 98.22 0.59 94.18 0.38 /workspace/coverage/default/0.sram_ctrl_sec_cm.3029820148
98.49 0.44 99.91 0.09 97.69 1.59 99.18 0.00 100.00 0.00 99.71 0.86 98.22 0.00 94.75 0.56 /workspace/coverage/default/4.sram_ctrl_stress_all.2154448149
98.71 0.21 99.91 0.00 97.69 0.00 99.18 0.00 100.00 0.00 99.71 0.00 98.22 0.00 96.25 1.50 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1303238627
98.92 0.21 99.91 0.00 97.69 0.00 99.22 0.04 100.00 0.00 99.71 0.00 98.37 0.15 97.56 1.31 /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.752103300
99.11 0.19 99.91 0.00 97.69 0.00 99.22 0.00 100.00 0.00 99.71 0.00 98.37 0.00 98.87 1.31 /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.1294568963
99.28 0.17 99.91 0.00 97.69 0.00 99.22 0.00 100.00 0.00 99.71 0.00 99.55 1.19 98.87 0.00 /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.907552427
99.39 0.11 100.00 0.09 97.69 0.00 99.93 0.71 100.00 0.00 99.71 0.00 99.55 0.00 98.87 0.00 /workspace/coverage/default/2.sram_ctrl_ram_cfg.2144936970
99.47 0.08 100.00 0.00 97.69 0.00 99.93 0.00 100.00 0.00 99.71 0.00 99.55 0.00 99.44 0.56 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2395068917
99.53 0.05 100.00 0.00 97.98 0.29 100.00 0.07 100.00 0.00 99.71 0.00 99.55 0.00 99.44 0.00 /workspace/coverage/default/26.sram_ctrl_alert_test.4134859872
99.55 0.03 100.00 0.00 97.98 0.00 100.00 0.00 100.00 0.00 99.71 0.00 99.55 0.00 99.62 0.19 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2664239765
99.58 0.03 100.00 0.00 97.98 0.00 100.00 0.00 100.00 0.00 99.71 0.00 99.55 0.00 99.81 0.19 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1406838752
99.61 0.03 100.00 0.00 97.98 0.00 100.00 0.00 100.00 0.00 99.71 0.00 99.55 0.00 100.00 0.19 /workspace/coverage/default/0.sram_ctrl_regwen.2189107846
99.63 0.02 100.00 0.00 97.98 0.00 100.00 0.00 100.00 0.00 99.71 0.00 99.70 0.15 100.00 0.00 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.515996007

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.63717851
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.6229872
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3275608353
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2403511452
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.343942941
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2029586975
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3644593523
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.560627960
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1698929515
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3773701918
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.398120546
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3666796585
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2473092607
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1411899020
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2353483064
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2794089058
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2363368363
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.527534666
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.4116969627
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1630263235
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3197369384
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.855878840
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1021368744
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.944006017
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1079665348
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.716931300
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.740291125
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1781200280
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1101854271
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.415746590
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.341343870
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3411436651
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.517539274
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1202450485
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3391900918
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2168161253
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3619059823
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.133983930
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1903270670
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.712308193
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2042043165
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.907847730
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3891411158
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.816304752
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3501422474
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1393342140
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2928481468
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2838486959
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2215973528
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2236405537
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2934901669
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1615076882
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2586479879
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3739831863
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1710518611
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1660914782
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1159534807
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.859196246
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.4185480844
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.787195697
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1270524391
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1129622503
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3525826199
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2359999076
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1233023002
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3272034334
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3822360309
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1978850589
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1998451110
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.853090455
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2453004702
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3129408651
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.261852625
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2510173648
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3193137628
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1130432167
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3000578254
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2001884520
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.4257496961
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.925164534
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2962592072
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2228739706
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1297009468
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2668191714
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3411721266
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1663093945
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3603665577
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1420232448
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3677373175
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3135218620
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1894697666
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3696421566
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.464546752
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.48501555
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3356704425
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3334378608
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2244160361
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3609924168
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2308372168
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3826223746
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.4189222296
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1116277399
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2649211529
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3530964598
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1415107959
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.290727019
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1427782675
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3733549113
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.464190390
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1418805174
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3020877586
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.935357363
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.31442805
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1098617088
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.593139860
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3747623953
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1154335250
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.4096712959
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1621197995
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1274136936
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3554053657
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.4222804199
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2076490308
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.613666706
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1664372521
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2698107599
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3317691894
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.153557280
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.1955470390
/workspace/coverage/default/0.sram_ctrl_alert_test.383921829
/workspace/coverage/default/0.sram_ctrl_bijection.2208646122
/workspace/coverage/default/0.sram_ctrl_executable.3153043083
/workspace/coverage/default/0.sram_ctrl_max_throughput.1688058161
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.3613817657
/workspace/coverage/default/0.sram_ctrl_mem_walk.2101285111
/workspace/coverage/default/0.sram_ctrl_multiple_keys.1065246475
/workspace/coverage/default/0.sram_ctrl_partial_access.1528764046
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.1764842303
/workspace/coverage/default/0.sram_ctrl_ram_cfg.844835020
/workspace/coverage/default/0.sram_ctrl_smoke.2631827747
/workspace/coverage/default/0.sram_ctrl_stress_all.2938787222
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.170446454
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.1230141864
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.3156235280
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.1622911137
/workspace/coverage/default/1.sram_ctrl_alert_test.3680182787
/workspace/coverage/default/1.sram_ctrl_bijection.3683673391
/workspace/coverage/default/1.sram_ctrl_executable.2552579961
/workspace/coverage/default/1.sram_ctrl_max_throughput.1880073017
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.876530746
/workspace/coverage/default/1.sram_ctrl_mem_walk.2259970462
/workspace/coverage/default/1.sram_ctrl_multiple_keys.1727921631
/workspace/coverage/default/1.sram_ctrl_partial_access.1485917387
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.4239709931
/workspace/coverage/default/1.sram_ctrl_ram_cfg.3073686511
/workspace/coverage/default/1.sram_ctrl_regwen.595484178
/workspace/coverage/default/1.sram_ctrl_sec_cm.72501594
/workspace/coverage/default/1.sram_ctrl_smoke.1481726814
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.3157129268
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.1509760139
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.2395868774
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.2139634542
/workspace/coverage/default/10.sram_ctrl_alert_test.3952957846
/workspace/coverage/default/10.sram_ctrl_bijection.4261623510
/workspace/coverage/default/10.sram_ctrl_executable.3634531980
/workspace/coverage/default/10.sram_ctrl_lc_escalation.3735433778
/workspace/coverage/default/10.sram_ctrl_max_throughput.3363660139
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.4128153389
/workspace/coverage/default/10.sram_ctrl_mem_walk.4284966623
/workspace/coverage/default/10.sram_ctrl_multiple_keys.1700958920
/workspace/coverage/default/10.sram_ctrl_partial_access.2962748846
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.1888554378
/workspace/coverage/default/10.sram_ctrl_ram_cfg.2620532358
/workspace/coverage/default/10.sram_ctrl_regwen.3341889831
/workspace/coverage/default/10.sram_ctrl_smoke.1797193901
/workspace/coverage/default/10.sram_ctrl_stress_all.3079018540
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.1022164289
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.3782685531
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.502700146
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.1582083038
/workspace/coverage/default/11.sram_ctrl_alert_test.2406235463
/workspace/coverage/default/11.sram_ctrl_bijection.1291267918
/workspace/coverage/default/11.sram_ctrl_executable.1126039536
/workspace/coverage/default/11.sram_ctrl_max_throughput.48906448
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.3076626176
/workspace/coverage/default/11.sram_ctrl_mem_walk.999411212
/workspace/coverage/default/11.sram_ctrl_multiple_keys.1519579329
/workspace/coverage/default/11.sram_ctrl_partial_access.2270933769
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.984458549
/workspace/coverage/default/11.sram_ctrl_ram_cfg.3912209495
/workspace/coverage/default/11.sram_ctrl_regwen.4019553326
/workspace/coverage/default/11.sram_ctrl_smoke.235711167
/workspace/coverage/default/11.sram_ctrl_stress_all.2401535909
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.421535241
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.4212852293
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.2893032651
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.848590728
/workspace/coverage/default/12.sram_ctrl_alert_test.2166226070
/workspace/coverage/default/12.sram_ctrl_bijection.2297942794
/workspace/coverage/default/12.sram_ctrl_executable.3242272574
/workspace/coverage/default/12.sram_ctrl_lc_escalation.2124048638
/workspace/coverage/default/12.sram_ctrl_max_throughput.3598853962
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.1979528784
/workspace/coverage/default/12.sram_ctrl_mem_walk.3268220946
/workspace/coverage/default/12.sram_ctrl_multiple_keys.4074057418
/workspace/coverage/default/12.sram_ctrl_partial_access.300970750
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.1468012256
/workspace/coverage/default/12.sram_ctrl_ram_cfg.3666306119
/workspace/coverage/default/12.sram_ctrl_regwen.2920665961
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/workspace/coverage/default/45.sram_ctrl_mem_partial_access.1069726228
/workspace/coverage/default/45.sram_ctrl_mem_walk.914043788
/workspace/coverage/default/45.sram_ctrl_multiple_keys.2124879988
/workspace/coverage/default/45.sram_ctrl_partial_access.1211970792
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.3137510814
/workspace/coverage/default/45.sram_ctrl_ram_cfg.591743889
/workspace/coverage/default/45.sram_ctrl_regwen.573170581
/workspace/coverage/default/45.sram_ctrl_smoke.2060971705
/workspace/coverage/default/45.sram_ctrl_stress_all.1289746000
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.2804783935
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.3556415480
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.1327447305
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.1130996288
/workspace/coverage/default/46.sram_ctrl_alert_test.4042526961
/workspace/coverage/default/46.sram_ctrl_bijection.1197428196
/workspace/coverage/default/46.sram_ctrl_lc_escalation.2415687156
/workspace/coverage/default/46.sram_ctrl_max_throughput.1967709914
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.1579590496
/workspace/coverage/default/46.sram_ctrl_mem_walk.203627069
/workspace/coverage/default/46.sram_ctrl_multiple_keys.4252024369
/workspace/coverage/default/46.sram_ctrl_partial_access.1242806903
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.4059761670
/workspace/coverage/default/46.sram_ctrl_ram_cfg.1816037402
/workspace/coverage/default/46.sram_ctrl_regwen.3563422785
/workspace/coverage/default/46.sram_ctrl_smoke.683878140
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.2939352307
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.1077363700
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.2983636827
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.3187757561
/workspace/coverage/default/47.sram_ctrl_alert_test.3026706712
/workspace/coverage/default/47.sram_ctrl_bijection.1296607714
/workspace/coverage/default/47.sram_ctrl_lc_escalation.3717276230
/workspace/coverage/default/47.sram_ctrl_max_throughput.3177820633
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.2159298619
/workspace/coverage/default/47.sram_ctrl_mem_walk.3132141292
/workspace/coverage/default/47.sram_ctrl_multiple_keys.4234222569
/workspace/coverage/default/47.sram_ctrl_partial_access.3429304449
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.1664676905
/workspace/coverage/default/47.sram_ctrl_ram_cfg.1774153598
/workspace/coverage/default/47.sram_ctrl_regwen.3038220942
/workspace/coverage/default/47.sram_ctrl_smoke.2393571799
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.2933757553
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.3084177316
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.1189854553
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.573953248
/workspace/coverage/default/48.sram_ctrl_alert_test.1873060328
/workspace/coverage/default/48.sram_ctrl_bijection.1234417833
/workspace/coverage/default/48.sram_ctrl_lc_escalation.385759964
/workspace/coverage/default/48.sram_ctrl_max_throughput.750510401
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.835123721
/workspace/coverage/default/48.sram_ctrl_mem_walk.932517122
/workspace/coverage/default/48.sram_ctrl_multiple_keys.3467064009
/workspace/coverage/default/48.sram_ctrl_partial_access.2604636271
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.558122076
/workspace/coverage/default/48.sram_ctrl_ram_cfg.1032759784
/workspace/coverage/default/48.sram_ctrl_regwen.1015621688
/workspace/coverage/default/48.sram_ctrl_smoke.180725494
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.911446907
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.2688734502
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.4129215899
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.457098149
/workspace/coverage/default/49.sram_ctrl_alert_test.2690296456
/workspace/coverage/default/49.sram_ctrl_bijection.2477991115
/workspace/coverage/default/49.sram_ctrl_lc_escalation.3398596412
/workspace/coverage/default/49.sram_ctrl_max_throughput.2637613859
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.2006617396
/workspace/coverage/default/49.sram_ctrl_mem_walk.1954464139
/workspace/coverage/default/49.sram_ctrl_multiple_keys.271170897
/workspace/coverage/default/49.sram_ctrl_partial_access.4192609556
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.3096841444
/workspace/coverage/default/49.sram_ctrl_ram_cfg.1808124430
/workspace/coverage/default/49.sram_ctrl_regwen.2385224505
/workspace/coverage/default/49.sram_ctrl_smoke.856360153
/workspace/coverage/default/49.sram_ctrl_stress_all.2729628096
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.4215262154
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.3210825069
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.3895560071
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.2653505511
/workspace/coverage/default/5.sram_ctrl_alert_test.725658508
/workspace/coverage/default/5.sram_ctrl_bijection.390594455
/workspace/coverage/default/5.sram_ctrl_lc_escalation.1621034869
/workspace/coverage/default/5.sram_ctrl_max_throughput.3409775813
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.1074745540
/workspace/coverage/default/5.sram_ctrl_mem_walk.1809914724
/workspace/coverage/default/5.sram_ctrl_multiple_keys.156579797
/workspace/coverage/default/5.sram_ctrl_partial_access.1158318850
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.157945696
/workspace/coverage/default/5.sram_ctrl_ram_cfg.2292690687
/workspace/coverage/default/5.sram_ctrl_regwen.3390538693
/workspace/coverage/default/5.sram_ctrl_smoke.2593319934
/workspace/coverage/default/5.sram_ctrl_stress_all.3802681155
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.773719284
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.2963312861
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.727843650
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.3449789275
/workspace/coverage/default/6.sram_ctrl_alert_test.1065732837
/workspace/coverage/default/6.sram_ctrl_bijection.660358993
/workspace/coverage/default/6.sram_ctrl_executable.4186657066
/workspace/coverage/default/6.sram_ctrl_lc_escalation.2350142729
/workspace/coverage/default/6.sram_ctrl_max_throughput.3646155975
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.2230483235
/workspace/coverage/default/6.sram_ctrl_mem_walk.1351560501
/workspace/coverage/default/6.sram_ctrl_multiple_keys.1579718959
/workspace/coverage/default/6.sram_ctrl_partial_access.468071703
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.2365944334
/workspace/coverage/default/6.sram_ctrl_ram_cfg.3446763384
/workspace/coverage/default/6.sram_ctrl_regwen.3219569119
/workspace/coverage/default/6.sram_ctrl_smoke.2172148667
/workspace/coverage/default/6.sram_ctrl_stress_all.3984786994
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.3782382324
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.1509583068
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.2079727651
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.1770741619
/workspace/coverage/default/7.sram_ctrl_alert_test.320673224
/workspace/coverage/default/7.sram_ctrl_bijection.2012809398
/workspace/coverage/default/7.sram_ctrl_executable.2513927643
/workspace/coverage/default/7.sram_ctrl_max_throughput.4262336283
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.1756368256
/workspace/coverage/default/7.sram_ctrl_mem_walk.923643947
/workspace/coverage/default/7.sram_ctrl_multiple_keys.3966413525
/workspace/coverage/default/7.sram_ctrl_partial_access.126597943
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.3035195128
/workspace/coverage/default/7.sram_ctrl_ram_cfg.3997161958
/workspace/coverage/default/7.sram_ctrl_regwen.1513144943
/workspace/coverage/default/7.sram_ctrl_smoke.211502428
/workspace/coverage/default/7.sram_ctrl_stress_all.3201129100
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.240263474
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.966123824
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.1951409950
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.2395988585
/workspace/coverage/default/8.sram_ctrl_alert_test.3666418186
/workspace/coverage/default/8.sram_ctrl_bijection.1411467481
/workspace/coverage/default/8.sram_ctrl_executable.836263797
/workspace/coverage/default/8.sram_ctrl_lc_escalation.2070872481
/workspace/coverage/default/8.sram_ctrl_max_throughput.3741766237
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.1639893602
/workspace/coverage/default/8.sram_ctrl_mem_walk.3694525636
/workspace/coverage/default/8.sram_ctrl_multiple_keys.3102840835
/workspace/coverage/default/8.sram_ctrl_partial_access.2449504348
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.4042701536
/workspace/coverage/default/8.sram_ctrl_ram_cfg.1211506437
/workspace/coverage/default/8.sram_ctrl_regwen.2734227867
/workspace/coverage/default/8.sram_ctrl_smoke.2346141379
/workspace/coverage/default/8.sram_ctrl_stress_all.2570506124
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.1752967248
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.4193897008
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.3546066646
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.1286143919
/workspace/coverage/default/9.sram_ctrl_alert_test.545827277
/workspace/coverage/default/9.sram_ctrl_bijection.2423964107
/workspace/coverage/default/9.sram_ctrl_max_throughput.4192572335
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.3011425957
/workspace/coverage/default/9.sram_ctrl_mem_walk.812280299
/workspace/coverage/default/9.sram_ctrl_multiple_keys.2662493017
/workspace/coverage/default/9.sram_ctrl_partial_access.823598253
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.2149647799
/workspace/coverage/default/9.sram_ctrl_ram_cfg.3406921051
/workspace/coverage/default/9.sram_ctrl_regwen.1265297814
/workspace/coverage/default/9.sram_ctrl_smoke.2083535000
/workspace/coverage/default/9.sram_ctrl_stress_all.2520096985
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.1721228466
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.2497222302
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3450966062



Total test records in report: 986
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/35.sram_ctrl_smoke.1696756692 Jan 17 02:42:51 PM PST 24 Jan 17 02:46:09 PM PST 24 784620916 ps
T2 /workspace/coverage/default/12.sram_ctrl_bijection.2297942794 Jan 17 02:34:27 PM PST 24 Jan 17 02:52:06 PM PST 24 62261455880 ps
T3 /workspace/coverage/default/13.sram_ctrl_max_throughput.910010593 Jan 17 02:34:54 PM PST 24 Jan 17 02:36:57 PM PST 24 5036226873 ps
T10 /workspace/coverage/default/25.sram_ctrl_ram_cfg.595206659 Jan 17 02:39:55 PM PST 24 Jan 17 02:40:02 PM PST 24 1465163005 ps
T6 /workspace/coverage/default/45.sram_ctrl_max_throughput.3836391196 Jan 17 02:46:14 PM PST 24 Jan 17 02:48:49 PM PST 24 1533756736 ps
T4 /workspace/coverage/default/47.sram_ctrl_smoke.2393571799 Jan 17 02:46:46 PM PST 24 Jan 17 02:47:15 PM PST 24 3307692543 ps
T5 /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.752103300 Jan 17 02:41:00 PM PST 24 Jan 17 02:47:57 PM PST 24 23131689758 ps
T11 /workspace/coverage/default/10.sram_ctrl_alert_test.3952957846 Jan 17 02:34:00 PM PST 24 Jan 17 02:34:02 PM PST 24 18031106 ps
T12 /workspace/coverage/default/2.sram_ctrl_ram_cfg.2144936970 Jan 17 02:32:41 PM PST 24 Jan 17 02:32:56 PM PST 24 348989186 ps
T13 /workspace/coverage/default/17.sram_ctrl_access_during_key_req.53285938 Jan 17 02:36:46 PM PST 24 Jan 17 02:39:51 PM PST 24 2194437506 ps
T17 /workspace/coverage/default/29.sram_ctrl_mem_walk.2251433399 Jan 17 02:41:09 PM PST 24 Jan 17 02:43:20 PM PST 24 3873755401 ps
T14 /workspace/coverage/default/15.sram_ctrl_smoke.4079308190 Jan 17 02:35:29 PM PST 24 Jan 17 02:37:11 PM PST 24 18881836665 ps
T18 /workspace/coverage/default/23.sram_ctrl_bijection.484118539 Jan 17 02:39:14 PM PST 24 Jan 17 03:14:20 PM PST 24 253516250612 ps
T19 /workspace/coverage/default/31.sram_ctrl_stress_pipeline.1150167952 Jan 17 02:41:41 PM PST 24 Jan 17 02:45:04 PM PST 24 6001471737 ps
T23 /workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.192037293 Jan 17 02:45:24 PM PST 24 Jan 17 04:27:43 PM PST 24 1173654538 ps
T20 /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.2079727651 Jan 17 02:33:27 PM PST 24 Jan 17 02:33:54 PM PST 24 703565280 ps
T15 /workspace/coverage/default/16.sram_ctrl_mem_partial_access.931066499 Jan 17 02:36:24 PM PST 24 Jan 17 02:39:03 PM PST 24 5098150832 ps
T63 /workspace/coverage/default/33.sram_ctrl_mem_walk.211799299 Jan 17 02:42:28 PM PST 24 Jan 17 02:44:58 PM PST 24 7023023314 ps
T39 /workspace/coverage/default/41.sram_ctrl_ram_cfg.2656752200 Jan 17 02:45:01 PM PST 24 Jan 17 02:45:19 PM PST 24 367154110 ps
T21 /workspace/coverage/default/32.sram_ctrl_access_during_key_req.3038507224 Jan 17 02:42:08 PM PST 24 Jan 17 02:56:43 PM PST 24 6036719534 ps
T153 /workspace/coverage/default/11.sram_ctrl_max_throughput.48906448 Jan 17 02:34:06 PM PST 24 Jan 17 02:36:32 PM PST 24 3063918009 ps
T22 /workspace/coverage/default/17.sram_ctrl_mem_partial_access.1883624196 Jan 17 02:36:52 PM PST 24 Jan 17 02:39:16 PM PST 24 2303374326 ps
T73 /workspace/coverage/default/28.sram_ctrl_mem_partial_access.524439996 Jan 17 02:40:53 PM PST 24 Jan 17 02:43:26 PM PST 24 5054864130 ps
T24 /workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.2598297930 Jan 17 02:43:20 PM PST 24 Jan 17 03:49:13 PM PST 24 3626564820 ps
T64 /workspace/coverage/default/23.sram_ctrl_partial_access.1182336295 Jan 17 02:39:12 PM PST 24 Jan 17 02:39:58 PM PST 24 1936836704 ps
T16 /workspace/coverage/default/48.sram_ctrl_multiple_keys.3467064009 Jan 17 02:46:58 PM PST 24 Jan 17 03:03:31 PM PST 24 75017591220 ps
T65 /workspace/coverage/default/33.sram_ctrl_smoke.103048675 Jan 17 02:42:17 PM PST 24 Jan 17 02:42:39 PM PST 24 1001742299 ps
T154 /workspace/coverage/default/41.sram_ctrl_bijection.4160949938 Jan 17 02:44:56 PM PST 24 Jan 17 02:55:40 PM PST 24 9541796061 ps
T74 /workspace/coverage/default/46.sram_ctrl_mem_partial_access.1579590496 Jan 17 02:46:41 PM PST 24 Jan 17 02:47:57 PM PST 24 3804803604 ps
T26 /workspace/coverage/default/38.sram_ctrl_access_during_key_req.3492903264 Jan 17 02:43:48 PM PST 24 Jan 17 03:01:51 PM PST 24 10761845095 ps
T75 /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.493025424 Jan 17 02:34:54 PM PST 24 Jan 17 02:39:51 PM PST 24 4397824170 ps
T155 /workspace/coverage/default/2.sram_ctrl_smoke.3992813481 Jan 17 02:32:55 PM PST 24 Jan 17 02:33:25 PM PST 24 10392956466 ps
T27 /workspace/coverage/default/49.sram_ctrl_alert_test.2690296456 Jan 17 02:47:54 PM PST 24 Jan 17 02:47:56 PM PST 24 23375357 ps
T156 /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3450966062 Jan 17 02:33:53 PM PST 24 Jan 17 02:35:56 PM PST 24 5904887768 ps
T157 /workspace/coverage/default/25.sram_ctrl_mem_walk.3329786563 Jan 17 02:39:56 PM PST 24 Jan 17 02:42:20 PM PST 24 7261593626 ps
T76 /workspace/coverage/default/36.sram_ctrl_mem_partial_access.1668687298 Jan 17 02:43:20 PM PST 24 Jan 17 02:44:37 PM PST 24 3663138039 ps
T158 /workspace/coverage/default/43.sram_ctrl_bijection.2408120766 Jan 17 02:45:32 PM PST 24 Jan 17 02:56:50 PM PST 24 19036084712 ps
T119 /workspace/coverage/default/26.sram_ctrl_stress_pipeline.4207688246 Jan 17 02:40:08 PM PST 24 Jan 17 02:45:56 PM PST 24 6017595931 ps
T159 /workspace/coverage/default/32.sram_ctrl_ram_cfg.3223891261 Jan 17 02:42:08 PM PST 24 Jan 17 02:42:16 PM PST 24 3731012034 ps
T120 /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.2149647799 Jan 17 02:35:48 PM PST 24 Jan 17 02:42:32 PM PST 24 6637317026 ps
T25 /workspace/coverage/default/3.sram_ctrl_stress_all.3519265984 Jan 17 02:37:37 PM PST 24 Jan 17 03:37:43 PM PST 24 57093119360 ps
T121 /workspace/coverage/default/9.sram_ctrl_stress_pipeline.2497222302 Jan 17 02:34:26 PM PST 24 Jan 17 02:39:30 PM PST 24 18607117036 ps
T36 /workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.1754531085 Jan 17 02:33:30 PM PST 24 Jan 17 03:30:00 PM PST 24 7144165778 ps
T160 /workspace/coverage/default/8.sram_ctrl_max_throughput.3741766237 Jan 17 02:37:41 PM PST 24 Jan 17 02:38:44 PM PST 24 2696375961 ps
T82 /workspace/coverage/default/30.sram_ctrl_mem_partial_access.145620826 Jan 17 02:41:33 PM PST 24 Jan 17 02:43:52 PM PST 24 6196804011 ps
T83 /workspace/coverage/default/3.sram_ctrl_access_during_key_req.3957776847 Jan 17 02:32:59 PM PST 24 Jan 17 02:47:33 PM PST 24 36012497550 ps
T38 /workspace/coverage/default/39.sram_ctrl_executable.3640004843 Jan 17 02:44:09 PM PST 24 Jan 17 03:00:33 PM PST 24 73748241450 ps
T161 /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.2365944334 Jan 17 02:33:04 PM PST 24 Jan 17 02:38:36 PM PST 24 9413057104 ps
T162 /workspace/coverage/default/35.sram_ctrl_max_throughput.365110245 Jan 17 02:42:57 PM PST 24 Jan 17 02:44:00 PM PST 24 1140879214 ps
T56 /workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.726685533 Jan 17 02:41:41 PM PST 24 Jan 17 03:23:55 PM PST 24 459524785 ps
T57 /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.2939352307 Jan 17 02:46:39 PM PST 24 Jan 17 04:30:30 PM PST 24 507628968 ps
T37 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.63717851 Jan 17 03:52:33 PM PST 24 Jan 17 03:52:36 PM PST 24 155940674 ps
T58 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1615076882 Jan 17 03:53:28 PM PST 24 Jan 17 03:53:45 PM PST 24 1446431460 ps
T53 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.685718936 Jan 17 03:53:13 PM PST 24 Jan 17 03:53:16 PM PST 24 355940826 ps
T67 /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.907552427 Jan 17 03:53:02 PM PST 24 Jan 17 03:57:35 PM PST 24 28155523785 ps
T117 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1233023002 Jan 17 03:53:33 PM PST 24 Jan 17 03:53:35 PM PST 24 62666982 ps
T54 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2668191714 Jan 17 03:52:43 PM PST 24 Jan 17 03:52:46 PM PST 24 206815746 ps
T68 /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1894697666 Jan 17 03:52:55 PM PST 24 Jan 17 03:52:56 PM PST 24 84193866 ps
T59 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2649211529 Jan 17 03:53:00 PM PST 24 Jan 17 03:53:16 PM PST 24 1415796049 ps
T122 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1418805174 Jan 17 03:52:57 PM PST 24 Jan 17 03:52:59 PM PST 24 18626233 ps
T118 /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2228739706 Jan 17 03:52:45 PM PST 24 Jan 17 03:52:50 PM PST 24 38545123 ps
T69 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.48501555 Jan 17 03:52:58 PM PST 24 Jan 17 03:53:00 PM PST 24 15512635 ps
T55 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3197369384 Jan 17 03:53:10 PM PST 24 Jan 17 03:53:16 PM PST 24 95249990 ps
T70 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2586479879 Jan 17 03:53:31 PM PST 24 Jan 17 03:53:34 PM PST 24 32421379 ps
T60 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3644593523 Jan 17 03:52:38 PM PST 24 Jan 17 03:52:44 PM PST 24 163924768 ps
T71 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3391900918 Jan 17 03:53:26 PM PST 24 Jan 17 03:53:27 PM PST 24 14461847 ps
T66 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3501422474 Jan 17 03:53:26 PM PST 24 Jan 17 03:53:28 PM PST 24 376501820 ps
T61 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1427782675 Jan 17 03:53:00 PM PST 24 Jan 17 03:53:05 PM PST 24 28496502 ps
T72 /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.4222804199 Jan 17 03:53:07 PM PST 24 Jan 17 03:53:15 PM PST 24 39454903 ps
T81 /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.787195697 Jan 17 03:53:26 PM PST 24 Jan 17 03:54:32 PM PST 24 16802531303 ps
T105 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1202450485 Jan 17 03:53:24 PM PST 24 Jan 17 03:53:37 PM PST 24 682998559 ps
T77 /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1415107959 Jan 17 03:53:03 PM PST 24 Jan 17 03:57:34 PM PST 24 7389675294 ps
T94 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3554053657 Jan 17 03:53:08 PM PST 24 Jan 17 03:53:15 PM PST 24 32312087 ps
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T62 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2076490308 Jan 17 03:53:09 PM PST 24 Jan 17 03:53:18 PM PST 24 497000982 ps
T96 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1998451110 Jan 17 03:53:41 PM PST 24 Jan 17 03:53:44 PM PST 24 780892345 ps
T97 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.712308193 Jan 17 03:53:30 PM PST 24 Jan 17 03:53:45 PM PST 24 1374955825 ps
T98 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3525826199 Jan 17 03:53:26 PM PST 24 Jan 17 03:53:29 PM PST 24 106393792 ps
T99 /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1154335250 Jan 17 03:53:03 PM PST 24 Jan 17 03:53:05 PM PST 24 54628268 ps
T100 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3356704425 Jan 17 03:52:52 PM PST 24 Jan 17 03:52:54 PM PST 24 284728757 ps
T125 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3193137628 Jan 17 03:53:34 PM PST 24 Jan 17 03:53:44 PM PST 24 2182721408 ps
T78 /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2353483064 Jan 17 03:52:38 PM PST 24 Jan 17 03:52:42 PM PST 24 23529584 ps
T163 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3000578254 Jan 17 03:52:47 PM PST 24 Jan 17 03:52:51 PM PST 24 218113431 ps
T129 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1303238627 Jan 17 03:53:09 PM PST 24 Jan 17 03:53:16 PM PST 24 1247603045 ps
T79 /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1079665348 Jan 17 03:53:13 PM PST 24 Jan 17 03:53:15 PM PST 24 20749147 ps
T128 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2934901669 Jan 17 03:53:30 PM PST 24 Jan 17 03:53:34 PM PST 24 91726502 ps
T80 /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3272034334 Jan 17 03:53:51 PM PST 24 Jan 17 03:58:23 PM PST 24 35192614119 ps
T89 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3609924168 Jan 17 03:52:55 PM PST 24 Jan 17 03:52:56 PM PST 24 32287708 ps
T164 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1021368744 Jan 17 03:53:16 PM PST 24 Jan 17 03:53:17 PM PST 24 36391751 ps
T165 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3334378608 Jan 17 03:52:51 PM PST 24 Jan 17 03:52:52 PM PST 24 13827059 ps
T166 /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3317691894 Jan 17 03:53:08 PM PST 24 Jan 17 03:53:15 PM PST 24 91583457 ps
T167 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.464190390 Jan 17 03:53:04 PM PST 24 Jan 17 03:53:19 PM PST 24 1913072167 ps
T130 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2664239765 Jan 17 03:52:38 PM PST 24 Jan 17 03:52:43 PM PST 24 162896296 ps
T168 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.4096712959 Jan 17 03:53:06 PM PST 24 Jan 17 03:53:19 PM PST 24 145706630 ps
T169 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1297009468 Jan 17 03:52:43 PM PST 24 Jan 17 03:52:46 PM PST 24 136836535 ps
T170 /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3822360309 Jan 17 03:53:37 PM PST 24 Jan 17 03:53:42 PM PST 24 23857204 ps
T134 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1116277399 Jan 17 03:52:52 PM PST 24 Jan 17 03:52:55 PM PST 24 471892351 ps
T84 /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3020877586 Jan 17 03:52:58 PM PST 24 Jan 17 03:54:47 PM PST 24 8109877127 ps
T171 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.4257496961 Jan 17 03:52:47 PM PST 24 Jan 17 03:52:56 PM PST 24 3381694018 ps
T172 /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3891411158 Jan 17 03:53:26 PM PST 24 Jan 17 03:53:28 PM PST 24 33074870 ps
T173 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2042043165 Jan 17 03:53:29 PM PST 24 Jan 17 03:53:33 PM PST 24 23037281 ps
T174 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1129622503 Jan 17 03:53:30 PM PST 24 Jan 17 03:53:35 PM PST 24 94657951 ps
T175 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.4185480844 Jan 17 03:53:28 PM PST 24 Jan 17 03:53:32 PM PST 24 16109703 ps
T176 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2510173648 Jan 17 03:53:32 PM PST 24 Jan 17 03:53:37 PM PST 24 668831492 ps
T177 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3530964598 Jan 17 03:52:59 PM PST 24 Jan 17 03:53:02 PM PST 24 16559533 ps
T178 /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.290727019 Jan 17 03:53:00 PM PST 24 Jan 17 03:53:03 PM PST 24 22387692 ps
T85 /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2698107599 Jan 17 03:53:09 PM PST 24 Jan 17 03:58:21 PM PST 24 41297655350 ps
T107 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.859196246 Jan 17 03:53:26 PM PST 24 Jan 17 03:53:32 PM PST 24 770999966 ps
T108 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3411436651 Jan 17 03:53:14 PM PST 24 Jan 17 03:53:17 PM PST 24 72468801 ps
T109 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1406838752 Jan 17 03:53:13 PM PST 24 Jan 17 03:53:28 PM PST 24 1407747508 ps
T110 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.740291125 Jan 17 03:53:13 PM PST 24 Jan 17 03:53:16 PM PST 24 479970962 ps
T86 /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3135218620 Jan 17 03:52:47 PM PST 24 Jan 17 03:55:17 PM PST 24 16760208250 ps
T111 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1101854271 Jan 17 03:53:24 PM PST 24 Jan 17 03:53:25 PM PST 24 38138234 ps
T112 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.4189222296 Jan 17 03:52:55 PM PST 24 Jan 17 03:52:58 PM PST 24 79108931 ps
T87 /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2838486959 Jan 17 03:53:29 PM PST 24 Jan 17 03:55:58 PM PST 24 8205043879 ps
T113 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2473092607 Jan 17 03:52:39 PM PST 24 Jan 17 03:52:42 PM PST 24 53909339 ps
T88 /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2308372168 Jan 17 03:52:53 PM PST 24 Jan 17 03:55:08 PM PST 24 3792757825 ps
T93 /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.343942941 Jan 17 03:52:31 PM PST 24 Jan 17 03:55:06 PM PST 24 4449829162 ps
T179 /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.415746590 Jan 17 03:53:16 PM PST 24 Jan 17 03:55:25 PM PST 24 28174078140 ps
T180 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3275608353 Jan 17 03:52:40 PM PST 24 Jan 17 03:52:47 PM PST 24 454395140 ps
T181 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2244160361 Jan 17 03:52:59 PM PST 24 Jan 17 03:53:08 PM PST 24 347967726 ps
T106 /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.907847730 Jan 17 03:53:27 PM PST 24 Jan 17 03:55:52 PM PST 24 7578330389 ps
T182 /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.4116969627 Jan 17 03:53:10 PM PST 24 Jan 17 03:53:15 PM PST 24 42057480 ps
T101 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2001884520 Jan 17 03:52:44 PM PST 24 Jan 17 03:52:47 PM PST 24 48625264 ps
T183 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.517539274 Jan 17 03:53:16 PM PST 24 Jan 17 03:53:18 PM PST 24 238026442 ps
T184 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1630263235 Jan 17 03:53:13 PM PST 24 Jan 17 03:53:18 PM PST 24 136503658 ps
T102 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3773701918 Jan 17 03:52:38 PM PST 24 Jan 17 03:52:43 PM PST 24 393190710 ps
T135 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.464546752 Jan 17 03:52:47 PM PST 24 Jan 17 03:52:52 PM PST 24 106398090 ps
T185 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1098617088 Jan 17 03:53:04 PM PST 24 Jan 17 03:53:11 PM PST 24 1437683844 ps
T186 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3677373175 Jan 17 03:52:50 PM PST 24 Jan 17 03:52:52 PM PST 24 30617816 ps
T187 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.613666706 Jan 17 03:53:13 PM PST 24 Jan 17 03:53:19 PM PST 24 389383270 ps
T131 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2395068917 Jan 17 03:52:56 PM PST 24 Jan 17 03:52:59 PM PST 24 353817499 ps
T188 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2403511452 Jan 17 03:52:33 PM PST 24 Jan 17 03:52:39 PM PST 24 12411361 ps
T189 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.560627960 Jan 17 03:52:40 PM PST 24 Jan 17 03:52:43 PM PST 24 258255801 ps
T132 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3733549113 Jan 17 03:52:59 PM PST 24 Jan 17 03:53:04 PM PST 24 199281837 ps
T190 /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2215973528 Jan 17 03:53:25 PM PST 24 Jan 17 03:53:27 PM PST 24 27808089 ps
T191 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1664372521 Jan 17 03:53:09 PM PST 24 Jan 17 03:53:15 PM PST 24 17876303 ps
T192 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1274136936 Jan 17 03:53:08 PM PST 24 Jan 17 03:53:20 PM PST 24 445041144 ps
T193 /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3747623953 Jan 17 03:53:03 PM PST 24 Jan 17 03:53:55 PM PST 24 4193568091 ps
T194 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.31442805 Jan 17 03:53:01 PM PST 24 Jan 17 03:53:07 PM PST 24 108274939 ps
T195 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3411721266 Jan 17 03:52:54 PM PST 24 Jan 17 03:52:55 PM PST 24 40485151 ps
T114 /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2168161253 Jan 17 03:53:25 PM PST 24 Jan 17 03:56:01 PM PST 24 100496798219 ps
T196 /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3826223746 Jan 17 03:53:03 PM PST 24 Jan 17 03:53:05 PM PST 24 65288736 ps
T133 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1159534807 Jan 17 03:53:28 PM PST 24 Jan 17 03:53:32 PM PST 24 139676220 ps
T197 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1978850589 Jan 17 03:53:32 PM PST 24 Jan 17 03:53:37 PM PST 24 432712767 ps
T198 /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.341343870 Jan 17 03:53:26 PM PST 24 Jan 17 03:53:28 PM PST 24 140459390 ps
T199 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1698929515 Jan 17 03:52:40 PM PST 24 Jan 17 03:52:42 PM PST 24 85798557 ps
T200 /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1411899020 Jan 17 03:52:38 PM PST 24 Jan 17 03:55:01 PM PST 24 12373084656 ps
T201 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3666796585 Jan 17 03:52:39 PM PST 24 Jan 17 03:52:46 PM PST 24 369214629 ps
T202 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2359999076 Jan 17 03:53:31 PM PST 24 Jan 17 03:53:48 PM PST 24 386476707 ps
T203 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1130432167 Jan 17 03:52:46 PM PST 24 Jan 17 03:52:50 PM PST 24 14501501 ps
T204 /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.261852625 Jan 17 03:53:37 PM PST 24 Jan 17 03:53:42 PM PST 24 16286401 ps
T103 /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.944006017 Jan 17 03:53:12 PM PST 24 Jan 17 03:54:05 PM PST 24 28500908301 ps
T205 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.816304752 Jan 17 03:53:29 PM PST 24 Jan 17 03:53:35 PM PST 24 300694754 ps
T206 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3603665577 Jan 17 03:52:55 PM PST 24 Jan 17 03:52:56 PM PST 24 32178448 ps
T207 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.153557280 Jan 17 03:53:10 PM PST 24 Jan 17 03:53:16 PM PST 24 23866156 ps
T208 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.133983930 Jan 17 03:53:26 PM PST 24 Jan 17 03:53:28 PM PST 24 238867017 ps
T90 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.515996007 Jan 17 03:52:32 PM PST 24 Jan 17 03:52:34 PM PST 24 25657302 ps
T209 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1903270670 Jan 17 03:53:27 PM PST 24 Jan 17 03:53:29 PM PST 24 111238837 ps
T210 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1621197995 Jan 17 03:53:07 PM PST 24 Jan 17 03:53:17 PM PST 24 411167772 ps
T211 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2453004702 Jan 17 03:53:36 PM PST 24 Jan 17 03:53:42 PM PST 24 22088081 ps
T212 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2363368363 Jan 17 03:53:10 PM PST 24 Jan 17 03:53:15 PM PST 24 25443380 ps
T213 /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2029586975 Jan 17 03:52:33 PM PST 24 Jan 17 03:52:39 PM PST 24 16646415 ps
T214 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2236405537 Jan 17 03:53:27 PM PST 24 Jan 17 03:53:31 PM PST 24 157616228 ps
T215 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2928481468 Jan 17 03:53:30 PM PST 24 Jan 17 03:53:34 PM PST 24 33229564 ps
T104 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1663093945 Jan 17 03:52:48 PM PST 24 Jan 17 03:52:52 PM PST 24 351306267 ps
T216 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.6229872 Jan 17 03:52:38 PM PST 24 Jan 17 03:52:42 PM PST 24 118562966 ps
T217 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1420232448 Jan 17 03:52:55 PM PST 24 Jan 17 03:53:09 PM PST 24 366313168 ps
T218 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.855878840 Jan 17 03:53:13 PM PST 24 Jan 17 03:53:21 PM PST 24 712009745 ps
T219 /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2962592072 Jan 17 03:52:38 PM PST 24 Jan 17 03:53:41 PM PST 24 14203700849 ps
T220 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.925164534 Jan 17 03:52:44 PM PST 24 Jan 17 03:52:47 PM PST 24 32652012 ps
T221 /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1710518611 Jan 17 03:53:30 PM PST 24 Jan 17 03:53:33 PM PST 24 94183159 ps
T115 /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3129408651 Jan 17 03:53:32 PM PST 24 Jan 17 03:55:12 PM PST 24 7362539608 ps
T116 /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3739831863 Jan 17 03:53:30 PM PST 24 Jan 17 03:55:15 PM PST 24 14104605480 ps
T222 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1660914782 Jan 17 03:53:32 PM PST 24 Jan 17 03:53:37 PM PST 24 31677539 ps
T223 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3696421566 Jan 17 03:52:45 PM PST 24 Jan 17 03:52:51 PM PST 24 143023749 ps
T224 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1781200280 Jan 17 03:53:24 PM PST 24 Jan 17 03:53:32 PM PST 24 3218149220 ps
T225 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.853090455 Jan 17 03:53:35 PM PST 24 Jan 17 03:53:54 PM PST 24 1423481990 ps
T226 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.716931300 Jan 17 03:53:15 PM PST 24 Jan 17 03:53:19 PM PST 24 128594687 ps
T227 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.593139860 Jan 17 03:53:03 PM PST 24 Jan 17 03:53:05 PM PST 24 46505076 ps
T228 /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1270524391 Jan 17 03:53:25 PM PST 24 Jan 17 03:53:26 PM PST 24 31783859 ps
T229 /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.527534666 Jan 17 03:53:10 PM PST 24 Jan 17 03:54:11 PM PST 24 18485943797 ps
T230 /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.935357363 Jan 17 03:53:05 PM PST 24 Jan 17 03:53:15 PM PST 24 20052960 ps
T231 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2794089058 Jan 17 03:52:36 PM PST 24 Jan 17 03:52:43 PM PST 24 22133755 ps
T232 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.398120546 Jan 17 03:52:41 PM PST 24 Jan 17 03:52:43 PM PST 24 55988911 ps
T233 /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3619059823 Jan 17 03:53:25 PM PST 24 Jan 17 03:53:27 PM PST 24 20932280 ps
T136 /workspace/coverage/default/7.sram_ctrl_executable.2513927643 Jan 17 02:33:16 PM PST 24 Jan 17 02:35:57 PM PST 24 5976064566 ps
T28 /workspace/coverage/default/28.sram_ctrl_alert_test.1164734470 Jan 17 02:40:53 PM PST 24 Jan 17 02:40:57 PM PST 24 20074763 ps
T234 /workspace/coverage/default/34.sram_ctrl_ram_cfg.1579038170 Jan 17 02:42:42 PM PST 24 Jan 17 02:42:48 PM PST 24 1410563356 ps
T235 /workspace/coverage/default/23.sram_ctrl_multiple_keys.2240535166 Jan 17 02:39:07 PM PST 24 Jan 17 02:58:55 PM PST 24 20132921040 ps
T236 /workspace/coverage/default/1.sram_ctrl_access_during_key_req.1622911137 Jan 17 02:32:37 PM PST 24 Jan 17 02:41:49 PM PST 24 27453014884 ps
T237 /workspace/coverage/default/21.sram_ctrl_stress_pipeline.1899019102 Jan 17 02:38:33 PM PST 24 Jan 17 02:42:51 PM PST 24 12943711503 ps
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