Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	125224351	1			T1	9119		T2	589824		T3	8514
triple_byte_access	2632633	1			T1	177		T4	186		T5	38745
halfword_access	4055274	1			T1	263		T4	270		T5	58147
byte_access	5691087	1			T1	380		T4	391		T5	76986
zero_access	1747885	1			T1	97		T4	88		T5	18998

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

69101618

1

T1

4959

T2

294912

T3

4231

auto[1]

70249612

1

T1

5077

T2

294912

T3

4283

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	61926494	1			T1	4512		T2	294912		T3	4231
auto[0]	triple_byte_access	1243656	1			T1	89		T4	93		T5	19418
auto[0]	halfword_access	1967229	1			T1	126		T4	127		T5	29199
auto[0]	byte_access	2910746	1			T1	191		T4	193		T5	38748
auto[0]	zero_access	1053493	1			T1	41		T4	34		T5	9555
auto[1]	word_access	63297857	1			T1	4607		T2	294912		T3	4283
auto[1]	triple_byte_access	1388977	1			T1	88		T4	93		T5	19327
auto[1]	halfword_access	2088045	1			T1	137		T4	143		T5	28948
auto[1]	byte_access	2780341	1			T1	189		T4	198		T5	38238
auto[1]	zero_access	694392	1			T1	56		T4	54		T5	9443